CN114199519B - Testing device and system - Google Patents
Testing device and system Download PDFInfo
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- CN114199519B CN114199519B CN202111278956.4A CN202111278956A CN114199519B CN 114199519 B CN114199519 B CN 114199519B CN 202111278956 A CN202111278956 A CN 202111278956A CN 114199519 B CN114199519 B CN 114199519B
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- 238000012360 testing method Methods 0.000 title claims abstract description 72
- 230000003111 delayed effect Effects 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims description 54
- 230000000087 stabilizing effect Effects 0.000 claims description 23
- 239000013078 crystal Substances 0.000 claims description 19
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000001914 filtration Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
- G01M11/00—Testing of optical apparatus; Testing structures by optical methods not otherwise provided for
- G01M11/02—Testing optical properties
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
- G01M11/00—Testing of optical apparatus; Testing structures by optical methods not otherwise provided for
- G01M11/02—Testing optical properties
- G01M11/04—Optical benches therefor
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- Chemical & Material Sciences (AREA)
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a testing device and a testing system, wherein the testing device comprises: the device comprises a first clock signal output end, a second clock signal output end, a clock signal module and a clock signal delay module; the clock signal module is electrically connected with the first clock signal output end, and the clock signal delay module is electrically connected with the second clock signal output end; the clock signal output by the second clock signal output end is delayed than the clock signal output by the first clock signal output end.
Description
Technical Field
The present invention relates to the field of testing, and in particular, to a testing device and system.
Background
OIS (Optical Image Stabilization) optical anti-shake realizes the compensation of the shake direction of the lens and the camera body through a physical technology, reduces the image blurring effect caused by shake when shooting images, and improves the shooting quality. Along with the gradual upgrade of the camera module, the OIS function becomes more and more 'standard' of the camera module, and it is important to test the quality of the OIS function. However, the existing OIS test fixture cannot meet the time sequence requirements of the OIS driving IC and the photosensitive chip at the same time, so that the production test result of the finished OIS module is inaccurate, and the high reject ratio is further caused.
Disclosure of Invention
According to the test device and the test system, the technical problem that the test device in the prior art cannot meet the time sequence requirements of the OIS driving IC and the photosensitive chip simultaneously is solved, the test accuracy is improved, and the technical effect of yield is improved.
On the one hand, the present application provides the following technical solutions through an embodiment of the present application:
a test apparatus comprising:
the device comprises a first clock signal output end, a second clock signal output end, a clock signal module and a clock signal delay module;
the clock signal module is electrically connected with the first clock signal output end, and the clock signal delay module is electrically connected with the second clock signal output end;
the clock signal output by the second clock signal output end is delayed than the clock signal output by the first clock signal output end.
Optionally, the clock signal delay module includes:
a voltage stabilizing circuit and a clock circuit;
the input end of the voltage stabilizing circuit is electrically connected with the power supply end, the output end of the voltage stabilizing circuit is electrically connected with the input end of the clock circuit, and the output end of the clock circuit is electrically connected with the second clock signal output end;
the voltage stabilizing circuit is used for providing a stable voltage signal for the clock circuit, and the clock circuit is used for delaying the output clock signal.
Optionally, the voltage stabilizing circuit includes:
a low dropout linear voltage regulator, a first capacitor, a second capacitor and a third capacitor;
the first pin and the third pin of the low dropout linear voltage regulator are electrically connected with a power supply end and one end of the first capacitor, and the other end of the first capacitor is digitally grounded; the second pin of the low dropout linear regulator is grounded in a digital manner; the fifth pin of the low dropout linear voltage regulator is electrically connected with one end of the second capacitor, and the other end of the second capacitor is digitally grounded; and a fourth pin of the low dropout linear voltage regulator is respectively and electrically connected with one end of the third capacitor and the input end of the clock circuit, and the other end of the third capacitor is grounded digitally.
Optionally, the resistance of the first capacitor is 1uF, the resistance of the second capacitor is 0.01uF, and the resistance of the third capacitor is 1uF.
Optionally, the clock circuit includes:
a crystal oscillator and a fourth capacitor;
the first pin of the crystal oscillator is electrically connected with the output end of the voltage stabilizing circuit; the second pin of the crystal oscillator is grounded digitally; the third pin of the crystal oscillator is electrically connected with the second clock signal output end; and a fourth pin of the crystal oscillator is respectively and electrically connected with one end of the fourth capacitor and the output end of the voltage stabilizing circuit, and the other end of the fourth capacitor is digitally grounded.
Optionally, the resistance of the fourth capacitor is 0.01uF.
On the other hand, the application provides the following technical scheme through an embodiment of the application:
a test system, comprising:
the device comprises a testing device and equipment to be tested;
the first clock signal output end of the testing device is electrically connected with the first chip of the equipment to be tested, and the second clock signal output end of the testing device is electrically connected with the second chip of the equipment to be tested;
the clock signal output by the second clock signal output end is delayed than the clock signal output by the first clock signal output end.
Optionally, the device to be tested is a camera module; the first chip is a photosensitive chip; the second chip is a driving chip.
Optionally, the testing device synchronously outputs a power signal and a reset signal of 2.8V,1.8V and 1.1V to the photosensitive chip, and synchronously outputs a clock signal to the driving chip through the first clock signal output end; the testing device synchronously outputs 2.8V,1.8V and 1.1V power signals to the driving chip, outputs clock signals to the driving chip through the second clock signal output end, and finally outputs reset signals to the driving chip.
One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:
the embodiment of the invention discloses a testing device and a testing system, comprising: the device comprises a first clock signal output end, a second clock signal output end, a clock signal module and a clock signal delay module; the clock signal module is electrically connected with the first clock signal output end, and the clock signal delay module is electrically connected with the second clock signal output end. Based on the difference of the clock signals output by the clock signal module and the clock signal delay module, the testing device can output two clock signals with different time sequences through the two clock signal output ends. The clock signal output by the second clock signal output end is delayed compared with the clock signal output by the first clock signal output end, so that the power supply requirement of a chip needing to delay the clock signal can be met. Therefore, the technical problem that the testing device in the prior art cannot meet the time sequence requirements of the OIS driving IC and the photosensitive chip at the same time is solved, the testing accuracy is improved, and the technical effect of yield is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a testing device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a clock signal delay module according to an embodiment of the invention;
FIG. 3 is a circuit diagram of a voltage stabilizing circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a clock circuit according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a test system according to an embodiment of the present invention;
FIG. 6 is a timing diagram illustrating an embodiment of the present invention;
FIG. 7 is a timing diagram illustrating a second embodiment of the present invention.
Detailed Description
According to the test device and the test system, the technical problem that the test device in the prior art cannot meet the time sequence requirements of the OIS driving IC and the photosensitive chip simultaneously is solved, the test accuracy is improved, and the technical effect of yield is improved.
The technical scheme of the embodiment of the application aims to solve the technical problems, and the overall thought is as follows:
a test apparatus comprising:
the device comprises a first clock signal output end, a second clock signal output end, a clock signal module and a clock signal delay module;
the clock signal module is electrically connected with the first clock signal output end, and the clock signal delay module is electrically connected with the second clock signal output end;
the clock signal output by the second clock signal output end is delayed than the clock signal output by the first clock signal output end.
In order to better understand the above technical solutions, the following detailed description will refer to the accompanying drawings and specific embodiments.
First, the term "and/or" appearing herein is merely an association relationship describing associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
Example 1
As shown in fig. 1, there is provided a test apparatus 100 including:
a first clock signal output 110, a second clock signal output 120, a clock signal module 130, and a clock signal delay module 140;
the clock signal module 130 is electrically connected to the first clock signal output terminal 110, and the clock signal delay module 140 is electrically connected to the second clock signal output terminal 120;
wherein the clock signal output from the second clock signal output terminal 120 is delayed from the clock signal output from the first clock signal output terminal 110.
It should be noted that, the clock signal delay module 140 may be a separate plug-in module or an integrated module, which is not limited herein.
In an alternative embodiment, as shown in fig. 2, the clock signal delay module 140 includes: a voltage stabilizing circuit 141 and a clock circuit 142; the input end of the voltage stabilizing circuit 141 is electrically connected with the power supply end AVDD, the output end of the voltage stabilizing circuit 141 is electrically connected with the input end of the clock circuit 142, and the output end of the clock circuit 142 is electrically connected with the second clock signal output end 120; the voltage stabilizing circuit 141 is configured to provide a stable voltage signal to the clock circuit 142, and the clock circuit 142 is configured to delay the output clock signal.
In the implementation process, as shown in fig. 3, the voltage stabilizing circuit 141 includes: the low dropout linear regulator U1, the first capacitor C1, the second capacitor C2 and the third capacitor C3. Wherein the low dropout regulator U1 can maintain a prescribed output voltage over a wide load current and input voltage range, and the difference between the input and output voltages can be small. The capacitor of the voltage stabilizing circuit is used for filtering noise and controlling load transient variation. The larger the values of the capacitor C1 and the capacitor C2, the better the transient response performance of the low dropout linear regulator U1, and the longer the start-up time. Therefore, the start time can be set by setting the capacitors C1 and C2 of different sizes, thereby delaying the output signal to the clock circuit. Optionally, the resistance of the first capacitor is 1uF, the resistance of the second capacitor is 0.01uF, and the resistance of the third capacitor is 1uF.
Specifically, the first pin 1U and the third pin 3U of the low dropout linear regulator U1 are electrically connected to the power supply terminal AVDD and one end of the first capacitor C1, and the other end of the first capacitor C1 is digitally grounded; the second pin 2U of the low dropout linear regulator U1 is digitally grounded; the fifth pin 5U of the low dropout linear regulator U1 is electrically connected with one end of the second capacitor C2, and the other end of the second capacitor C2 is digitally grounded; the fourth pin 4U of the low dropout linear regulator U1 is electrically connected to one end of the third capacitor C3 and the input terminal VDD of the clock circuit, respectively, and the other end of the third capacitor C3 is digitally grounded.
In an alternative embodiment, as shown in fig. 4, the clock circuit 142 includes: a crystal oscillator X1 and a fourth capacitor C4. The capacitor C4 is used for filtering, so that the crystal oscillator X1 obtains a pure power supply without ac components. Optionally, the resistance of the fourth capacitor is 0.01uF, so that a stable power supply can be obtained. Of course, the resistance of the fourth capacitor may also be selected to be different based on the filtering requirement of the crystal oscillator X1, which is not limited in this embodiment. The crystal oscillator X1 is used for outputting the clock frequency required by the tested chip, and different crystal oscillators can be used based on the requirements of the tested chip, which is not limited in this embodiment.
Specifically, a first pin 1X of the crystal oscillator is electrically connected with an output end VDD of the voltage stabilizing circuit; the second pin 2X of the crystal oscillator is digitally grounded; the third pin 3X of the crystal oscillator X1 is electrically connected to the second clock signal output end 120; the fourth pin 4X of the crystal oscillator X1 is electrically connected to one end of the fourth capacitor C4 and the output terminal VDD of the voltage stabilizing circuit, respectively, and the other end of the fourth capacitor C4 is digitally grounded.
Example two
As shown in fig. 5, there is provided a test system 400 comprising: a testing device 100 and a device under test 200; the first clock signal output end 110 of the testing device is electrically connected with the first chip 210 of the device under test, and the second clock signal output end 120 of the testing device is electrically connected with the second chip 220 of the device under test; the clock signal output by the second clock signal output end is delayed than the clock signal output by the first clock signal output end.
In an alternative embodiment, the device under test 200 is a camera module, and the first chip 210 is a photosensitive chip; the second chip 220 is a driving chip. Of course, the device under test 200 may be a screen panel, the first chip 210 may be an infrared chip, and the second chip 220 may be a display chip, which is not limited in this embodiment.
In an alternative embodiment, the testing device synchronously outputs a power signal and a reset signal of 2.8V,1.8V and 1.1V to the photosensitive chip, and synchronously outputs a clock signal to the driving chip through the first clock signal output terminal 110; the test device synchronously outputs 2.8V,1.8V and 1.1V power signals to the driving chip, outputs a clock signal to the driving chip through the second clock signal output end 120, and finally outputs a reset signal to the driving chip.
In a specific implementation process, the 2.8V,1.8V, and 1.1V power signals and the reset signals can be output through different interfaces in the same port. Of course, the power signals of 2.8V,1.8V and 1.1V and the reset signal may be output through different ports, which is not limited in this embodiment. Since the test system described in this embodiment is a test system used for implementing the test device in this embodiment, based on the test device described in this embodiment, those skilled in the art can understand the specific implementation of the test system in this embodiment and various modifications thereof, so how the test system implements the method in this embodiment will not be described in detail herein. The test system used by the test device in the embodiments of the present application is within the scope of the protection sought by the present application, as long as those skilled in the art implement the test system.
A specific example is provided below in connection with fig. 6-7 to aid in understanding the apparatus and systems provided herein:
the first clock signal output 110 of the test device 100 is electrically connected to the photosensitive chip of the device under test 200, and the second clock signal output 120 of the test device 100 is electrically connected to the driving chip of the device under test 200. The power-up timing sequence of the photosensitive chip is shown in fig. 6, wherein 2.8v,1.8v, and 1.1v (VANA 1, VANA2, VIF, and VDIG in fig. 6 are corresponding voltage signals) can be synchronously output with the reset signal reset and the clock signal CLK. The power-on sequence of the driving chip is shown in fig. 7, wherein 2.8v,1.8v and 1.1v (VDD, VCC, VM in fig. 6 is a corresponding voltage signal) can be synchronously output, and then the clock signal CLK is output, and finally the Reset signal Reset is output. Namely, the testing device synchronously outputs 2.8V,1.8V and 1.1V power signals and reset signals to the photosensitive chip, and synchronously outputs clock signals to the driving chip through the first clock signal output end 110; the testing device synchronously outputs 2.8V,1.8V and 1.1V power signals to the driving chip, delays the second clock signal output end 120 to output a clock signal to the driving chip through the clock signal delay module 140, and finally outputs a reset signal to the driving chip.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
the embodiment of the invention discloses a testing device and a testing system, comprising: the device comprises a first clock signal output end, a second clock signal output end, a clock signal module and a clock signal delay module; the clock signal module is electrically connected with the first clock signal output end, and the clock signal delay module is electrically connected with the second clock signal output end. Based on the difference of the clock signals output by the clock signal module and the clock signal delay module, the testing device can output two clock signals with different time sequences through the two clock signal output ends. The clock signal output by the second clock signal output end is delayed compared with the clock signal output by the first clock signal output end, so that the power supply requirement of a chip needing to delay the clock signal can be met. Therefore, the technical problem that the testing device in the prior art cannot meet the time sequence requirements of the OIS driving IC and the photosensitive chip at the same time is solved, the testing accuracy is improved, and the technical effect of yield is further improved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. A test device, comprising:
the device comprises a first clock signal output end, a second clock signal output end, a clock signal module and a clock signal delay module;
the clock signal module is electrically connected with one end of the first clock signal output end, the other end of the first clock signal output end is electrically connected with a first chip of equipment to be tested, the equipment to be tested is a camera module, and the first chip is a photosensitive chip; the clock signal delay module is electrically connected with one end of the second clock signal output end, the other end of the second clock signal output end is electrically connected with a second chip of the equipment to be tested, and the second chip is a driving chip;
the clock signal output by the second clock signal output end is delayed than the clock signal output by the first clock signal output end.
2. The apparatus of claim 1, wherein the clock signal delay module comprises:
a voltage stabilizing circuit and a clock circuit;
the input end of the voltage stabilizing circuit is electrically connected with the power supply end, the output end of the voltage stabilizing circuit is electrically connected with the input end of the clock circuit, and the output end of the clock circuit is electrically connected with the second clock signal output end;
the voltage stabilizing circuit is used for providing a stable voltage signal for the clock circuit, and the clock circuit is used for delaying the output clock signal.
3. The apparatus of claim 2, wherein the voltage stabilizing circuit comprises:
a low dropout linear voltage regulator, a first capacitor, a second capacitor and a third capacitor;
the first pin and the third pin of the low dropout linear voltage regulator are electrically connected with a power supply end and one end of the first capacitor, and the other end of the first capacitor is digitally grounded; the second pin of the low dropout linear regulator is grounded in a digital manner; the fifth pin of the low dropout linear voltage regulator is electrically connected with one end of the second capacitor, and the other end of the second capacitor is digitally grounded; and a fourth pin of the low dropout linear voltage regulator is respectively and electrically connected with one end of the third capacitor and the input end of the clock circuit, and the other end of the third capacitor is grounded digitally.
4. A device as claimed in claim 3, comprising:
the resistance of the first capacitor is 1uF, the resistance of the second capacitor is 0.01uF, and the resistance of the third capacitor is 1uF.
5. The apparatus of claim 2, wherein the clock circuit comprises:
a crystal oscillator and a fourth capacitor;
the first pin of the crystal oscillator is electrically connected with the output end of the voltage stabilizing circuit; the second pin of the crystal oscillator is grounded digitally; the third pin of the crystal oscillator is electrically connected with the second clock signal output end; and a fourth pin of the crystal oscillator is respectively and electrically connected with one end of the fourth capacitor and the output end of the voltage stabilizing circuit, and the other end of the fourth capacitor is digitally grounded.
6. The apparatus of claim 5, characterized in that it comprises:
the resistance of the fourth capacitor is 0.01uF.
7. A test system, comprising:
the device comprises a testing device and equipment to be tested;
the first clock signal output end of the testing device is electrically connected with a first chip of the equipment to be tested, the equipment to be tested is a camera module, and the first chip is a photosensitive chip; the second clock signal output end of the testing device is electrically connected with a second chip of the equipment to be tested, and the second chip is a driving chip;
the clock signal output by the second clock signal output end is delayed than the clock signal output by the first clock signal output end.
8. The system of claim 7, wherein:
the testing device synchronously outputs 2.8V,1.8V and 1.1V power signals and reset signals to the photosensitive chip, and synchronously outputs clock signals to the photosensitive chip through the first clock signal output end;
the testing device synchronously outputs 2.8V,1.8V and 1.1V power signals to the driving chip, outputs clock signals to the driving chip through the second clock signal output end, and finally outputs reset signals to the driving chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111278956.4A CN114199519B (en) | 2021-10-31 | 2021-10-31 | Testing device and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111278956.4A CN114199519B (en) | 2021-10-31 | 2021-10-31 | Testing device and system |
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| CN114199519A CN114199519A (en) | 2022-03-18 |
| CN114199519B true CN114199519B (en) | 2024-04-16 |
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| Publication number | Publication date |
|---|---|
| CN114199519A (en) | 2022-03-18 |
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