CN109493782A - Signal correction controller, signal correction control method and display device - Google Patents
Signal correction controller, signal correction control method and display device Download PDFInfo
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- CN109493782A CN109493782A CN201811556308.9A CN201811556308A CN109493782A CN 109493782 A CN109493782 A CN 109493782A CN 201811556308 A CN201811556308 A CN 201811556308A CN 109493782 A CN109493782 A CN 109493782A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
This application involves a kind of signal correction controller, signal correction control method and display devices.Wherein, signal correction controller includes: detecting phase module and phase correction module, the input terminal of detecting phase module is used to connect the bus of display device, the input terminal of the output end connection phase correction module of detecting phase module, the output end of phase correction module are used to connect the driving circuit of display device；Detecting phase module is used to obtain clock signal in bus and data-signal and the first phase potential difference for exporting clock signal and data-signal；It is target phase difference that phase correction module, which is used to adjust clock signal and the phase difference of data-signal according to first phase potential difference and preset exemplary voltages,.Avoid because phase difference is excessive or it is too small caused by data are written when the mistake that occurs to improve the reliability and accuracy of write-in data be further conducive to improve display image quality.
Description
Technical field
The present invention relates to signal processing technology fields, control more particularly to a kind of signal correction controller, signal correction
Method and display device.
Background technique
In display field, in order to control voltage signal or enable signal, to guarantee the display of display, frequently with
I2C bus (Inter-Integrated Circuit, IC bus) is to the integrated circuit for driving display to show
It carries out writing data realization.But inventor in the implementation process, it was found that, when carrying out writing data in example technique, often will appear data
Write error causes to generate malfunction, and then influences display effect.
Summary of the invention
Based on this, it is necessary to write in example technique data be easy error aiming at the problem that, a kind of signal correction control is provided
Device, signal correction control method and display device processed.
On the one hand, the embodiment of the invention provides a kind of signal correction controllers, comprising: detecting phase module and phase school
Positive module, the input terminal of detecting phase module are used to connect the bus of display device, and the output end of detecting phase module connects phase
The input terminal of bit correction module, the output end of phase correction module are used to connect the driving circuit of display device；
Detecting phase module be used to obtain clock signal in bus and data-signal and export clock signal sum number it is believed that
Number first phase potential difference；
Phase correction module is used to adjust clock signal and data according to first phase potential difference and preset exemplary voltages
The phase difference of signal is target phase difference.
Detecting phase module includes phase discriminator in one of the embodiments, and the input terminal of phase discriminator is for connecting display
The bus of device, the input terminal of the output end connection phase correction module of phase discriminator.
Phase correction module includes voltage comparator and phase delay unit in one of the embodiments,；Voltage compares
The reference end of device is for accessing exemplary voltages；
The output end of the input terminal connection phase discriminator of voltage comparator, the output end and phase delay unit of voltage comparator
Connection, voltage comparator export comparison result signal for comparing first phase potential difference and exemplary voltages；
The output end of phase delay unit is used to connect the driving circuit of display device, phase delay unit be used for according to than
The phase difference that clock signal and data-signal are adjusted compared with consequential signal is target phase difference.
Phase correction module further includes charge pump in one of the embodiments, the input terminal of charge pump and phase discriminator
Output end connection, the output end of charge pump and the input terminal of voltage comparator connect, and charge pump is used for first phase potential difference
Second phase potential difference is converted to, voltage comparator exports for comparing second phase potential difference and exemplary voltages and compares knot
Fruit signal.
The bus of display device is I2C bus in one of the embodiments,.
A kind of signal correction control method, comprising:
Obtain clock signal and data-signal；
According to the clock signal and data-signal of acquisition, the first phase potential difference of clock signal and data-signal is obtained；
According to first phase potential difference and preset exemplary voltages, the phase difference for adjusting clock signal and data-signal is mesh
Phase difference is marked, data-signal adjusted is enable to be correctly written in driving circuit.
Signal correction control method further comprises the steps of: in one of the embodiments,
Clock signal and data-signal adjusted after output adjustment are to driving circuit.
In one of the embodiments, according to first phase potential difference and preset exemplary voltages, adjust clock signal and
The phase difference of data-signal be target phase difference the step of include:
According to first phase potential difference and exemplary voltages, comparison result signal is obtained；
According to comparison result signal, clock signal is adjusted, so that the phase difference of clock signal adjusted and data-signal
For target phase difference.
In one of the embodiments, according to first phase potential difference and exemplary voltages, the step of comparison result signal is obtained
Suddenly include:
According to first phase potential difference, second phase potential difference is obtained；
According to second phase potential difference and exemplary voltages, comparison result signal is obtained.
In one of the embodiments, according to comparison result signal, the step of adjusting clock signal, includes:
If comparison result signal is greater than exemplary voltages, reduce according to comparison result signal is corresponding with the difference of exemplary voltages
The phase of clock signal；
If comparison result signal is less than exemplary voltages, increase according to exemplary voltages are corresponding with the difference of comparison result signal
The phase of clock signal.
A kind of display device, including display panel, bus, driving circuit and above-mentioned signal correction controller, bus and letter
The input terminal connection of number correcting controller, the output end of signal correction controller are connect with driving circuit input terminal, driving circuit
The first output end connect with the scan line on display panel, the data line in the second output terminal and display panel of driving circuit
Connection.
One or more embodiment provided by the invention at least has the advantages that the embodiment of the invention provides one
Kind signal correction controller, detecting phase module therein acquire, detect the clock signal and data-signal of display device bus
And the phase difference of the two exports first phase potential difference, phase correction module is according to the first phase potential difference got and in advance
If exemplary voltages, the phase difference for adjusting clock signal and data-signal is target phase difference so that clock signal sum number it is believed that
The requirement that number can meet bus signal transmission, avoid because phase difference is excessive or it is too small caused by data are written when the mistake that occurs
Accidentally, to improve the reliability and accuracy of write-in data, be further conducive to improve display image quality.
Detailed description of the invention
Fig. 1 is the time diagram of clock signal and data-signal in bus in an example technique；
Fig. 2 is the structural schematic diagram of signal correction controller in one embodiment；
Fig. 3 is the structural schematic diagram of signal correction controller in another embodiment；
Fig. 4 is the flow diagram of signal correction control method in one embodiment；
Fig. 5 is the flow diagram of signal correction control method in another embodiment；
Fig. 6 is to adjust clock signal sum number according to first phase potential difference and preset exemplary voltages in one embodiment
It is believed that number phase difference be target phase difference step flow diagram；
Fig. 7 is to obtain comparison result signals step according to first phase potential difference and exemplary voltages in another embodiment
Flow diagram；
Fig. 8 is to adjust the flow diagram of clock signal step according to comparison result signal in further embodiment；
Fig. 9 is the structural block diagram of display device in one embodiment.
Specific embodiment
To facilitate the understanding of the present invention, a more comprehensive description of the invention is given in the following sections with reference to the relevant attached drawings.In attached drawing
Give preferred embodiment of the invention.But the invention can be realized in many different forms, however it is not limited to this paper institute
The embodiment of description.On the contrary, purpose of providing these embodiments is make it is more thorough and comprehensive to the disclosure.
It should be noted that it can be directly to separately when an element is considered as " connection " another element
One element and it is in combination be integrated, or may be simultaneously present centering elements.Term as used herein " installation ", " one
End ", " other end " and similar statement are for illustrative purposes only.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term " and or " used herein includes one or more phases
Any and all combinations of the listed item of pass.
It needs to control voltage signal or enable signal, at present to realize normal display in field of display technology
Write-in data are carried out to driving circuit frequently with I2C bus to realize.But in actual operation, due to external disturbance, I2C bus
Clock signal SCL and data-signal SDA in signal can generate phase difference, lead to mistake occur when data are written, final to generate
Malfunction, causes display effect poor.
For example, being as shown in Figure 1 the waveform of the clock signal SCL and data-signal SDA of I2C bus signals, SCL is I2C
The clock signal of bus signals, SDA are the data-signals of I2C bus signals.When carrying out write-in data to driving circuit, driving
Circuit can carry out the write-in of data according to the timing of clock signal SCL and according to I2C agreement.As shown in Figure 1, the t in diagram is
The settling time (setup time) of data write-in, wherein settling time referred to before rising edge clock signal arrival, data
Stablize the constant time.Obviously, if settling time is inadequate, the data that data-signal carries cannot be in this rising edge clock
It is normally written when arrival.Correctly write-in data, settling time t, which such as can be write, to driving circuit has to comply with I2C agreement
It is required that.But in actual operation, settling time t is often influenced by external interference signal, and t is caused not meet I2C agreement
Requirement so that write-in data when there is write error.
The embodiment of the present invention provides a kind of signal correction controller, as shown in Figure 2, comprising: detecting phase module 10 and phase
Bit correction module 20, the input terminal of detecting phase module 10 are used to connect the bus 30 of display device, detecting phase module 10
Output end connects the input terminal of phase correction module 20, and the output end of phase correction module 20 is used to connect the driving of display device
Circuit 40；Detecting phase module 10 is used to obtain the clock signal and data-signal in bus 30 and exports clock signal and data
The first phase potential difference of signal；Phase correction module 20 is used to be adjusted according to first phase potential difference and preset exemplary voltages
The phase difference of whole clock signal and data-signal is target phase difference.
Wherein, detecting phase module 10 refers to the module with signal acquisition and phase identification, for example, detecting phase module
10 may include phase discriminator 11 etc..Phase correction module 20 refers to the module with signal processing and phase adjustment function.Clock
Signal refer to each sub-pixel for controlling in display device whether start be written data signal, data-signal refer to for
When clock signal meets write-in data demand, the signal of each sub-pixel display brightness in display device is driven.Preset typical case
Voltage refers to voltage value corresponding to the phase difference for meeting 30 request signal transmission of bus.Target phase difference can be for characterizing
Clock signal and the phase relation of data-signal can satisfy the phase difference of the request signal transmission of bus 30.The drive of display device
Dynamic circuit 40 refers to the circuit for driving each sub-pixel in display device to be shown.For example, driving circuit 40 can be with
Including shift register and scan line, the input terminal of shift register is connect with the output end of phase correction module 20, for obtaining
Take clock signal adjusted, and the opening through the corresponding active array switch of each sub-pixel of each scanning line driving by scanning signal
It opens.Driving circuit 40 can also include data line, and the data-signal of the output end output of driving circuit 40 is transmitted by data line
To the pixel electrode of each sub-pixel, pixel voltage is formed between pixel electrode and public electrode, liquid crystal deflection is driven, so that sub
Pixel is shown.
In actual operation, due to external disturbance, the clock signal SCL and data-signal SDA in 30 signal of bus can be produced
Raw phase difference will lead to write-in number if the settling time (setup time) that phase difference is unsatisfactory in the transmission of bus 30 requires
According to when there is mistake, final to generate malfunction, display effect is poor.In order to solve this problem, inventor uses detecting phase module
10 obtain and detect the clock signal in bus 30 and the first phase potential difference between data-signal, first then will obtained
Phase voltage is transmitted to phase correction module 20, and phase correction module 20 is according to the first phase potential difference got and in advance
If exemplary voltages, measure current phase difference whether meet bus 30 transmission requirement, if not meeting, according to first phase
Potential difference and preset exemplary voltages, the phase difference between corresponding adjustment clock signal and data-signal, arrive adjusting offset
Target phase difference guarantees number so that the data stabilization constant time can satisfy requirement before rising edge clock signal arrives
It is written into according in this rising edge clock, carries out display driving.
In one of the embodiments, as shown in figure 3, detecting phase module 10 include phase discriminator 11, phase discriminator 11 it is defeated
Enter to hold the bus 30 for connecting display device, the input terminal of the output end connection phase correction module 20 of phase discriminator 11.
Wherein, phase discriminator 11 (phasedetector) refers to identify the device of the phase difference of input signal, is
The phase difference between output voltage and two input signals is set to have the circuit of determining relationship.
Specifically, phase discriminator 11 obtains the clock signal and data-signal of bus 30, by processing, two signals are exported
First phase potential difference is to phase correction module 20, and then, phase correction module 20 is according to the first phase potential difference got
Difference between exemplary voltages, it can be determined that whether the phase difference of clock signal and data-signal that bus 30 exports meets always
The settling time of line 30 requires, and adjusts the phase difference between two signals according to difference, guarantees the phase difference between two signals
Meet the transmission requirement of bus 30.
During the adjustment, it can be realized by the phase adjustment to clock signal to phase difference between two signals
Adjustment.For example, phase discriminator 11 after receiving clock signal and data-signal, if data-signal is ahead of clock signal, reflects
Phase device 11 can produce so that its internal counter counting permission signal, starts in data-signal rising edge to corresponding clock
During signal rising edge arrives, high level is kept, after counting, exports first phase potential difference corresponding with count results extremely
Phase correction module 20, then phase correction module 20 can adjust the phase of clock signal, the pass according to preset relation table
It is phase mass of the table for phase difference and to the clock signal in requisition for adjustment.Specific adjustment, which is realized, can be by adjusting clock letter
Resistance etc. in number generation circuit, realizes phase adjustment.Phase-locked loop pll can also be utilized to the phase adjustment realization of clock signal
Phase adjustment function, generate the out of phase of several clocks, phase correction module 20 is according to the first phase difference received
Relationship between voltage and exemplary voltages judges which phase can accurately collect data-signal, then takes among window
One clock phase, as clock signal when working normally.For example, generating 0,45,90,135 by PLL ... ..., 315 degree 8
The clock of a phase shift can then choose intermediate phase if the clock signal of 0,45,90 degree of phase shift can correctly sample input,
The clock signal of i.e. 45 degree phase shifts is as clock signal.There is maximum timing allowance, to be further ensured that in this way on interface
The reliability of link.
In one of the embodiments, as shown in figure 3, phase correction module 20 includes voltage comparator 21 and phase delay
Unit 22；The reference end of voltage comparator 21 is for accessing exemplary voltages；The input terminal of voltage comparator 21 connects phase discriminator 11
Output end, the output end of voltage comparator 21 connect with phase delay unit 22, and voltage comparator 21 is for comparing the first phase
Potential difference voltage and exemplary voltages, and export comparison result signal；The output end of phase delay unit 22 is for connecting display device
Driving circuit 40, phase delay unit 22 be used for according to comparison result signal adjust clock signal and data-signal phase difference
For target phase difference.
Wherein, voltage comparator 21 is the circuit identified compared with to input signal, it can be determined that two or more
Size relation between input signal, and export output voltage corresponding with size relation.Phase delay unit 22 is to refer to
Carry out the circuit unit of signal phase delay.Specifically, voltage comparator 21 compares the first first phase potential difference and typical electrical
Relationship between pressure, and according to comparison result, corresponding comparison result signal is exported to phase delay unit 22, phase delay list
According to the comparison result signal got, whether the phase difference of the clock signal and data-signal that judge bus 30 meets is wanted member 22
It asks, if not satisfied, the phase difference of clock signal and data-signal is then adjusted according to comparison result signal, so that two adjusted
Phase difference between signal meets the requirement of 30 communication protocol of I2C bus.
In one of the embodiments, as shown in figure 3, phase correction module 20 further includes charge pump 23, charge pump 23
Input terminal is connect with the output end of phase discriminator 11, and the output end of charge pump 23 is connect with the input terminal of voltage comparator 21, charge
Pump 23 is for being converted to second phase potential difference for first phase potential difference, and voltage comparator 21 is for comparing second phase difference electricity
Pressure and exemplary voltages, and export comparison result signal.
Wherein, charge pump 23 (charge pump) is also referred to as switched capacitor voltage changer, is to be able to carry out direct current
The device that buckling is changed.First phase potential difference is converted to second phase potential difference by charge pump 23, and second phase potential difference can be with
Be with the consistent voltage of exemplary voltages measurement degree, then phase delay unit 22 according to second phase potential difference and exemplary voltages it
Between size relation and size of the difference, adjust the phase difference between clock signal and data-signal, phase difference reached
30 protocol requirement of bus.The phase that adjustment process can be by adjusting clock signal adjusts the phase difference of two signals.
The bus of display device is I2C bus in one of the embodiments,.Signal correction control device being capable of basis
The phase difference of clock signal SCL and data-signal SDA in I2C bus signals, to correspond to the phase of adjustment clock signal SCL,
So that the requirement of the time (setup time) when the phase difference between two signals can satisfy I2C bus transfer, to improve
Accuracy and display quality is written in data.Specifically, can using detecting phase module 10 obtain and detect in I2C bus when
First phase potential difference between clock signal SCL and data-signal SDA, then by obtained first phase difference voltage transmission to phase
Bit correction module 20, phase correction module 20 are measured according to the first phase potential difference and preset exemplary voltages got
Whether current phase difference meets the requirement of I2C bus transfer, if not meeting, according to first phase potential difference and preset allusion quotation
Type voltage, the phase difference between corresponding adjustment clock signal SCL and data-signal SDA make adjusting offset to target phase difference,
So that the data stabilization constant time can satisfy requirement before rising edge clock signal arrives, guarantee data at this
Clock rising edge is written into, and carries out display driving.
Signal correction control method provided in an embodiment of the present invention applied to above-mentioned signal correction controller, such as Fig. 4 institute
Show, comprising:
S10: clock signal and data-signal are obtained；
S20: according to the clock signal and data-signal of acquisition, the first phase difference electricity of clock signal and data-signal is obtained
Pressure；
S40: according to first phase potential difference and preset exemplary voltages, the phase difference of clock signal and data-signal is adjusted
For target phase difference, data-signal adjusted is enable to be correctly written in driving circuit.
Wherein, the paraphrase of the nouns such as clock signal and data-signal is identical as in above-mentioned signal correction controller, herein not
It repeats.Specifically, obtaining the first phase difference of clock signal and data-signal according to the clock signal and data-signal of acquisition
Voltage, then according to obtained first phase potential difference and preset exemplary voltages, judge the clock signal sum number of bus it is believed that
Whether the phase difference between number meets request signal transmission.Then the phase difference for adjusting clock signal and data-signal is target phase
Potential difference.
In one of the embodiments, as shown in figure 5, signal correction control method further comprises the steps of:
S60: clock signal and data-signal adjusted after output adjustment to driving circuit.
According to the size relation and difference between first phase potential difference and exemplary voltages, adjust clock signal sum number it is believed that
Phase difference between number, and the clock signal for meeting phase difference requirement and data-signal are exported to driving circuit, through overdriving
Each sub-pixel in circuit transmission to display device, drives each sub-pixel to show.
In one of the embodiments, as shown in fig. 6, according to first phase potential difference and preset exemplary voltages, adjustment
The phase difference of clock signal and data-signal be target phase difference the step of include:
S41: according to first phase potential difference and exemplary voltages, comparison result signal is obtained；
S42: according to comparison result signal, clock signal is adjusted, so that the phase of clock signal adjusted and data-signal
Potential difference is target phase difference.
According to the ratio of first phase potential difference and the exemplary voltages available size being able to reflect between the two and difference
Compared with consequential signal, then according to comparison result signal, it can be determined that clock signal is relative to the number under exemplary voltages corresponding states
It is believed that number phase be in advance or lag, according to judging result carry out phase adjustment so that clock signal adjusted and tune
The phase difference of data-signal after whole is target phase difference, guarantees the accuracy of data write-in.
For example, first phase potential difference is compared with exemplary voltages, if first phase potential difference is greater than exemplary voltages,
Illustrate that actual phase is greater than the phase of exemplary voltages, it is necessary to which the rising edge of clock signal SCL is shifted to an earlier date into corresponding phase difference.
Similarly, if first phase potential difference is less than exemplary voltages, illustrate that actual phase is less than the phase of exemplary voltages, it is necessary to will
The corresponding phase difference of the rise edge delay of clock signal SCL.If first phase potential difference is equal to exemplary voltages, illustrate reality
Phase be equal to exemplary voltages phase, there is no need to make any change for that.
In one of the embodiments, as shown in fig. 7, being obtained according to the first phase potential difference and the exemplary voltages
Comparison result signal the step of include:
S411: according to the first phase potential difference, second phase potential difference is obtained；
S412: according to the second phase potential difference and the exemplary voltages, comparison result signal is obtained.
If the first phase potential difference of phase discriminator equiphase detecting module output differs larger with the weights and measures of exemplary voltages,
Then the voltage value with exemplary voltages for a weights and measures, i.e. second phase can be converted into according to first phase potential difference
Potential difference obtains comparison result signal according to size, the difference between second phase potential difference and exemplary voltages, and according to than
The phase difference between two signals is adjusted compared with consequential signal, reaches target phase difference.
For example, second phase potential difference is compared with exemplary voltages, if second phase potential difference is greater than exemplary voltages,
Illustrate that actual phase is greater than the phase of exemplary voltages, it is necessary to which the rising edge of clock signal SCL is shifted to an earlier date into corresponding phase difference.
Similarly, if second phase potential difference is less than exemplary voltages, illustrate that actual phase is less than the phase of exemplary voltages, it is necessary to will
The corresponding phase difference of the rise edge delay of clock signal SCL.If second phase potential difference is equal to exemplary voltages, illustrate reality
Phase be equal to exemplary voltages phase, there is no need to make any change for that.
In one of the embodiments, as shown in figure 8, according to comparison result signal, adjust clock signal the step of include:
S421: if comparison result signal is greater than exemplary voltages, according to the difference pair of comparison result signal and exemplary voltages
The phase of clock signal should be reduced；
S422: if comparison result signal is less than exemplary voltages, according to the difference pair of exemplary voltages and comparison result signal
The phase of clock signal should be increased.
As shown in figures 3 and 8, clock signal SCL and data-signal SDA enters phase discriminator, and phase discriminator detects clock signal
The phase difference of SCL and data-signal SDA, and first phase potential difference is exported, subsequent charge pump converts first phase potential difference
For second phase potential difference, then second phase potential difference is compared to obtain comparison result signal with exemplary voltages, according to
Comparison result signal is changed the phase of clock signal SCL, guarantees the phase difference of clock signal SCL and data-signal SDA
It is maintained at target phase difference.
It should be understood that although each step in the flow chart of Fig. 4-8 is successively shown according to the instruction of arrow,
These steps are not that the inevitable sequence according to arrow instruction successively executes.Unless expressly stating otherwise herein, these steps
Execution there is no stringent sequences to limit, these steps can execute in other order.Moreover, at least one in Fig. 4-8
Part steps may include that perhaps these sub-steps of multiple stages or stage are not necessarily in synchronization to multiple sub-steps
Completion is executed, but can be executed at different times, the execution sequence in these sub-steps or stage is also not necessarily successively
It carries out, but can be at least part of the sub-step or stage of other steps or other steps in turn or alternately
It executes.
A kind of display device, as shown in figure 9, including display panel 1, bus 30, driving circuit 40 and above-mentioned signal correction
Controller 2, bus 30 are connect with the input terminal of signal correction controller 2, the output end and driving circuit of signal correction controller 2
The connection of 40 input terminals, the first output end of driving circuit 40 are connect with the scan line on display panel 1, and the second of driving circuit 40
Output end is connect with the data line on display panel 1.
Wherein, the paraphrase of the nouns such as clock signal is identical as the noun paraphrase in above-mentioned signal correction controller, does not do herein
It repeats.One end of bus 30 can connect external equipment or connection mainboard controller etc., other end connection signal Corrective control
Device 2.Specifically, signal correction controller 2 obtains the clock signal transmitted in bus 30 and data-signal, two letters are then judged
Whether the phase difference between number is target phase difference, that is, meets 30 transmission requirement of bus, can guarantee being correctly written in for data, if
It does not meet, then adjusts the phase difference between two signals, and clock signal after output adjustment and data-signal adjusted are given
Driving circuit 40, driving circuit 40 exports clock signal to each scan line respectively, and outputting data signals give pieces of data line,
Display panel 1 is driven correctly to show.Clock signal adjusted and the phase relation of data-signal adjusted are expired
The requirement that Football Association's line 30 transmits, avoid because phase difference it is undesirable caused by write error in data, to guarantee that display device is aobvious
The stability and accuracy shown improve display image quality.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Protect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (11)
1. a kind of signal correction controller characterized by comprising detecting phase module and phase correction module；
The input terminal of the detecting phase module is used to connect the bus of display device, and the output end of the detecting phase module connects
The input terminal of the phase correction module is connect, the output end of the phase correction module is used to connect the driving electricity of display device
Road；
The detecting phase module is used to obtain the clock signal and data-signal in the bus and exports the clock signal
With the first phase potential difference of the data-signal；
The phase correction module is used to adjust the clock letter according to the first phase potential difference and preset exemplary voltages
Number and the data-signal phase difference be target phase difference.
2. signal correction controller according to claim 1, which is characterized in that the detecting phase module includes phase demodulation
Device, the input terminal of the phase discriminator are used to connect the bus of the display device, and the output end of the phase discriminator connects the phase
The input terminal of bit correction module.
3. signal correction controller according to claim 2, which is characterized in that the phase correction module includes voltage ratio
Compared with device and phase delay unit；The reference end of the voltage comparator is for accessing exemplary voltages；
The input terminal of voltage comparator connects the output end of the phase discriminator, the output end of the voltage comparator and the phase
Delay unit connection, the voltage comparator export ratio for the first phase potential difference and the exemplary voltages
Compared with consequential signal；
The output end of the phase delay unit is used to connect the driving circuit of display device, and the phase delay unit is used for root
The phase difference that the clock signal and the data-signal are adjusted according to the comparison result signal is target phase difference.
4. signal correction controller according to claim 3, which is characterized in that the phase correction module further includes charge
Pump, the input terminal of the charge pump are connect with the output end of the phase discriminator, the output end of the charge pump and the voltage ratio
Input terminal compared with device connects, and the charge pump is used to the first phase potential difference being converted to second phase potential difference, described
Voltage comparator exports comparison result signal for the second phase potential difference and the exemplary voltages.
5. signal correction controller described in any one of -4 according to claim 1, which is characterized in that the display device it is total
Line is I2C bus.
6. a kind of signal correction control method characterized by comprising
Obtain the clock signal and data-signal of bus；
According to the clock signal of acquisition and the data-signal, the first of the clock signal and the data-signal is obtained
Phase voltage；
According to the first phase potential difference and preset exemplary voltages, the phase of the clock signal and the data-signal is adjusted
Potential difference is target phase difference, and data-signal adjusted is enable to be correctly written in driving circuit.
7. signal correction control method according to claim 6, which is characterized in that further comprise the steps of:
Clock signal and data-signal adjusted after output adjustment are to the driving circuit.
8. signal correction control method according to claim 7, which is characterized in that according to the first phase potential difference and
The step of preset exemplary voltages, the phase difference for adjusting the clock signal and data-signal adjusted is target phase difference packet
It includes:
According to the first phase potential difference and the exemplary voltages, comparison result signal is obtained；
According to the comparison result signal, the clock signal is adjusted, so that clock signal adjusted and data adjusted
The phase difference of signal is target phase difference.
9. signal correction control method according to claim 8, which is characterized in that according to the first phase potential difference and
The exemplary voltages, obtain comparison result signal the step of include:
According to the first phase potential difference, second phase potential difference is obtained；
According to the second phase potential difference and the exemplary voltages, comparison result signal is obtained.
10. signal correction control method according to claim 8 or claim 9, which is characterized in that believed according to the comparison result
Number, the step of adjusting the clock signal includes:
If the comparison result signal is greater than the exemplary voltages, according to the comparison result signal and the exemplary voltages
The corresponding phase for reducing clock signal of difference；
If the comparison result signal is less than the exemplary voltages, according to the exemplary voltages and the comparison result signal
The corresponding phase for increasing clock signal of difference.
11. a kind of display device, which is characterized in that including display panel, bus is any in driving circuit and claim 1-5
Signal correction controller described in, the bus are connect with the input terminal of the signal correction controller, the signal correction
The output end of controller is connect with the driving circuit input terminal, the first output end and the display panel of the driving circuit
On scan line connection, the second output terminal of the driving circuit connect with the data line on the display panel.
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| CN201811556308.9A CN109493782A (en) | 2018-12-19 | 2018-12-19 | Signal correction controller, signal correction control method and display device |
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Application publication date: 20190319 |