CN204375392U - A kind of driving circuit and display device - Google Patents
A kind of driving circuit and display device Download PDFInfo
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- CN204375392U CN204375392U CN201520053616.5U CN201520053616U CN204375392U CN 204375392 U CN204375392 U CN 204375392U CN 201520053616 U CN201520053616 U CN 201520053616U CN 204375392 U CN204375392 U CN 204375392U
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Abstract
The utility model provides a kind of driving circuit and display device, described driving circuit comprises time schedule controller, timing adjuster and driver, described time schedule controller exports the first data-signal and the first clock signal, described timing adjuster regulates the phase place of described first data-signal and described first clock signal, to produce the second mutually corresponding data-signal and second clock signal, described driver produces drive singal according to described second data-signal and described second clock signal.Described timing adjuster active regulates the first data-signal of time schedule controller output and the first clock signal, to produce the second mutually corresponding data-signal and second clock signal, thus realize, with the perfect matching of display panel, improve the display quality of display panel.
Description
Technical field
The utility model relates to display technique field, particularly relates to a kind of driving circuit and display device.
Background technology
Existing display uses time schedule controller to produce data-signal and clock signal, and the driver of described display carrys out actuating logic computing according to described data-signal and clock signal again, thus produces the drive singal of described display panel.Therefore, the phase differential between described data-signal and clock signal is predetermined value, that is, is mutually corresponding between described data-signal and clock signal.But, size due to display panel increases and the factor such as circuit layout, the data-signal that described driver receives and clock signal there will be signal delay in various degree, mutually can not mate between the data-signal of the data-signal causing described time schedule controller to export and clock signal and described display panel needs and clock signal, thus affect the display quality of display.
Utility model content
For solving the problem, the utility model provides a kind of driving circuit and display device, for can not mutually mating between data-signal and clock signal of solving that data-signal that time schedule controller in prior art exports and clock signal and display panel need, thus affect the problem of the display quality of display.
For this reason, the utility model provides a kind of driving circuit, comprises time schedule controller, timing adjuster and driver, and described timing adjuster is connected with the input end of described time schedule controller, and the output terminal of described timing adjuster is connected with described driver; Described time schedule controller is for exporting the first data-signal and the first clock signal; Described timing adjuster for regulating the phase place of described first data-signal and described first clock signal, to produce the second mutually corresponding data-signal and second clock signal; Described driver is used for producing drive singal according to described second data-signal and described second clock signal.
Optionally, described timing adjuster comprises converting unit and lock unit, the input end of described converting unit is connected with described time schedule controller, first output terminal of described converting unit is connected with the first input end of described lock unit, second output terminal of described converting unit is connected with described driver, second input end of described lock unit is connected with described time schedule controller, and the output terminal of described lock unit is connected with described driver; Described converting unit is for regulating the phase place of described first clock signal to produce described second clock signal; Described lock unit is used for producing the second data-signal according to described second clock signal and described first data-signal, and described second data-signal and described second clock signal have predetermined phase differential.
Optionally, described converting unit comprises multiple phase inverter.
Optionally, described lock unit comprises d type flip flop.
Optionally, described driver comprises source electrode driver.
Optionally, described phase inverter comprises at least one in nmos type phase inverter, pmos type phase inverter and CMOS type phase inverter, described nmos type phase inverter comprises nmos pass transistor and resistance, described pmos type phase inverter comprises PMOS transistor and resistance, and described CMOS type phase inverter comprises nmos pass transistor and PMOS transistor.
The utility model also provides a kind of display device, comprises display panel and above-mentioned arbitrary driving circuit.
The utility model has following beneficial effect:
In the driving circuit that the utility model provides and display device, described driving circuit comprises time schedule controller, timing adjuster and driver, described time schedule controller exports the first data-signal and the first clock signal, described timing adjuster regulates the phase place of described first data-signal and described first clock signal, to produce the second mutually corresponding data-signal and second clock signal, described driver produces drive singal according to described second data-signal and described second clock signal.Described timing adjuster active regulates the first data-signal of time schedule controller output and the first clock signal, to produce the second mutually corresponding data-signal and second clock signal, thus realize, with the perfect matching of display panel, improve the display quality of display panel.
Accompanying drawing explanation
The structural representation of a kind of driving circuit that Fig. 1 provides for the utility model embodiment one;
Fig. 2 is the structural representation of timing adjuster shown in Fig. 1.
Embodiment
For making those skilled in the art understand the technical solution of the utility model better, the driving circuit provided the utility model below in conjunction with accompanying drawing and display device are described in detail.
Embodiment one
The structural representation of a kind of driving circuit that Fig. 1 provides for the utility model embodiment one.As shown in Figure 1, driving circuit comprises time schedule controller 101, timing adjuster 102 and driver 103, and timing adjuster 102 is connected with the input end of time schedule controller 101, and the output terminal of timing adjuster 102 is connected with driver 103.Time schedule controller 101 is for exporting the first data-signal and the first clock signal, timing adjuster 102 is for regulating the phase place of the first data-signal and the first clock signal, to produce the second mutually corresponding data-signal and second clock signal, driver 103 is for producing drive singal according to the second data-signal and second clock signal.
In the present embodiment, time schedule controller 101 produces the first data-signal and the first clock signal, and by the first data-signal and the first clock signal transmission to timing adjuster 102.In the ideal situation, phase differential between first data-signal and the first clock signal is predetermined value, in actual applications, the factors such as circuit layout cause the first data-signal and the first clock signal to there will be signal delay in various degree, make the phase differential between the first data-signal and the first clock signal depart from predetermined value.After timing adjuster 102 receives the first data-signal and the first clock signal, regulate the phase place of the first data-signal and the first clock signal, to produce the second data-signal after phase only pupil filter and second clock signal, the second data-signal and second clock signal mutually corresponding.Driver 103 receives the second data-signal and second clock signal, then produces the drive singal of display panel needs according to the second data-signal and second clock signal, thus realizes the perfect matching with display panel, improves the display quality of display panel.
Fig. 2 is the structural representation of timing adjuster 102 shown in Fig. 1.As shown in Figure 2, timing adjuster 102 is connected with the input end of time schedule controller 101, and the output terminal of timing adjuster 102 is connected with driver 103.Timing adjuster 102 comprises converting unit 104 and lock unit 105, the input end of converting unit 104 is connected with time schedule controller 101, first output terminal of converting unit 104 is connected with the first input end of lock unit 105, second output terminal of converting unit 104 is connected with driver 103, second input end of lock unit 105 is connected with time schedule controller 101, and the output terminal of lock unit 105 is connected with driver 103.
Converting unit 104 receives the first clock signal that time schedule controller 101 produces, and then regulates the phase place of the first clock signal to produce second clock signal, and by second clock Signal transmissions to lock unit 105 and driver 103.Lock unit 105 receives the first data-signal of time schedule controller 101 generation and the second clock signal of converting unit 104 generation, then second data-signal corresponding with second clock signal is produced according to predetermined phase differential, thus realize, with the perfect matching of display panel, improve the display quality of display panel.
In the present embodiment, converting unit 104 comprises multiple phase inverter.Phase inverter provides signal delay in various degree for the first clock signal, to regulate the phase place of the first clock signal, thus produces second clock signal.Phase inverter has that operating rate is fast, carrying load ability is strong and the advantage such as transport property is good.
In actual applications, Fundamental Digital Circuit carries out computing in the fixed voltage level range that logical zero and 1 (scale-of-two) is corresponding.Phase inverter is basic logic gate, can convert between two voltage levels.Logic level representated by the output voltage of phase inverter is contrary with the logic level representated by input voltage.Such as, high level is become low level, or low level is become high level.The voltage of the phase inverter of practical application is all different, and such as, in logic gates (Transistor-Transistor Logic, TTL), 0 is low level, and+5V is high level.Optionally, phase inverter is nmos type phase inverter.Nmos type phase inverter is made up of a nmos pass transistor and a resistance.Optionally, phase inverter is pmos type phase inverter.Pmos type phase inverter is made up of a PMOS transistor and a resistance.Because nmos type phase inverter and pmos type phase inverter only need the transistor of use one type, the therefore low cost of manufacture of nmos type phase inverter and pmos type phase inverter.Preferably, phase inverter is CMOS type phase inverter.CMOS type phase inverter is made up of nmos pass transistor and PMOS transistor.Due in two kinds of logic states, in nmos pass transistor and PMOS transistor one always ends, and therefore CMOS type phase inverter can reduce power consumption.Compared with nmos type phase inverter or pmos type phase inverter, the resistance of CMOS type phase inverter is relatively low, and therefore CMOS type phase inverter can improve processing speed.
Optionally, lock unit 105 comprises d type flip flop.D type flip flop comprises first input end, the second input end and output terminal, and first input end is for inputting second clock signal, and the second input end is for inputting the first data-signal, and output terminal is used for driver output second data-signal.Optionally, driver 103 comprises source electrode driver 103.Source electrode driver 103 receives the second clock signal of converting unit 104 generation and the second data-signal of lock unit 105 generation, then produces drive singal according to second clock signal and the second data-signal.Because the second data-signal is mutually corresponding with second clock signal, therefore, it is possible to realize, with the perfect matching of display panel, improve the display quality of display panel.
In the driving circuit that the present embodiment provides, driving circuit comprises time schedule controller 101, timing adjuster 102 and driver 103, time schedule controller 101 exports the first data-signal and the first clock signal, timing adjuster 102 regulates the phase place of the first data-signal and the first clock signal, to produce the second mutually corresponding data-signal and second clock signal, driver 103 produces drive singal according to the second data-signal and second clock signal.Timing adjuster 102 active regulates the first data-signal of time schedule controller 101 output and the first clock signal, to produce the second mutually corresponding data-signal and second clock signal, thus realize, with the perfect matching of display panel, improve the display quality of display panel.
Embodiment two
The present embodiment two provides a kind of display device, and comprise the driving circuit that display panel and embodiment one provide, particular content can refer to the description in above-described embodiment one, repeats no more herein.
In the display device that the present embodiment provides, driving circuit comprises time schedule controller 101, timing adjuster 102 and driver 103, time schedule controller 101 exports the first data-signal and the first clock signal, timing adjuster 102 regulates the phase place of the first data-signal and the first clock signal, to produce the second mutually corresponding data-signal and second clock signal, driver 103 produces drive singal according to the second data-signal and second clock signal.Timing adjuster 102 active regulates the first data-signal of time schedule controller 101 output and the first clock signal, to produce the second mutually corresponding data-signal and second clock signal, thus realize, with the perfect matching of display panel, improve the display quality of display panel.
Be understandable that, the illustrative embodiments that above embodiment is only used to principle of the present utility model is described and adopts, but the utility model is not limited thereto.For those skilled in the art, when not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection domain of the present utility model.
Claims (7)
1. a driving circuit, is characterized in that, comprises time schedule controller, timing adjuster and driver, and described timing adjuster is connected with the input end of described time schedule controller, and the output terminal of described timing adjuster is connected with described driver;
Described time schedule controller is for exporting the first data-signal and the first clock signal;
Described timing adjuster for regulating the phase place of described first data-signal and described first clock signal, to produce the second mutually corresponding data-signal and second clock signal;
Described driver is used for producing drive singal according to described second data-signal and described second clock signal.
2. driving circuit according to claim 1, it is characterized in that, described timing adjuster comprises converting unit and lock unit, the input end of described converting unit is connected with described time schedule controller, first output terminal of described converting unit is connected with the first input end of described lock unit, second output terminal of described converting unit is connected with described driver, and the second input end of described lock unit is connected with described time schedule controller, and the output terminal of described lock unit is connected with described driver;
Described converting unit is for regulating the phase place of described first clock signal to produce described second clock signal;
Described lock unit is used for producing the second data-signal according to described second clock signal and described first data-signal, and described second data-signal and described second clock signal have predetermined phase differential.
3. driving circuit according to claim 2, is characterized in that, described converting unit comprises multiple phase inverter.
4. driving circuit according to claim 2, is characterized in that, described lock unit comprises d type flip flop.
5. driving circuit according to claim 1, is characterized in that, described driver comprises source electrode driver.
6. driving circuit according to claim 3, it is characterized in that, described phase inverter comprises at least one in nmos type phase inverter, pmos type phase inverter and CMOS type phase inverter, described nmos type phase inverter comprises nmos pass transistor and resistance, described pmos type phase inverter comprises PMOS transistor and resistance, and described CMOS type phase inverter comprises nmos pass transistor and PMOS transistor.
7. a display device, is characterized in that, comprises display panel and the arbitrary described driving circuit of claim 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520053616.5U CN204375392U (en) | 2015-01-26 | 2015-01-26 | A kind of driving circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520053616.5U CN204375392U (en) | 2015-01-26 | 2015-01-26 | A kind of driving circuit and display device |
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| CN204375392U true CN204375392U (en) | 2015-06-03 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016119467A1 (en) * | 2015-01-26 | 2016-08-04 | 京东方科技集团股份有限公司 | Drive circuit and drive method therefor, and display device |
| CN109493782A (en) * | 2018-12-19 | 2019-03-19 | 惠科股份有限公司 | Signal correction controller, signal correction control method and display device |
| CN110858474A (en) * | 2018-08-23 | 2020-03-03 | 堺显示器制品株式会社 | Display device and data transmission method in display device |
-
2015
- 2015-01-26 CN CN201520053616.5U patent/CN204375392U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016119467A1 (en) * | 2015-01-26 | 2016-08-04 | 京东方科技集团股份有限公司 | Drive circuit and drive method therefor, and display device |
| CN110858474A (en) * | 2018-08-23 | 2020-03-03 | 堺显示器制品株式会社 | Display device and data transmission method in display device |
| CN109493782A (en) * | 2018-12-19 | 2019-03-19 | 惠科股份有限公司 | Signal correction controller, signal correction control method and display device |
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Granted publication date: 20150603 |
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| CF01 | Termination of patent right due to non-payment of annual fee |