US7916132B2 - Systems for displaying images and related methods - Google Patents

Systems for displaying images and related methods Download PDF

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US7916132B2
US7916132B2 US11/842,285 US84228507A US7916132B2 US 7916132 B2 US7916132 B2 US 7916132B2 US 84228507 A US84228507 A US 84228507A US 7916132 B2 US7916132 B2 US 7916132B2
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switch
signal
node
terminal
coupled
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US20080068365A1 (en
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Szu-Hsien Lee
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Innolux Corp
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Chimei Innolux Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • the invention relates to AC signal generating circuits.
  • FIG. 1 shows a conventional AC signal generating circuit 10 , comprising capacitor C, resistor R 1 and output terminal 11 .
  • Capacitor C is coupled between output terminal 11 and AC voltage signal VCOM.
  • Resistor R 1 is coupled between output terminal 11 and DC signal Vdc.
  • the voltage of output terminal 11 comprises a DC voltage component from DC signal Vdc and an AC voltage component from the AC voltage signal VCOM.
  • FIG. 2 is a timing diagram of AC voltage signal VCOM, DC signal Vdc and AC voltage signal VCOMP of output terminal 11 of AC signal generating circuit 10 in FIG. 1 .
  • AC voltage signal VCOM is output through capacitor C to output terminal 11 and DC voltage signal Vdc is output through resistor R 1 to output terminal 11 .
  • the voltage of output terminal 11 is changed by adjusting DC voltage signal Vdc and AC voltage signal VCOM.
  • Voltage amplitude A is voltage amplitude of AC voltage signal VCOM or voltage amplitude of AC voltage signal VCOMP.
  • an embodiment of a system comprises an AC signal generating circuit.
  • the AC signal generating circuit comprises a first capacitor coupled between a first node and an AC signal, a second capacitor coupled between a second node and the AC signal, a first switch coupled between the first node and a first DC signal, a second switch coupled between the second node and a second DC signal, a third switch coupled between the first node and an output terminal and a fourth switch coupled between the second node and the output terminal.
  • the first switch and the fourth switch are synchronous, the second switch and the third switch are synchronous and the first switch and the second switch are asynchronous.
  • An embodiment of a method for driving an AC signal generating circuit comprising a first capacitor coupled between a first node and an AC signal, a second capacitor coupled between a second node and the AC signal, a first switch coupled between the first node and a first DC signal, a second switch coupled between the second node and a second DC signal, a third switch coupled between the first node and an output terminal, and a fourth switch coupled between the second node and the output terminal, the method comprising: providing the AC signal to the first capacitor and the second capacitor; providing the first DC signal through the first switch to the first node; and providing the second DC signal through the second switch to the second node; wherein the first switch and the fourth switch are synchronous, the second switch and the third switch are synchronous and the first switch and the second switch are asynchronous.
  • FIG. 1 shows a conventional AC signal generating circuit
  • FIG. 2 is a timing diagram of AC voltage signal VCOM, DC signal Vdc and AC voltage signal VCOMP;
  • FIG. 3 is a schematic diagram of a first state of the AC signal generating circuit according to an embodiment of the invention.
  • FIG. 4 is a schematic diagram of a second state of the AC signal generating circuit according to an embodiment of the invention.
  • FIG. 5 is a timing diagram of AC voltage signal VCOM, first DC signal Vdc 1 , second DC signal Vdc 2 and AC voltage signal VCOMP according to an embodiment of the invention
  • FIG. 6 shows an AC signal generating circuit according to another embodiment of the invention.
  • FIG. 7 shows a large scale AC signal generating architecture according to another embodiment of the invention.
  • FIG. 8 schematically shows another embodiment of a system for displaying images.
  • FIG. 3 is a schematic diagram of a first state of AC signal generating circuit 30 according to an embodiment of the invention.
  • AC signal generating circuit 30 provides a wide range AC voltage to a display panel.
  • AC signal generating circuit 30 comprises first capacitor C 1 , second capacitor C 2 , first switch SW 1 , second switch SW 2 , third switch SW 3 and fourth switch SW 4 .
  • First capacitor C 1 is coupled between first node 1 and AC signal VCOM.
  • Second capacitor is coupled between second node 2 and AC signal VCOM.
  • First switch SW 1 is coupled between first node 1 and first DC signal Vdc 1 .
  • Second switch SW 2 is coupled between second node 2 and second DC signal Vdc 2 .
  • Third switch SW 3 is coupled between first node 1 and output node 12 .
  • Fourth switch SW 4 is coupled between second node 2 and output node 12 .
  • Each of first switch SW 1 , second switch SW 2 , third switch SW 3 and fourth switch SW 4 may comprise a switch transistor.
  • the switch transistor may comprise a P-type transistor and an N-type transistor.
  • first capacitor C 1 and second capacitor C 2 are between 1 ⁇ F and 4 ⁇ F
  • first DC voltage Vdc 1 and second DC voltage Vdc 2 are between 1 and 5 v.
  • first switch SW 1 and fourth switch SW 4 are turned off simultaneously and second switch SW 2 and third switch SW 3 are turned on simultaneously.
  • second DC signal Vdc 2 is transmitted through second switch SW 2 to second node 2 .
  • the voltage of second node 2 equals the voltage of second DC signal Vdc 2 .
  • the voltage of first node 1 is transmitted through third switch SW 3 to output node 12 , such that voltage of output node 12 equals the voltage of first node 1 .
  • FIG. 4 is a schematic diagram of the second state of AC signal generating circuit 30 according to an embodiment of the invention. Components of AC signal generating circuit 30 in FIG. 4 are the same as in FIG. 3 , differing only in the states of first switch SW 1 , second switch SW 2 , third switch SW 3 and fourth switch SW 4 .
  • Each of first switch SW 1 , second switch SW 2 , third switch SW 3 and fourth switch SW 4 may comprise a switch transistor.
  • the switch transistor may comprise a P-type transistor and a N-type transistor.
  • first switch SW 1 and fourth switch SW 4 are turned on simultaneously and second switch SW 2 and third switch SW 3 are turned off simultaneously.
  • first DC signal Vdc 1 is transmitted through first switch SW 1 to first node 1 .
  • the voltage of first node 1 equals the voltage of first DC signal Vdc 1 .
  • the voltage of second node 2 is transmitted through fourth switch SW 4 to output node 12 , so the voltage of output node 12 equals the voltage of second node 2 .
  • FIG. 5 is a timing diagram of AC voltage signal VCOM, first DC signal Vdc 1 , second DC signal Vdc 2 and AC voltage signal VCOMP of output node 12 according to an embodiment of the invention.
  • first switch SW 1 and fourth switch SW 4 are turned off simultaneously, and second switch SW 2 and third switch SW 3 are turned on simultaneously.
  • the voltage of second node 2 equals the voltage of second DC signal Vdc 2 .
  • the voltage of output node 12 equals the voltage of first node 1 .
  • the voltage of first node 1 equals the voltage of first DC signal Vdc 1 .
  • the cross voltage of first capacitor C 1 cannot change immediately.
  • first switch SW 1 and fourth switch SW 4 are turned on simultaneously, and second switch SW 2 and third switch SW 3 are turned off simultaneously.
  • the voltage of first node 1 equals the voltage of first DC signal Vdc 1 .
  • the voltage of output node 12 equals the voltage of second node 2 .
  • the voltage of second node 2 equals the voltage of second DC signal Vdc 2 .
  • the cross voltage of second capacitor C 2 cannot be changed immediately.
  • Voltage amplitude A 1 exceeds voltage amplitude A 2 .
  • AC signal generating circuit 30 provides the voltage amplitude of AC voltage signal VCOMP which exceeds the voltage amplitude of AC voltage signal VCOM.
  • FIG. 6 shows AC signal generating circuit 60 according to another embodiment of the invention.
  • AC signal generating circuit 60 comprises first capacitor C 1 , second capacitor C 2 , first switch SW 1 , second switch SW 2 , third switch SW 3 , fourth switch SW 4 and control signal generator 62 .
  • control signal generator 62 controls first switch SW 1 , second switch SW 2 , third switch SW 3 and fourth switch SW 4 which are implemented by transmission gates.
  • each transmission gate comprises a P-type transistor and an N-type transistor.
  • Each transmission gate comprises a first terminal, a second terminal, a third terminal and a fourth terminal.
  • the P-type transistor is coupled to the first terminal, the second terminal and the fourth terminal.
  • the N-type transistor is coupled to the first terminal, the third terminal and the fourth terminal.
  • Control signal generator 62 is coupled to the second terminal and the third terminal. Since the operation of AC signal generating circuit 60 in FIG. 6 is similar to the operation of AC signal generating circuit 30 in FIGS. 3 and 4 , it is not detailed here.
  • FIG. 7 shows large scale AC signal generating architecture 70 according to another embodiment of the invention.
  • Large scale AC signal generating architecture 70 comprises control signal generator 71 and large scale AC signal generating circuit 72 .
  • Control signal generator 71 is disposed on the driving IC.
  • Large scale AC signal generating circuit 72 is disposed on the glass panel.
  • Control signal generator 71 is electrically coupled to large scale AC signal generating circuit 72 .
  • Control signal generator 71 transmits first DC voltage signal Vdc 1 , second DC voltage signal Vdc 2 and AC voltage signal VCOM to large scale AC signal generating circuit 72 .
  • Large scale AC signal generating circuit 72 generates AC voltage signal VCOMP according to first DC voltage signal Vdc 1 , second DC voltage signal Vdc 2 and AC voltage signal VCOM. Due to large scale AC signal generating circuit 72 , the driving IC can utilize a process with lower voltage grade, thereby potentially reducing costs.
  • FIG. 8 schematically shows another embodiment of a system for displaying images which, in this case, is implemented as electronic device 600 , which incorporates a display panel 400 .
  • display panel 400 comprises an AC signal generating circuit, such as circuit 30 of FIG. 3 , and a power supply 500 .
  • Power supply 500 is operatively coupled to display panel 400 and provides power to display panel 400 .
  • Electronic device 600 can be a mobile phone, digital camera, PDA (personal data assistant), notebook computer, desktop computer, television, or portable DVD player, for example.
  • PDA personal data assistant

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

A representative AC signal generating circuit includes a first capacitor, a second capacitor, a first switch, a second switch, a third switch and a fourth switch. The first capacitor is coupled between a first node and an AC signal. The second capacitor is coupled between a second node and the AC signal. The first switch is coupled between the first node and a first DC signal. The second switch is coupled between the second node and a second DC signal. The third switch is coupled between the first node and an output terminal. The fourth switch is coupled between the second node and the output terminal. The first switch and the fourth switch are synchronous, the second switch and the third switch are synchronous and the first switch and the second switch are asynchronous.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to AC signal generating circuits.
2. Description of the Related Art
While conventional black liquid crystal displays provide high contrast and wide viewing angle, driving circuits thereof normally integrated in a driving IC require high driving voltages. However, the driving voltage provided by the driving IC is limited by a processing voltage grade, with costs increased accordingly. Thus, it becomes more and more important to provide higher driving voltages associated with the limited processing voltage grades.
In this regard, FIG. 1 shows a conventional AC signal generating circuit 10, comprising capacitor C, resistor R1 and output terminal 11. Capacitor C is coupled between output terminal 11 and AC voltage signal VCOM. Resistor R1 is coupled between output terminal 11 and DC signal Vdc. Using a capacitive coupling method, the voltage of output terminal 11 comprises a DC voltage component from DC signal Vdc and an AC voltage component from the AC voltage signal VCOM.
FIG. 2 is a timing diagram of AC voltage signal VCOM, DC signal Vdc and AC voltage signal VCOMP of output terminal 11 of AC signal generating circuit 10 in FIG. 1. AC voltage signal VCOM is output through capacitor C to output terminal 11 and DC voltage signal Vdc is output through resistor R1 to output terminal 11. The voltage of output terminal 11 is changed by adjusting DC voltage signal Vdc and AC voltage signal VCOM. Voltage amplitude A is voltage amplitude of AC voltage signal VCOM or voltage amplitude of AC voltage signal VCOMP.
BRIEF SUMMARY OF THE INVENTION
Systems for displaying images and related methods are provided. In this regard, an embodiment of a system comprises an AC signal generating circuit. The AC signal generating circuit comprises a first capacitor coupled between a first node and an AC signal, a second capacitor coupled between a second node and the AC signal, a first switch coupled between the first node and a first DC signal, a second switch coupled between the second node and a second DC signal, a third switch coupled between the first node and an output terminal and a fourth switch coupled between the second node and the output terminal. The first switch and the fourth switch are synchronous, the second switch and the third switch are synchronous and the first switch and the second switch are asynchronous.
Another embodiment of a system for generating an AC signal comprises: an AC signal generating circuit comprising a first capacitor coupled between a first node and an AC signal, a second capacitor coupled between a second node and the AC signal, a first switch coupled between the first node and a first DC signal, a second switch coupled between the second node and a second DC signal, a third switch coupled between the first node and an output terminal, and a fourth switch coupled between the second node and the output terminal; wherein: during a first period, the AC signal generating circuit is operative to turn on the second switch and the third switch and turn off the first switch and the fourth switch such that voltage of the first node is transmitted through the third switch to the output terminal, and a second DC signal is transmitted through the second switch to the second node; and during a second period, the AC signal generating circuit is operative to turn off the second switch and the third switch and turn on the first switch and the fourth switch such that voltage of the second node is transmitted through the fourth switch to the output terminal, and a first DC signal is transmitted through the first switch to the first node.
An embodiment of a method for driving an AC signal generating circuit, the AC signal generating circuit comprising a first capacitor coupled between a first node and an AC signal, a second capacitor coupled between a second node and the AC signal, a first switch coupled between the first node and a first DC signal, a second switch coupled between the second node and a second DC signal, a third switch coupled between the first node and an output terminal, and a fourth switch coupled between the second node and the output terminal, the method comprising: providing the AC signal to the first capacitor and the second capacitor; providing the first DC signal through the first switch to the first node; and providing the second DC signal through the second switch to the second node; wherein the first switch and the fourth switch are synchronous, the second switch and the third switch are synchronous and the first switch and the second switch are asynchronous.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 shows a conventional AC signal generating circuit;
FIG. 2 is a timing diagram of AC voltage signal VCOM, DC signal Vdc and AC voltage signal VCOMP;
FIG. 3 is a schematic diagram of a first state of the AC signal generating circuit according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a second state of the AC signal generating circuit according to an embodiment of the invention;
FIG. 5 is a timing diagram of AC voltage signal VCOM, first DC signal Vdc1, second DC signal Vdc2 and AC voltage signal VCOMP according to an embodiment of the invention;
FIG. 6 shows an AC signal generating circuit according to another embodiment of the invention;
FIG. 7 shows a large scale AC signal generating architecture according to another embodiment of the invention; and
FIG. 8 schematically shows another embodiment of a system for displaying images.
 DETAILED DESCRIPTION OF THE INVENTION
The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 3 is a schematic diagram of a first state of AC signal generating circuit 30 according to an embodiment of the invention. AC signal generating circuit 30 provides a wide range AC voltage to a display panel. AC signal generating circuit 30 comprises first capacitor C1, second capacitor C2, first switch SW1, second switch SW2, third switch SW3 and fourth switch SW4. First capacitor C1 is coupled between first node 1 and AC signal VCOM. Second capacitor is coupled between second node 2 and AC signal VCOM. First switch SW1 is coupled between first node 1 and first DC signal Vdc1. Second switch SW2 is coupled between second node 2 and second DC signal Vdc2. Third switch SW3 is coupled between first node 1 and output node 12. Fourth switch SW4 is coupled between second node 2 and output node 12. Each of first switch SW1, second switch SW2, third switch SW3 and fourth switch SW4 may comprise a switch transistor. The switch transistor may comprise a P-type transistor and an N-type transistor. In addition, first capacitor C1 and second capacitor C2 are between 1 μF and 4 μF, and first DC voltage Vdc1 and second DC voltage Vdc2 are between 1 and 5 v.
As shown in FIG. 3, first switch SW1 and fourth switch SW4 are turned off simultaneously and second switch SW2 and third switch SW3 are turned on simultaneously. Thus, second DC signal Vdc2 is transmitted through second switch SW2 to second node 2. The voltage of second node 2 equals the voltage of second DC signal Vdc2. The voltage of first node 1 is transmitted through third switch SW3 to output node 12, such that voltage of output node 12 equals the voltage of first node 1.
FIG. 4 is a schematic diagram of the second state of AC signal generating circuit 30 according to an embodiment of the invention. Components of AC signal generating circuit 30 in FIG. 4 are the same as in FIG. 3, differing only in the states of first switch SW1, second switch SW2, third switch SW3 and fourth switch SW4. Each of first switch SW1, second switch SW2, third switch SW3 and fourth switch SW4 may comprise a switch transistor. The switch transistor may comprise a P-type transistor and a N-type transistor.
In FIG. 4, first switch SW1 and fourth switch SW4 are turned on simultaneously and second switch SW2 and third switch SW3 are turned off simultaneously. Thus, first DC signal Vdc1 is transmitted through first switch SW1 to first node 1. The voltage of first node 1 equals the voltage of first DC signal Vdc1. The voltage of second node 2 is transmitted through fourth switch SW4 to output node 12, so the voltage of output node 12 equals the voltage of second node 2.
FIG. 5 is a timing diagram of AC voltage signal VCOM, first DC signal Vdc1, second DC signal Vdc2 and AC voltage signal VCOMP of output node 12 according to an embodiment of the invention. When AC signal generating circuit 30 is at the first state S1, first switch SW1 and fourth switch SW4 are turned off simultaneously, and second switch SW2 and third switch SW3 are turned on simultaneously. The voltage of second node 2 equals the voltage of second DC signal Vdc2. The voltage of output node 12 equals the voltage of first node 1. Before entering the first state S1, the voltage of first node 1 equals the voltage of first DC signal Vdc1. Upon entering the first state S1, the cross voltage of first capacitor C1 cannot change immediately. Thus, the voltage of first node 1 is VCOMPL=VCOML−(VCOMH−Vdc1) of which VCOMH and VCOML are respectively the highest voltage and the lowest voltage of AC voltage signal VCOM and VCOMPH and VCOMPL are respectively the highest voltage and the lowest voltage of AC voltage signal VCOMP.
As shown in FIGS. 3, 4, and 5, when AC signal generating circuit 30 is at the second state S2, first switch SW1 and fourth switch SW4 are turned on simultaneously, and second switch SW2 and third switch SW3 are turned off simultaneously. The voltage of first node 1 equals the voltage of first DC signal Vdc1. The voltage of output node 12 equals the voltage of second node 2. Before entering the second state S2 (at the first state S1), the voltage of second node 2 equals the voltage of second DC signal Vdc2. Upon entering the first state S2, the cross voltage of second capacitor C2 cannot be changed immediately. Thus, the voltage of second node 2 is VCOMPH=VCOMH+(Vdc2−VCOML).
As shown in FIG. 5, the voltage amplitude of AC voltage signal VCOM is A1=VCOMH−VCOML. The voltage amplitude of output node 12 is A2=VCOMPH−VCOMPL. Voltage amplitude A1 exceeds voltage amplitude A2. Thus, AC signal generating circuit 30 provides the voltage amplitude of AC voltage signal VCOMP which exceeds the voltage amplitude of AC voltage signal VCOM.
FIG. 6 shows AC signal generating circuit 60 according to another embodiment of the invention. AC signal generating circuit 60 comprises first capacitor C1, second capacitor C2, first switch SW1, second switch SW2, third switch SW3, fourth switch SW4 and control signal generator 62. The difference between AC signal generating circuit 60 in FIG. 6 and AC signal generating circuit 30 in FIG. 3 is that control signal generator 62 controls first switch SW1, second switch SW2, third switch SW3 and fourth switch SW4 which are implemented by transmission gates.
In FIG. 6, each transmission gate comprises a P-type transistor and an N-type transistor. Each transmission gate comprises a first terminal, a second terminal, a third terminal and a fourth terminal. The P-type transistor is coupled to the first terminal, the second terminal and the fourth terminal. The N-type transistor is coupled to the first terminal, the third terminal and the fourth terminal. Control signal generator 62 is coupled to the second terminal and the third terminal. Since the operation of AC signal generating circuit 60 in FIG. 6 is similar to the operation of AC signal generating circuit 30 in FIGS. 3 and 4, it is not detailed here.
FIG. 7 shows large scale AC signal generating architecture 70 according to another embodiment of the invention. Large scale AC signal generating architecture 70 comprises control signal generator 71 and large scale AC signal generating circuit 72. Control signal generator 71 is disposed on the driving IC. Large scale AC signal generating circuit 72 is disposed on the glass panel. Control signal generator 71 is electrically coupled to large scale AC signal generating circuit 72. Control signal generator 71 transmits first DC voltage signal Vdc1, second DC voltage signal Vdc2 and AC voltage signal VCOM to large scale AC signal generating circuit 72. Large scale AC signal generating circuit 72 generates AC voltage signal VCOMP according to first DC voltage signal Vdc1, second DC voltage signal Vdc2 and AC voltage signal VCOM. Due to large scale AC signal generating circuit 72, the driving IC can utilize a process with lower voltage grade, thereby potentially reducing costs.
FIG. 8 schematically shows another embodiment of a system for displaying images which, in this case, is implemented as electronic device 600, which incorporates a display panel 400. As shown in FIG. 8, display panel 400 comprises an AC signal generating circuit, such as circuit 30 of FIG. 3, and a power supply 500. Power supply 500 is operatively coupled to display panel 400 and provides power to display panel 400. Electronic device 600 can be a mobile phone, digital camera, PDA (personal data assistant), notebook computer, desktop computer, television, or portable DVD player, for example.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (20)

1. A system for displaying images, comprising:
an AC signal generating circuit, comprising:
a first capacitor coupled between a first node and an AC signal;
a second capacitor coupled between a second node and the AC signal;
a first switch coupled between the first node and a first DC signal;
a second switch coupled between the second node and a second DC signal;
a third switch coupled between the first node and an output terminal; and
a fourth switch coupled between the second node and the output terminal;
wherein the first switch and the fourth switch are synchronous, the second switch and the third switch are synchronous, and the first switch and the second switch are asynchronous.
2. The system as claimed in claim 1, further comprising a control signal generator operative to control the first switch, the second switch, the third switch and the fourth switch.
3. The system as claimed in claim 2, wherein each of the first switch, the second switch, the third switch and the fourth switch comprises a switch transistor.
4. The system as claimed in claim 3, wherein each said switch transistor is a transmission gate comprising a first terminal, a second terminal, a third terminal and a fourth terminal.
5. The system as claimed in claim 4, wherein the control signal generator is coupled to the second terminal and the third terminal.
6. The system as claimed in claim 1, wherein voltage range of the output terminal exceeds voltage range of the AC signal.
7. The system as claimed in claim 1, further comprising a display panel, wherein the AC signal generating circuit forms a portion of the display panel.
8. The system as claimed in claim 7, further comprising an electronic device, wherein the electronic device comprises:
the display panel; and
a power supply coupled to and operative to provide power to the display panel.
9. A system for generating an AC signal comprising:
an AC signal generating circuit comprising a first capacitor coupled between a first node and an AC signal, a second capacitor coupled between a second node and the AC signal, a first switch coupled between the first node and a first DC signal, a second switch coupled between the second node and a second DC signal, a third switch coupled between the first node and an output terminal, and a fourth switch coupled between the second node and the output terminal:
wherein:
during a first period, the AC signal generating circuit is operative to turn on the second switch and the third switch and turn off the first switch and the fourth switch such that voltage of the first node is transmitted through the third switch to the output terminal, and a second DC signal is transmitted through the second switch to the second node; and
during a second period, the AC signal generating circuit is operative to turn off the second switch and the third switch and turn on the first switch and the fourth switch such that voltage of the second node is transmitted through the fourth switch to the output terminal, and a first DC signal is transmitted through the first switch to the first node.
10. The system as claimed in claim 9, further comprising means for controlling the first switch, the second switch, the third switch and the fourth switch.
11. The system as claimed in claim 9, wherein each of the first switch, the second switch, the third switch and the fourth switch comprises a switch transistor.
12. The system as claimed in claim 11, wherein each said switch transistor is a transmission gate comprising a first terminal, a second terminal, a third terminal and a fourth terminal.
13. The system as claimed in claim 12, further comprising a control signal generator coupled to the second terminal and the third terminal of at least one said switch transistor.
14. The system as claimed in claim 9, wherein output voltage of the output terminal is configured to be applied in a display panel.
15. A method for driving an AC signal generating circuit, the AC signal generating circuit comprising a first capacitor coupled between a first node and an AC signal, a second capacitor coupled between a second node and the AC signal, a first switch coupled between the first node and a first DC signal, a second switch coupled between the second node and a second DC signal, a third switch coupled between the first node and an output terminal, and a fourth switch coupled between the second node and the output terminal, the method comprising:
providing the AC signal to the first capacitor and the second capacitor;
providing the first DC signal through the first switch to the first node; and
providing the second DC signal through the second switch to the second node;
wherein the first switch and the fourth switch are synchronous, the second switch and the third switch are synchronous and the first switch and the second switch are asynchronous.
16. The method as claimed in claim 15, further comprising a control signal generator controlling the first switch, the second switch, the third switch and the fourth switch.
17. The method as claimed in claim 16, wherein each of the first switch, the second switch, the third switch and the fourth switch comprises a switch transistor.
18. The method as claimed in claim 17, wherein the switch transistor is a transmission gate comprising a first terminal, a second terminal, a third terminal and a fourth terminal.
19. The method as claimed in claim 18, wherein the transmission gate comprises a P-type transistor coupled to the first terminal, the second terminal and the fourth terminal and a N-type transistor coupled to the first terminal, the third terminal and the fourth terminal.
20. The method as claimed in claim 19, wherein the control signal generator is coupled to the second terminal and the third terminal.
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