JP3684699B2 - D / A converter, liquid crystal panel substrate and liquid crystal display device - Google Patents

Description

となる。なお、i＝0,1,2,3,4,5である。また、Ｄiは、デジタル信号Ｄ0 〜Ｄ5 の各信号レベルに対応して「Ｈ」レベルのときを「１」とし、「Ｌ」レベルのときを「０」としたものである。
【００９０】
こうして得られた電位がアナログ出力として、出力端子１０２ａから取り出される。
【００９１】
図４は、上記Ｄ／Ａ変換回路１００のＤ／Ａコンバータ特性を示す図である。なお、このＤ／Ａ変換回路１００では、変換容量Ｃxiは全て等しく1.0 pＦであり、基準容量Ｃs は2.0 pＦである。変換選択配線１１０〜１１５の電位Ｖx0,Ｖx1,Ｖx2,Ｖx3,Ｖx4,Ｖx5は、0.5, 1.0, 2.0, 4.0, 8.0, 16.0 Ｖと、公比２の等比数列をなしている。変換基準配線１１８の電位Ｖxsは、4.0Ｖである。また、共通電位配線１１９の電位Ｖcom は、ＧＮＤ電位となっている。
【００９２】
図４に示すように、６ビットのデジタル入力値とアナログ出力との間には、完全な線形性があることが分かる。その理由は、アナログ出力Ｖout を導く（２・７）式において、分母の（ΣＣxi＋Ｃs）の値が、デジタル入力値にかかわらず定数となっているからである。そして、デジタル入力値とアナログ出力とは、正比例の関係になるので、Ｄ／Ａ変換回路１００は線形特性を有する。なお、図４において、デジタル入力値が０のときでもアナログ出力は、１Ｖとなっている。これは、デジタル入力値が０でも基準容量Ｃs には電荷が蓄積されるからである。
【００９３】
次に、図５は、上記Ｄ／Ａ変換回路１００を用いた液晶表示装置の駆動方法を示す図である。言い換えると、図２に示す液晶表示装置用の駆動回路の動作を説明する図である。
【００９４】
図５に示すように、液晶駆動の１水平走査期間Ｔh は、走査信号の選択期間Ｔs と、選択期間Ｔs と次の選択期間Ｔs との間のブランキング期間Ｔb と、からなる。
【００９５】
選択期間Ｔs において、時刻ｔ0 〜ｔ1 の間に、デジタル信号Ｄ0 〜Ｄ5 が、サンプリングパルスＳＰ0 〜ＳＰn によってラッチ回路Ａ0 〜Ａ5 に取り込まれる。
【００９６】
ブランキング期間Ｔb は、次の選択期間Ｔs に移る前の期間であって、この期間を利用してＤ／Ａ変換を含む種々の処理が行われる。
【００９７】
ブランキング期間Ｔb において、時刻ｔ2 では、結合パルスＣＰが「Ｌ」となってアナログスイッチＴc10 〜Ｔc15 がオフになり、変換容量Ｃx0〜Ｃx5と基準容量Ｃs とが電気的に切断される。次に、時刻ｔ3 では、ラッチパルスＬＰによって、ラッチ回路Ａ0 〜Ａ5 に取り込まれた信号がラッチ回路Ｂ0 〜Ｂ5 に移される。
【００９８】
時刻ｔ4 では、ラッチ回路Ｂ0 〜Ｂ5 の信号と変換パルスＸＰとによって、アナログスイッチＴa10 〜Ｔa15 、Ｔb10 〜Ｔb15 が制御される。そして、変換容量Ｃx0〜Ｃx5のうち、「Ｈ」のデジタル信号に対応するものには電荷が蓄積され、「Ｌ」のデジタル信号に対応するものには電荷が蓄積されない。同時に、基準容量Ｃs には、電荷が蓄積される。なお、電荷を蓄積するために、変換パルスＸＰは、他のパルスと比較して長時間「Ｈ」状態となっている。
【００９９】
時刻ｔ5 では、変換パルスＸＰが「Ｌ」状態となって、上記電荷の蓄積が終わる。
【０１００】
そして、時刻ｔ6 で、結合パルスＣＰによって変換容量Ｃx0〜Ｃx5と基準容量Ｃs とが結合されて、出力端子１０２ａから所定の出力電圧を取り出すことができる。
【０１０１】
次に、図６（Ａ）及び図６（Ｂ）は、液晶表示装置の反転駆動の動作を説明する図である。
【０１０２】
液晶駆動装置では、液晶の品質劣化を防止する等の理由から、反転駆動が行われる。そこで、上記Ｄ／Ａ変換回路１００を含む駆動回路５０（図２及び図３）でも、図６（Ａ）及び図６（Ｂ）に示すように反転駆動が行われる。詳しくは、この反転駆動は、１水平走査線ごと、かつ、１画面ごとに行われ、１信号線ごとには反転しないようになっている。
【０１０３】
図６（Ａ）には、変換選択配線１１０〜１１５の電位Ｖx0, Ｖx1, Ｖx2, Ｖx3, Ｖx4, Ｖx5及び変換基準配線１１８の電位Ｖxsの供給方法が示されている。図６（Ｂ）には、それぞれの電位の具体的な数値が示されている。
【０１０４】
このＤ／Ａ変換回路１００では、変換容量Ｃxiは全て等しく1.0 pＦであり、基準容量Ｃs は2.0 pＦである。また、共通電位配線１１９の電位Ｖcom は、ＧＮＤ電位となっている。
【０１０５】
そして、図６（Ａ）に示すようにして、反転駆動が行われる。なお、動作の詳細は周知であるので説明を省略する。
【０１０６】
（第１実施形態の調整方法）
上記Ｄ／Ａ変換回路１００は、変換容量Ｃx0〜Ｃx5を全て同一の容量値とし、それぞれに２進加重された電圧を印加することで、Ｄ／Ａ変換を行えるようになっている。ここで、容量の容量値は製造後に変更することが困難である一方、電圧を変更することは容易に行うことができる。そこで、上記変換容量Ｃx0〜Ｃx5の容量値が、上述した設計値と異なった場合の電圧の調整方法を以下説明する。
【０１０７】
まず、図７（Ａ）に、変換容量Ｃxi′の容量値が設計値Ｃxi（1.0pF）と異なるが、容量値の平均が設計値と等しい例を示す。この例において、変換選択配線１１０〜１１５には、設計上の電位Ｖxi0 を調整して電位Ｖxi′が供給される。なお、i＝0,1,2,3,4,5 である。詳しくは、
Ｖxi′＝（Ｃxi／Ｃxi′）×Ｖxi0
となるように調整されている。例えば、最下位ビットでは、
Ｃx0＝1.0pF、Ｃx0′＝0.9pF、Ｖx0＝0.5Ｖであるから、
Ｖx0′＝（1.0／0.9）×0.5＝0.5556 Ｖ
となる。
【０１０８】
次に、図７（Ｂ）に、変換容量Ｃxi″の容量値が設計値と異なり、かつ、容量値の平均が設計値と異なる例を示す。この例においては、
Ｖxi″
＝（Ｃxi0／Ｃxi″）×（ΣＣxi″＋Ｃs ）／（ΣＣxi0＋Ｃs ）×Ｖxi
となるように電位Ｖxi″が調整されている。例えば、最下位ビットでは、
Ｃxi＝1.0pF、Ｃxi″＝0.9pF、ΣＣxi″＋Ｃs ＝7.4pF、ΣＣxi＋Ｃs ＝8.0pF、Ｖx0＝0.5Ｖであるから、
Ｖxi″＝（1.0／0.9）×（7.4／8.0）×0.5＝0.5139 Ｖ
となる。
【０１０９】
図７（Ａ）及び図７（Ｂ）のいずれの例においても、変換選択配線１１０〜１１５の電位Ｖxi′及びＶxi″が完全に調整され、Ｄ／Ａコンバータ特性は、図４に示すものと全く同じものが得られる。そして、変換容量Ｃx0〜Ｃx5の容量値が設計通りの値でなくとも、設計値通りのアナログ出力電圧を得ることができる。
【０１１０】
したがって、このＤ／Ａ変換回路１００を用いた液晶表示装置用の駆動回路５０によれば、逆転現象による階調反転等の画質問題は、全く発生しない。
【０１１１】
なお、本実施形態では、変換容量Ｃx0〜Ｃx5が設計値と異なる場合を考えたが、基準容量Ｃs が設計値と異なる場合も、電位Ｖx0〜Ｖx5及びＶxsを調整することで、所定の液晶印加電圧を得ることができる。また、上記調整方法では、計算によって電位の調整を行ったが、ここで説明した思想にしたがって試行錯誤によって電位を調整しても効果がある。
【０１１２】
また、今回の例では、変換容量Ｃx0〜Ｃx5の実際の値が予め分かっているものとして計算したが、現実には不明である場合が多い。このようなときにも、電位Ｖx0〜Ｖx5を調整することで、理想的なＤ／Ａコンバータ特性を得ることが可能である。
【０１１３】
なお、上記Ｄ／Ａ変換回路１００は、パッシブマトリクス型表示装置に適用したり、例えばプリント基板であってガラス基板以外に形成したり、あるいは、アモルファスシリコン、高温ポリシリコン、結晶シリコン、又はガリウム砒素等の如何なる半導体で形成しても効果がある。
【０１１４】
また、上記駆動回路５０の反転駆動は、１画面ごと又は複数画面ごと、１水平走査線ごと又は複数水平走査線ごと、あるいは１信号線ごと又は複数信号線ごとに極性反転するか否かに関わらず効果がある。
【０１１５】
本実施形態では、変換容量Ｃx0〜Ｃx5の一方の極板は、共通電位配線１１９に接続されているが、他の電位配線に接続されてもよい。また、本実施形態では、デジタル信号Ｄ0 〜Ｄ5 が「Ｌ」（オフ）のときに変換容量Ｃx0〜Ｃx5の両極板には電位Ｖcomが印加されるとしたが、これに代わって、他の電位が印加されるようにしてもよい。
【０１１６】
これらを考慮した変形例としてのＤ／Ａ変換回路２００を図８に示す。Ｄ／Ａ変換回路２００において、変換容量Ｃx0〜Ｃx5の一方の極板が、共通電位配線１１９の代わりに変換基準配線１１８に接続されている。また、変換容量Ｃx0〜Ｃx5の他方の極板は、アナログスイッチＴb10 〜Ｔb15 を介して変換基準配線１１８に接続されている。これ以外は、図１に示すＤ／Ａ変換回路１００と同様である。
【０１１７】
このＤ／Ａ変換回路２００によれば、デジタル信号Ｄ0 〜Ｄ5 が「Ｌ」（オフ）のときには、変換容量Ｃx0〜Ｃx5に電位Ｖxsが供給されるが、これらの両極板間の電位差がないので、電荷が蓄積されない。デジタル信号Ｄ0 〜Ｄ5 が「Ｈ」（オン）のときには、変換容量Ｃx0〜Ｃx5には、電位Ｖx0〜Ｖx5と電位Ｖxsとの電位差によって電荷が蓄積される。その他の動作は、Ｄ／Ａ変換回路１００と同様であるので説明を省略する。
【０１１８】
（第２実施形態）
次に、図９に、本発明の第２実施形態に係るＤ／Ａ変換回路３００を示す。このＤ／Ａ変換回路３００は、図２に示す液晶表示装置用の駆動回路５０において、Ｄ／Ａ変換回路１００の代わりに用いられる。そのときの液晶表示装置の駆動方法は、第１実施形態と同様である。また、第１実施形態と同じ構成には、同一の符号を付して説明を省略する。
【０１１９】
図１に示すＤ／Ａ変換回路１００では、公比２の等比数列をなす電位Ｖx0〜Ｖx5を供給するために変換選択配線１１０〜１１５が設けられていた。これに対して、図９に示すＤ／Ａ変換回路３００では、高電位配線３１０と低電位配線３１２との間に、抵抗Ｒx0〜Ｒx5が直列接続されている。
【０１２０】
高電位配線３１０には高電位側の電位ＶxHが、低電位配線３１２には低電位側の電位ＶxLが印加される。抵抗Ｒx0〜Ｒx5の各々の抵抗値が、公比２の等比数列をなすようにし、第１の実施形態における電位Ｖx0〜Ｖx5のうちの最高の電位Ｖx5と、高電位側の電位ＶxHが等しくなるようにし、第１の実施形態における最低の電位Ｖx0と、低電位側の電位ＶxLが等しくなるようにする。これにより、本実施形態でも第１の実施形態と等しい電位Ｖx0〜Ｖx5を、各抵抗Ｒx0〜Ｒx5の間から、分割電圧として取り出すことができる。
【０１２１】
本実施形態においても、第１の実施形態と同様に、デジタル入力とアナログ出力値の線形性が実現できる。
【０１２２】
なお、本実施形態では、１組の高電位配線３１０と低電位配線３１２が設けられたが、２組以上の高電位配線と低電位配線を設けて、各々に異なる電位を印加し、各々に複数の抵抗を直列接続することにより、第１実施形態と第２実施形態を併用することができる。
【０１２３】
（第３実施形態）
次に、図１０に、本発明の第３実施形態に係るＤ／Ａ変換回路４００を示す。このＤ／Ａ変換回路４００も、図２に示す液晶表示装置用の駆動回路５０において、Ｄ／Ａ変換回路１００の代わりに用いられる。そのときの液晶表示装置の駆動方法は、第１実施形態と同様である。また、第１実施形態と同じ構成には、同一の符号を付して説明を省略する。
【０１２４】
図１に示すＤ／Ａ変換回路１００は、複数の電位Ｖx0〜Ｖx5を供給するために、１つの変換パルス配線１１６と、複数の変換選択配線１１０〜１１５が設けられていた。これに対して、図１０に示すＤ／Ａ変換回路４００では、複数の電位を供給するために、複数の変換パルス配線４１０〜４１５と、１つの変換選択配線４２０とを有する。
【０１２５】
図１０の回路を概説すると、後段のラッチ回路Ｂ0 〜Ｂ5 の信号は、対応する変換パルス配線４１０〜４１５の変換パルスＸＰ0 〜ＸＰ5 と論理積をとってアナログスイッチＴa10 〜Ｔa15 に入力される。アナログスイッチＴa10 〜Ｔa15 は、変換容量Ｃx0〜Ｃx5に対する変換選択配線４２０の出力を制御するように接続されている。
【０１２６】
同時に、ラッチ回路Ｂ0 〜Ｂ5 の信号は、否定をとってから対応する変換パルスＸＰ0 〜ＸＰ5 と論理積をとってアナログスイッチＴb10 〜Ｔb15 に入力される。
【０１２７】
図１１に、上記Ｄ／Ａ変換回路４００を適用した液晶表示装置の駆動方法を示す。デジタル入力Ｄ0 〜Ｄ5 およびサンプリングパルスＳＲは、第１実施形態と同様のものが印加される。電位Ｖxは変換選択配線４２０に印加され、ブランキング期間において時間的に変化している。変換パルスＸＰ0 〜ＸＰ5 は、複数の変換パルス配線４１０〜４１５に印加される。
【０１２８】
図１０および図１１を参照して、本実施形態の液晶表示装置の駆動回路の動作を説明する。これらの図に示すように、電位Ｖx の変化に同調して、変換パルスＸＰ0 〜ＸＰ5 が入力されているので、所定の電位Ｖx0〜Ｖx5が選び出される。そして、デジタル入力Ｄ0 〜Ｄ5 に応じて、アナログスイッチＴa10 〜Ｔa15 が導通すれば、上記選び出された電位Ｖx0〜Ｖx5が変換容量Ｃx0〜Ｃx5に供給されて電荷が蓄積される。あるいは、アナログスイッチＴb10 〜Ｔb15 が導通すれば、電位Vcomが変換容量Ｃx0〜Ｃx5に供給されて、電荷が蓄積されない。こうして、所定のアナログ出力Ｖout を取り出すことができる。
【０１２９】
本実施形態においても、第１の実施形態と同様の効果が、実現できる。
【０１３０】
なお、変形例として、複数の変換選択配線のそれぞれに、時間的に変化する変換選択電位を印加してもよい。
【０１３１】
（第４実施形態）
次に、図１２に、本発明の第４実施形態に係るＤ／Ａ変換回路５００を示す。このＤ／Ａ変換回路５００も、図２に示す液晶表示装置用の駆動回路５０において、Ｄ／Ａ変換回路１００の代わりに用いられる。そのときの液晶表示装置の駆動方法は、第１実施形態と同様である。また、第１実施形態と同じ構成には、同一の符号を付して説明を省略する。
【０１３２】
第４実施形態は、複数の電位を選択するとともに、変換容量の容量値を異なるようにして、所定のアナログ出力電圧を得るものである。図１２において、３つの変換選択配線５１０〜５１２が形成されている。変換容量Ｃx50 〜Ｃx55の容量値は、次式を満たす。
【０１３３】
Ｃx50：Ｃx51：Ｃx52：Ｃx53：Ｃx54：Ｃx55 = 1：2：1：2：1：2
図１３に、第４実施形態に係る変換容量Ｃx50 〜Ｃx55及び基準容量Ｃs の容量値と、電位Ｖx0〜Ｖx2及び電位Ｖxsの値を示す。変換容量Ｃx50及びＣx51、Ｃx52及びＣx53、Ｃx54及びＣx55には、それぞれ、電位Ｖx0、電位Ｖx1又はＶx2から電位が供給される。
【０１３４】
本実施形態においても、第１の実施形態と同様の効果が実現できる。
【０１３５】
（第５実施形態）
次に、図１４に、第５実施形態に係る液晶表示装置の駆動方法を示す。本実施形態において、液晶表示装置の駆動回路及びＤ／Ａ変換回路は、第１の実施形態あるいは第２の実施形態と同一である。
【０１３６】
図５に示す駆動方法においては、選択期間Ｔｓにおいて、デジタル入力Ｄ0 〜Ｄ5 およびサンプリングパルスＳＲの入力が終了した後、ブランキング期間に入る。そして、ラッチパルスＬＰがオフ電位からオン電位となって再びオフ電位になる。次に、変換パルスＸＰがオフ電位からオン電位となり、再びオフ電位になる。次に、結合パルスＣＰがオフ電位からオン電位となって再びオフ電位になる。
【０１３７】
ここでは、次の条件を満たす必要がある。ラッチパルスＬＰの入力がデジタル入力Ｄ0 〜Ｄ5 およびサンプリングパルスＳＲの入力終了後であること、変換パルスＸＰの入力がラッチパルスＬＰの入力終了後であること、結合パルスＣＰの入力が変換パルスＸＰの入力終了後であること、である。
【０１３８】
この条件を満たす限り、変換パルスＸＰおよび結合パルスＣＰのオンオフは、選択期間Ｔｓとブランキング期間Ｔｂのどちらで行われてもよい。また、ラッチパルスＬＰと結合パルスＣＰは、入力期間が重複していてもよい。
【０１３９】
そこで、変換容量Ｃx0〜Ｃx5及び基準容量Ｃs への充電、および、変換容量Ｃx0〜Ｃx5に保持された電荷の基準容量Ｃs への供給を、全て十分に行うために、変換パルスＸＰのオン期間の長さと、結合パルスＣＰのオン期間の長さを最適化することが好ましい。
【０１４０】
特に、選択期間Ｔs に比べてブランキング期間Ｔb が短い場合に、変換パルスＸＰのオン電位終了がブランキング期間Ｔb 中に行うと、変換容量Ｃx0〜Ｃx5への充電と、基準容量Ｃs への充電が不十分となる可能性がある。
【０１４１】
そこで、本実施形態では、変換パルスＸＰのオン電位終了を選択期間Ｔs 中に行うことで、これらの充電を十分に行うことができる。
【０１４２】
本実施形態においても、第１の実施形態と同様の効果が実現できる。
【０１４３】
なお、本実施形態は、電位Ｖx0〜Ｖx5が、複数の変換選択配線によって、または分割抵抗によって与えられる場合のみならず、１つの変換選択配線に時間変化する電位が印加される場合にも、適用することができる。
【０１４４】
（第６実施形態）
次に、図１５に、本発明の第６実施形態に係るＤ／Ａ変換回路６００を示す。このＤ／Ａ変換回路６００も、図２に示す液晶表示装置用の駆動回路５０において、Ｄ／Ａ変換回路１００の代わりに用いられる。そのときの液晶表示装置の駆動方法は、第１実施形態と同様である。また、第１実施形態と同じ構成には、同一の符号を付して説明を省略する。
【０１４５】
薄膜トランジスタ、とくに、低温プロセスによるポリシリコン薄膜トランジスタは、オフ時のリーク電流が大きい。そこで、本実施形態では、薄膜トランジスタからなる一対のアナログスイッチＴa10 〜Ｔa15 を直列に接続した。この構成によれば、オフ時のリーク電流を低減でき、また、片方の薄膜トランジスタの突発的なオフ特性の劣化も、他方の薄膜トランジスタにより補償することができる。
【０１４６】
本実施形態においても、第１の実施形態と同様の効果が実現できる。
【０１４７】
なお、変形例として、アナログスイッチＴb10 〜Ｔb15 、Ｔc10 〜Ｔc15 及びＴs 、又は図２に示すシフトレジスタ２０、ラッチ回路Ａ0 〜Ａ5 及びＢ0 〜Ｂ5 等の全ての素子に対して、２つの薄膜トランジスタを直列に接続する構成が考えられる。また、３つ以上の薄膜トランジスタを直列に接続する構成も考えられる。
【０１４８】
（第７実施形態）
次に、図１６に、本発明の第７実施形態に係るＤ／Ａ変換回路７００を示す。このＤ／Ａ変換回路７００も、図２に示す液晶表示装置用の駆動回路５０において、Ｄ／Ａ変換回路１００の代わりに用いられる。そのときの液晶表示装置の駆動方法は、第１実施形態と同様である。また、第１実施形態と同じ構成には、同一の符号を付して説明を省略する。
【０１４９】
薄膜、とくに、低温プロセスによるポリシリコン薄膜によって形成されたＭＯＳ形トランジスタは、しきい値電圧が高いことに加えて、オン時の充電電流が小さい。そして、ｎチャネル形トランジスタは、オン時に、ゲートにプラスの電位が印加されるので、ソース又はドレインの電位が高いと、その電位とゲートの電位との差が小さくなって動作速度が遅くなる。また、ｐチャネル形トランジスタは、オン時に、ゲートにマイナスの電位が印加されるので、ソース又はドレインの電位が低いと、その電位とゲートの電位との差が小さくなって動作速度が遅くなる。
【０１５０】
そこで、第７実施形態では、ｎチャネルのトランジスタとｐチャネルのトランジスタが並列に接続されるＣＭＯＳ構造のアナログスイッチＴb70 〜Ｔb75 が採用されている。そして、ソース又はドレインの電位に関わらず、良好な充電特性が得られるようになっている。
【０１５１】
本実施形態においても、第１の実施形態と同様の効果が実現できる。
【０１５２】
なお、ＣＭＯＳ構造は、アナログスイッチＴa10 〜Ｔa15 、Ｔc10 〜Ｔc15 及びＴs 、又は図２に示すシフトレジスタ２０、ラッチ回路Ａ0 〜Ａ5 及びＢ0 〜Ｂ5 等の全ての素子に対して、適用することができる。
【０１５３】
（第８実施形態）
次に、図１７（Ａ）及び図１７（Ｂ）に、第８実施形態に係る液晶表示装置の駆動方法を示す。本実施形態において、液晶表示装置の駆動回路及びＤ／Ａ変換回路は、第１の実施形態と同一である。
【０１５４】
図１７（Ａ）に、電位Ｖx0〜Ｖx5、Ｖxs、Ｖcom の与え方を、図１７（Ｂ）に、これらの電位を示す。なお、変換容量Ｃx0〜Ｃx5は全て等しく1.0 pＦであり、基準容量Ｃs は2.0 pＦである。
【０１５５】
本実施形態では、電位Ｖx0〜Ｖx5および電位Ｖxsが、１画面ごとに、かつ、１水平走査線ごとに極性反転し、１信号線ごとには反転しない駆動を行っている。電位Ｖcom も、電位Ｖx0〜Ｖx5およびＶxsに同調して極性反転している。ただし、逆極性の反転である。
【０１５６】
本実施形態の特徴は、電位Ｖcom が極性反転していることである。この電位Ｖcom は、液晶を挟持する電極の一方に印加される。電極の他方には、出力端子１０２ａ（図１参照）からのアナログ出力Ｖout が印加される。電位Ｖcom が極性反転することで両電極間の電位差を形成できる。この電位差は、液晶駆動に必要な電圧の一部となる。したがって、バイアス電圧が必要なときに、デジタル入力値が０のときのアナログ出力Ｖout が小さくてもよい。つまり、基準容量Ｃs に印加する電圧を小さくすることができる。
【０１５７】
本実施形態において、電位Ｖcom の片側振幅は１Ｖであり、電位Ｖxsは０Ｖである。
【０１５８】
電位Ｖcom の振幅をさらに上げると、同じＤ／Ａコンバータ特性を得るためには、電位Ｖxsを反転駆動する必要がある。電位Ｖxsの反転は、電位Ｖx0〜Ｖx5と逆極性である。また、電位Ｖcom 、Ｖxsの振幅を調整することで、電源電圧の電圧値の低減や、電圧レベルの削減が可能となる。
【０１５９】
本実施形態においても、第１の実施形態と同様の効果が、実現できる。
【０１６０】
（第９実施形態）
次に、図１８に、第９実施形態に係る液晶表示装置の駆動方法を示す。本実施形態において、液晶表示装置の駆動回路及びＤ／Ａ変換回路は、第１の実施形態と同一である。
【０１６１】
図１８（Ａ）に、電位Ｖx0〜Ｖx5、ＶxsおよびＶcom の与え方を、図１８（Ｂ）に、電位Ｖx0〜Ｖx5、ＶxsおよびＶcom の値を示す。本実施形態では、電位Ｖx0〜Ｖx5およびＶxsが、１画面ごと、かつ、１水平走査線ごとに反転し、１信号線ごとには反転しない駆動を行っている。電位Ｖcom は定電位である。
【０１６２】
本実施形態の特徴は、電位Ｖx0〜Ｖx5と電位Ｖxsとが、互いに逆位相で極性反転していることである。したがって、図１に示すＤ／Ａ変換回路１００において、基準容量Ｃs に蓄積される電荷と、変換容量Ｃx0〜Ｃx5に蓄積される電荷とは、極性が逆になる。そして、基準容量Ｃs の電荷と変換容量Ｃx0〜Ｃx5の電荷とが合成されると、総電荷が減少し、これまでの加算型とは異なる、いわゆる減算型のＤ／Ａ変換を行うことができる。
【０１６３】
図１９に、この実施形態に係るＤ／Ａコンバータ特性を示す。減算型であるために、図４に示す特性とは傾きが逆であるが、全てのデジタル入力値（０〜６３）にわたって、アナログ出力は１Ｖ〜５Ｖで完全な線形性が実現されていることがわかる。
【０１６４】
本実施形態においても、第１の実施形態と同様の効果が実現できる。
【０１６５】
なお、上記実施形態において、電位Ｖcom 及びＶxsの振幅を調整して、電源電圧の電圧値の低減や、電圧レベル数の削減が可能となる。その例を、図２０（Ａ）及び図２０（Ｂ）を参照して説明する。
【０１６６】
図２０（Ａ）に、第９実施形態の変形例において、電位Ｖx0〜Ｖx5、ＶxsおよびＶcom の与え方を示し、図２０（Ｂ）に、電位Ｖx0〜Ｖx5、ＶxsおよびＶcom の値を示す。これらの図に示すように、電位Ｖcom も、電位Ｖx0〜Ｖx5および変換基準電位Ｖxsに同調して極性反転している。また、電位Ｖcom の極性反転は、電位Ｖxsの極性反転と逆位相である。
【０１６７】
第８実施形態に関して上述したように、液晶を挟持する電極の一方に、電位Ｖcom が印加され、駆動に必要な電圧の一部を負担する。したがって、この変形例においても、極性反転する電位Ｖcom が一方の電極に印加されるため、他方の電極に印加される電位Ｖxsは小さくてよい。具体的には、電位Ｖcom の振幅が３Ｖで、電位Ｖxsの振幅は逆極性で８Ｖである。この値は、図１８に示す値と比べて、極めて小さな値であり、消費電力低減に効果的である。
【０１６８】
なお、本発明に係る液晶表示装置は、直視型のみならず投写型のものも含む。
【０１６９】
また、本発明に係るＤ／Ａ変換回路は、光シャッタのような周知の液晶光学装置に適用することもできる。
【０１７０】
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係るＤ／Ａ変換回路を示す図である。
【図２】本発明の第１の実施形態に係る液晶表示装置用の駆動回路を示す図である。
【図３】本発明の第１の実施形態に係る液晶表示装置を示す図である。
【図４】本発明の第１の実施形態に係るＤ／Ａコンバータ特性を示す図である。
【図５】本発明の第１の実施形態に係る液晶表示装置の駆動方法を示す図である。
【図６】図６（Ａ）及び図６（Ｂ）は、液晶表示装置の反転駆動の動作を説明する図である。
【図７】図７（Ａ）及び図７（Ｂ）は、第１の実施形態における変換容量及び電位の調整方法を説明する図である。
【図８】本発明の第１実施形態の変形例を示す図である。
【図９】本発明の第２実施形態に係るＤ／Ａ変換回路を示す図である。
【図１０】本発明の第３実施形態に係るＤ／Ａ変換回路を示す図である。
【図１１】図１０に示すＤ／Ａ変換回路を適用した液晶表示装置の駆動方法を示す図である。
【図１２】本発明の第４実施形態に係るＤ／Ａ変換回路を示す図である。
【図１３】第４実施形態における変換容量の容量値及び電位を示す図である。
【図１４】本発明の第５実施形態に係る液晶表示装置の駆動方法を示す図である。
【図１５】本発明の第６実施形態に係るＤ／Ａ変換回路を示す図である。
【図１６】本発明の第７実施形態に係るＤ／Ａ変換回路を示す図である。
【図１７】図１７（Ａ）及び図１７（Ｂ）は、本発明の第８実施形態に係る液晶表示装置の駆動方法示す図である。
【図１８】図１８（Ａ）及び図１８（Ｂ）は、本発明の第９実施形態に係る液晶表示装置の駆動方法を示す図である。
【図１９】第９実施形態のＤ／Ａコンバータ特性を示す。
【図２０】図２０（Ａ）及び図２０（Ｂ）は、第９実施形態の駆動方法の変形例を示す図である。
【図２１】従来の二進荷重キャパシタを使用したＤ／Ａ変換回路を示す図である。
【図２２】従来のＤ／Ａ変換器のＤ／Ａコンバータ特性の一例を示す図である。
【符号の説明】
１１０〜１１５、４２０ 変換選択配線
１０２ 出力配線
１１８ 変換基準配線（基準配線）
１１９ 共通配線（基準配線）
３１０ 高電位配線
３１２ 低電位配線
４１０〜４１５ 変換パルス配線
Ｃx0〜Ｃx5 変換容量
Ｄ0 〜Ｄ5 デジタル信号
Ｒx0〜Ｒx4 抵抗
Ｔa10 〜Ｔa15 、Ｔb10 〜Ｔb15 、Ｔc10 〜Ｔc15、Ｔs アナログスイッチ（スイッチ）[0001]
BACKGROUND OF THE INVENTION
The present invention provides a D / A converter, liquid The present invention relates to a crystal panel substrate and a liquid crystal display device.
[0002]
BACKGROUND OF THE INVENTION
Some D / A converters use capacitors and others use resistors. A D / A converter using a capacitor is superior to a resistor using a resistor in terms of low power consumption. As a D / A converter using a capacitor, one using a binary load capacitor is known. FIG. 21 is a diagram showing a D / A converter using a conventional binary load capacitor.
[0003]
In this D / A converter, an analog output corresponding to a 6-bit digital input value is obtained. Specifically, digital signals D0 to D5 corresponding to the first digit to the sixth digit of the binary number are input to each of the six digital wirings 1001, and “000000” to “111111” (“0 in decimal number”). ”To“ 63 ”).
[0004]
The digital signals D0 to D5 are held in the two-stage latch circuits A0 to A5 and B0 to B5. The latch circuits A0 to A5 or B0 to B5 operate with the clock CL1 or CL2 and its inverted clock nCL1 or nCL2. The clocks CL1 and CL2 and the inverted clocks nCL1 and nCL2 are generated from output signals of a shift register (not shown).
[0005]
The D / A converter is provided with a wiring 1002 (potential V0), a wiring 1003 (potential Vs), and a wiring 1004 (GND potential). Note that the potential V0> the potential Vs> the GND potential. An analog output can be taken out from the wiring 1005.
[0006]
One electrode plate of conversion capacitors C0 to C5 is connected to the wiring 1002. The conversion capacities C0 to C5 are designed to have a binary load.
C0: C1: C2: C3: C4: C5 = 1: 2: 4: 8: 16: 32
Ratio.
[0007]
The operation of this D / A converter will be described taking as an example the case where a digital input of “000001” is made. At this time, since the digital signal D0 is “H”, the latch circuit A0 holds “H”. Since the digital signals D1 to D5 are "L", the latch circuits A1 to A5 hold "L". When a latch pulse is input, the signals of the latch circuits A1 to A5 at the first stage are transferred to the latch circuits B1 to B5 at the second stage by the clock CL2 and the inverted clock nCL2.
[0008]
Next, the reset signal R of the wiring 1006 becomes “H”, the analog switches Ta0 to Ta5 are turned on, and the conversion capacitors C0 to C5 have no potential difference between their bipolar plates, so that there is no charge. At the same time, the analog switch T3 is turned on, and a predetermined charge is accumulated in the reference capacitor Cs due to the potential difference between the wiring 1003 (potential Vs) and the wiring 1004 (GND potential). The charge Qs stored in the reference capacitor Cs at this time is
Qs = CsVs (1 ・ 1)
It is.
[0009]
Next, the reset signal R becomes “L” and the analog switches Ta0 to Ta5 and T3 are turned off. Then, the set signal S of the wiring 1007 becomes the “H” state, and the analog switch Tb0 is obtained by the logical product of the signal level “H” of the set signal S and the signal level “H” or “L” of the latch circuits B0 to B5. ~ Tb5 is controlled.
[0010]
Specifically, the analog switch Tb0 corresponding to the latch circuit B0 is turned on, and the conversion capacitor C0 and the reference capacitor Cs are connected. A part of the charge Qs stored in the reference capacitor Cs flows into the conversion capacitor C0.
[0011]
On the other hand, the analog switches Tb1 to Tb5 corresponding to the latch circuits B1 to B5 are turned off, and the conversion capacitors C1 to C5 are not connected to the reference capacitor Cs.
[0012]
As a result, the potential Vout of the wiring 1005 is obtained as follows. The charge Qs stored in the reference capacitor Cs flows into the conversion capacitor C0. If the charge stored in the reference capacitor Cs at this time is Qs 'and the charge stored in the conversion capacitor C0 is Q0',
Qs' = CsVout (1 ・ 2)
Q0 '= C0 (Vout-V0) (1/3)
Since Qs = Qs ′ + Q0 ′, from equations (1 · 1) to (1 · 3),
CsVs = CsVout + C0 (Vout-V0)
It becomes. Transform this,
Vout = (CsVs + C0V0) / (Cs + C0)
It becomes. What has been described above is an example when a digital input of “000001” is made.
Vout = (CsVs + V0ΣDiCi) / (Cs + ΣDiCi) (1 · 4)
It becomes. Note that i = 0,1,2,3,4,5. Di is set to “1” when it is “H” level and “0” when it is “L” level corresponding to each signal level of the digital signals D0 to D5.
[0013]
Next, FIG. 22 is a diagram showing an example of the D / A converter characteristic of the conventional D / A converter. As shown in the figure, the relationship between the digital input value and the analog output draws a gentle curve. That is, the conventional D / A converter cannot obtain a D / A converter characteristic having linearity.
[0014]
The reason for this is that in equation (1 · 4), there is a variable (ΣDiCi) of the digital signals D0 to D5 in the denominator, so it is not a directly proportional function. To avoid this, the denominator must be a constant.
[0015]
In addition, the conventional D / A converter sometimes fails to obtain a predetermined analog voltage. For example, in FIG. 22, the analog output when the digital input value is “32” (binary number “100000”) decreases more discontinuously than when the digital input value is “31” (binary number “011111”). Yes. The reason is that the ratio between the capacitance value of the conversion capacitor C5 corresponding to the most significant bit and the sum of the capacitance values of the lower-bit conversion capacitors C0 to C4 is not 32:31.
[0016]
In the capacity manufacturing process, it is difficult to avoid such variations in the capacitance value. In particular, the capacity of the large capacity value tends to increase an error from the design value. For this reason, a predetermined analog output cannot be obtained with respect to the digital input value, and a so-called reverse phenomenon occurs in which the analog output decreases as the digital input increases.
[0017]
Accordingly, an object of the present invention is to provide a D / A converter having linearity and not causing a reverse phenomenon, liquid An object is to obtain a crystal panel substrate and a liquid crystal display device.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, a D / A converter according to the present invention converts a digital signal Di (i = 1, 2,..., N) of n bits (n is a natural number) into an analog output Vout. In the A converter,
N conversion capacitors Cxi corresponding to each bit of the digital signal Di;
At least one conversion selection wiring to which n kinds of potentials Vxi corresponding to each bit of the digital signal Di are supplied;
Output wiring for taking out the analog output Vout;
A first reference wiring having a potential Vs1 connected to one electrode plate of the conversion capacitor Cxi;
Have
The other electrode plate of the conversion capacitor Cxi corresponding to the ON digital signal Di is connected to the conversion selection wiring, and the conversion charge is accumulated in the conversion capacitor Cxi by the potential difference between the corresponding potentials Vxi and Vs1,
The other electrode plate of the conversion capacitor Cxi corresponding to the off digital signal Di is connected to a predetermined wiring,
After the conversion charge is accumulated, the other electrode plate is electrically disconnected from the conversion selection wiring and the predetermined wiring, connected to the output wiring, and summed up the respective conversion charges. An analog output Vout is supplied corresponding to the total charge.
[0019]
According to the present invention, conversion capacitors Cx1 to Cxn are provided corresponding to the digital signals D1 to Dn. The potential Vs1 is supplied to one electrode plate of the conversion capacitors Cx1 to Cxn. Potentials Vx1 to Vxn or a predetermined potential can be supplied to the other electrode plates of the conversion capacitors Cx1 to Cxn.
[0020]
If the digital signals D1 to Dn are turned on, the potentials Vx1 to Vxn are supplied to the other electrode plates of the conversion capacitors Cx1 to Cxn, and charges are accumulated by the potential difference with the potential Vs1.
[0021]
If the digital signals D1 to Dn are off, a predetermined potential is supplied to the other plate of the conversion capacitors Cx1 to Cxn. For example, if this potential is the same as the potential of one plate, no charge is accumulated. . Specifically, if the other electrode plates of the conversion capacitors Cx1 to Cxn are connected to the first reference wiring, the potentials of both electrode plates are the same.
[0022]
Alternatively, when the digital signals D1 to Dn are off, the other electrode plate of the conversion capacitors Cx1 to Cxn may be connected to a wiring different from the first reference wiring.
[0023]
As described above, the charges accumulated in the conversion capacitors Cx1 to Cxn are changed by turning on / off the digital signals D1 to Dn. Therefore, D / A conversion can be performed if the potentials Vx1 to Vxn and a predetermined potential are set so that the digital input value represented by the on / off of the digital signals D1 to Dn corresponds to the analog output. it can. The set potential can be easily adjusted even after the D / A converter is manufactured. By adjusting this potential, the D / A conversion characteristics have continuity.
[0024]
The D / A converter according to the present invention is
A second reference wiring having a potential Vs2;
A reference capacitor Cs formed in the output wiring and storing a reference charge by a potential difference between the potentials Vs1 and Vs2 in the first and second reference wirings;
Have
The predetermined wiring corresponding to the off digital signal Di is the first reference wiring;
The total charge consists of the sum of the converted charge and the reference charge,
Analog output Vout is
Vout = (ΣCxi (DiVxi + Vs1 (1-Di)) + CsVs2) / (ΣCxi + Cs) [Di is 1 when the digital signal Di is on and 0 when it is off. It is preferable that it is represented by.
[0025]
In the present invention, when the digital signals D1 to Dn are off, the same potential Vs1 is supplied to the bipolar plates of the conversion capacitors Cx1 to Cxn, so that no charge is accumulated.
[0026]
In addition, the output wiring is given a charge to the reference capacitor Cs regardless of whether the digital signals D1 to Dn are turned on or off, and the analog output Vout is increased uniformly.
[0027]
And the said formula is calculated | required as follows. First, assuming that the sum of the charges initially accumulated in the conversion capacitor Ci is ΣQi,
ΣQi = ΣCxi (Di (Vxi−Vs1))
It becomes. Di is “1” when it is “H” level and “0” when it is “L” level, corresponding to each signal level of the digital signals D0 to D5.
[0028]
If the charge accumulated in the reference capacitor Cs is Qs,
Qs = Cs (Vs2-Vs1)
It is.
[0029]
Next, when the conversion capacitor Ci is electrically disconnected from the conversion selection wiring and the predetermined wiring and connected to the output wiring, the total charge accumulated in the conversion capacitor Ci is expressed as ΣQi ′, the reference If the charge stored in the capacitor Cs is Qs ′,
ΣQi '= ΣCxi (Vout-Vs1)
Qs' = Cs (Vout-Vs1)
It becomes.
[0030]
ΣQi + Qs = ΣQi '+ Qs'
So,
ΣCxi (Di (Vxi−Vs1)) + Cs (Vs2−Vs1)
= ΣCxi (Vout−Vs1) + Cs (Vout−Vs1)
And transform this,
Vout
= (ΣCxi (DiVxi + Vs1 (1-Di)) + CsVs2) / (ΣCxi + Cs)
It becomes.
[0031]
Since the denominator of this equation is a constant regardless of the value of the digital signal Di, the analog output Vout and the digital signal Di are directly proportional functions. As a result, a D / A conversion characteristic having linearity can be obtained.
[0032]
The D / A converter according to the present invention is
A first switch connected between the other electrode plate of the conversion capacitor Cxi and the conversion selection wiring;
A second switch connected between the other electrode plate of the conversion capacitor Cxi and the predetermined wiring;
A third switch connected between the other electrode plate of the conversion capacitor Cxi and the output wiring;
It is preferable to have.
[0033]
Alternatively, the D / A converter according to the present invention is
A first switch connected between the other electrode plate of the conversion capacitor Cxi and the conversion selection wiring;
A second switch connected between the other electrode plate of the conversion capacitor Cxi and the first reference wiring;
A third switch connected between the other electrode plate of the conversion capacitor Cxi and the output wiring;
A fourth switch for controlling application of a voltage from the first and second reference wires to the reference capacitor Cs;
It is preferable to have.
[0034]
With these switches, application of voltage to the conversion capacitor Cxi and the reference capacitor Cs can be controlled.
[0035]
In the D / A converter according to the present invention, it is preferable that n types of potentials Vxi are supplied by n conversion selection wirings. This is the simplest form for supplying n types of potentials Vxi.
[0036]
Alternatively, the D / A converter according to the present invention is
A high potential wiring, a low potential wiring, n-1 resistors connected in series between the high potential wiring and the low potential wiring;
Have
The conversion selection wiring is directly connected to the wiring between the high potential wiring and the resistor directly connected to the high potential wiring, the wiring connecting adjacent resistors, and the low potential wiring and the low potential wiring. It is preferable to be configured by wiring between the resistors.
[0037]
According to the present invention, the wiring between the high potential wiring and the resistor directly connected to the high potential wiring is the highest potential conversion selection wiring of the potential Vxi. Since the voltage drop increases as the resistance increases by one, the wiring connecting the adjacent resistors becomes a conversion selection wiring that gradually decreases in potential. The wiring between the low potential wiring and the resistor directly connected to the low potential wiring is the lowest potential conversion selection wiring.
[0038]
The D / A converter according to the present invention is
It is preferable that one conversion selection wiring is provided and n potentials Vxi are supplied by changing the potential supplied to the conversion selection wiring over time.
[0039]
Specifically, the D / A converter according to the present invention is:
N conversion pulse wirings corresponding to the n conversion capacitors Cxi,
A pulse signal is applied to each conversion pulse wiring when the potential that changes in the conversion selection wiring becomes the potential Vxi supplied to the corresponding conversion capacitor Cxi,
It is preferable that the potential Vxi is supplied to the conversion capacitor Cxi in accordance with the pulse signal.
[0040]
In this way, if a potential that changes with time is supplied to one conversion selection line, the number of conversion selection lines can be reduced most. In this case, by inputting a pulse signal to n conversion pulse wirings, a necessary potential can be taken out according to the pulse signal.
[0041]
The D / A converter according to the present invention is
The n kinds of potentials Vxi supplied to the conversion selection wiring preferably form a geometric sequence with a common ratio of 2.
[0042]
By doing so, the charge corresponding to the binary load can be accumulated in the conversion capacitor Cxi. A linear D / A converter can be obtained.
[0043]
The D / A converter according to the present invention is a D / A converter that converts an n-bit (n is a natural number) digital signal Di (i = 1, 2,..., N) into an analog output Vout.
N conversion capacitors Cxi corresponding to each bit of the digital signal Di;
At least one conversion selection wiring to which a plurality of types of potentials Vxi are supplied;
Have
According to the bit digit of the digital signal Di, capacitance values of the potential Vxi and the conversion capacitor Cxi are set so that conversion charges are accumulated in the n conversion capacitors Cxi. The analog output Vout is supplied corresponding to the total charge obtained by summing the converted charges.
[0044]
According to the present invention, a plurality of types of potentials Vxi are used to store the converted charges corresponding to the bit digits of the digital signal Di. Therefore, the value of the potential Vxi can be adjusted by the actual capacitance value of the conversion capacitor Cxi corresponding to each potential Vxi. A D / A converter having linearity can be obtained.
[0056]
The substrate for a liquid crystal panel according to the present invention is one of the substrates in the liquid crystal panel, a driving circuit for driving the liquid crystal panel, a pixel electrode for applying a voltage to the liquid crystal, and a connection to the pixel electrode. A thin film transistor that controls supply of a potential, and the driving circuit includes the above-described D / A converter.
[0057]
According to the present invention, since a D / A converter having linearity is used, it is possible to obtain a liquid crystal panel that does not cause a gradation reversal phenomenon.
[0058]
In the liquid crystal panel substrate according to the present invention, it is preferable that at least one of the conversion capacitor Cxi and the reference capacitor Cs is manufactured on the same substrate by a manufacturing process common to the thin film transistor.
[0059]
In the liquid crystal display device according to the present invention, the liquid crystal panel substrate is used.
[0060]
The liquid crystal display device according to the present invention is
One horizontal scanning period includes a scanning signal selection period and a blanking period between the selection period and the next selection period.
During the blanking period, the total charge is accumulated and the analog output Vout is supplied.
[0061]
The liquid crystal display device according to the present invention is
One horizontal scanning period includes a scanning signal selection period and a blanking period between the selection period and the next selection period.
In the blanking period, the accumulation of the total charge is started,
In the selection period of the next horizontal scanning period, the accumulation of the total charge is completed, and the analog output Vout is supplied.
[0062]
According to the present invention, since the period from the start to the end of the accumulation of the total charge can be lengthened, the charging can be sufficiently performed.
[0063]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0064]
(First embodiment)
FIG. 2 shows a drive circuit for the liquid crystal display device according to the first embodiment. FIG. 3 is an exploded perspective view of the liquid crystal display device. As shown in FIG. 3, the liquid crystal display device has an active matrix type liquid crystal panel 40. In the liquid crystal panel 40, a liquid crystal 46 is sealed between a TFT substrate 43 having a thin film transistor 42 that controls supply of a potential to the pixel electrode 41 and a color filter substrate 45 having a counter electrode 44. Then, polarizing plates 47 and 48 are attached to both surfaces of the liquid crystal panel 40, and a backlight 49 is attached to one polarizing plate 48. The drive circuit 50 is formed on the TFT substrate 43.
[0065]
As shown in FIG. 2, the drive circuit 50 includes a D / A conversion circuit 100 according to the present invention. The D / A conversion circuit 100 can convert a 6-bit digital signal into an analog voltage.
[0066]
The circuits on the TFT substrate 43 are all made of polysilicon formed by a low temperature process.
[0067]
In FIG. 2, digital signals D0 to D5 are inputted to each of six digital wirings 10. The digital signals D0 to D5 are held in the latch circuits A0 to A5 according to the clock CL1 and the inverted clock nCL1. The latch circuits A0 to A5 are the same as those shown in FIG.
[0068]
The shift register 20 includes registers 21, 22,... Corresponding to the number of signal lines of the liquid crystal display device, and each outputs a sampling pulse SP as a clock CL1. The signal level of the sampling pulse SP is inverted by the inverter 12, and an inverted clock nCL1 is generated.
[0069]
Latch circuits A0 to A5 are provided corresponding to the registers 21, 22,. When signals are held in the latch circuits A0 to A5, all signals are transferred to the subsequent latch circuits B0 to B5. For this purpose, the clock CL2 and the inverted clock nCL2 are input to the latch circuits B0 to B5.
[0070]
A latch pulse LP as a clock CL2 is input to the latch pulse wiring 30. The signal level of the latch pulse LP is inverted by the inverter 14, and an inverted clock nCL2 is generated.
[0071]
When the signal is transferred to the latch circuits B0 to B5 in the subsequent stage, D / A conversion processing is performed in accordance with this signal. During this process, the following signals can be sequentially input to the latch circuits A0 to A5 corresponding to the registers 21, 22,.
[0072]
Since the latch circuits B0 to B5 are the same as the latch circuits A0 to A5, detailed description thereof is omitted.
[0073]
The signals held in the latch circuits B0 to B5 are input to the D / A conversion circuit 100. The D / A conversion circuit 100 includes a conversion capacitor unit 101. The conversion capacitor unit 101 outputs a corresponding analog voltage by changing the accumulated charge according to the signals held in the latch circuits B0 to B5.
[0074]
FIG. 1 is a diagram showing details of the D / A conversion circuit 100. The D / A conversion circuit 100 has conversion capacitors Cx0 to Cx5, and the charge stored in each of them changes according to the digital signals D0 to D5, whereby the corresponding analog voltage Vout is output from the output terminal 102a of the output wiring 102. It can be taken out. The conversion capacitors Cx0 to Cx5 form a main part of the conversion capacitor unit 101 shown in FIG.
[0075]
Specifically, each of the conversion capacitors Cx0 to Cx5 is connected between one of the conversion selection wirings 110 to 115 and the common potential wiring 119. The conversion selection wirings 110 to 115 are supplied with the potential Vx0 to Vx5, and the common potential wiring 119 is supplied with the potential Vcom. Therefore, charges are accumulated in the conversion capacitors Cx0 to Cx5 due to the potential difference between one of Vx0 to Vx5 and Vcom.
[0076]
However, the conversion capacitors Cx0 to Cx5 and the conversion selection wirings 110 to 115 can be electrically disconnected by the analog switches Ta10 to Ta15. At this time, when the other analog switches Tb10 to Tb15 are turned on, both electrode plates of the conversion capacitors Cx0 to Cx5 are connected to the common potential wiring 119 as shown in FIG. And since there is no potential difference, no charge is accumulated.
[0077]
The capacitance values of the conversion capacitors Cx0 to Cx5 are
Cx0 = Cx1 = Cx2 = Cx3 = Cx4 = Cx5
It has become. The potentials Vx0 to Vx5 are based on Vcom.
Vx0: Vx1 :: Vx2: Vx3: Vx4: Vx5 = 1: 2: 4: 8: 16: 32
It has become. That is, a geometric sequence with a common ratio of 2 is formed.
[0078]
The analog switches Ta10 to Ta15 are controlled by the logical product of the signals held in the latch circuits B0 to B5 and the conversion pulse XP input to the conversion pulse wiring 116. Specifically, the analog switches Ta10 to Ta15 are controlled by the outputs from the AND gates 120 to 125.
[0079]
The analog switches Tb10 to Tb15 are controlled by the logical product of the inverted signal of the signal held in the latch circuits B0 to B5 and the conversion pulse XP input to the conversion pulse wiring 116. More specifically, the inverters 130 to 135 invert the signals held in the latch circuits B0 to B5, and the analog switches Tb10 to Tb15 are controlled by the outputs from the AND gates 140 to 145.
[0080]
A reference capacitor Cs is connected between the output wiring 102 and the common potential wiring 119. An analog switch Ts is connected between the output wiring 102 and the conversion reference wiring 118. The conversion reference wiring 118 is supplied with a potential of Vxs. When the analog switch Ts is turned on, charges are accumulated in the reference capacitor Cs due to the potential difference between Vcom and Vxs. The minimum value of the analog output can be increased by the charge accumulated in the reference capacitor Cs. A bias voltage can be applied when the D / A conversion circuit 100 is applied to a liquid crystal display device.
[0081]
The reference capacitor Cs is connected in series with each of the conversion capacitors Cx0 to Cx5 via the analog switches Tc10 to Tc15. The analog switches Tc10 to Tc15 are controlled by a coupling pulse CP input to the coupling pulse wiring 117.
[0082]
The D / A conversion circuit 100 is configured as described above, and the D / A conversion method will be described below.
[0083]
It is assumed that the digital signals D0 to D5 are held in the latch circuits B0 to B5.
[0084]
First, one of the analog switches Ta10 to Ta15 or Tb10 to Tb15 is turned on by the conversion pulse XP input to the conversion pulse wiring 116. Specifically, when the digital signals D0 to D5 are "H", the analog switches Ta10 to Ta15 are turned on. Charges are accumulated in the conversion capacitors Cx0 to Cx5 due to the potential difference between the potentials Vx0 to Vx5 of the conversion selection wirings 110 to 115 and the potential Vcom of the common potential wiring 119. If each charge is Qi,
Qi = Cxi (Vxi-Vcom) (2.1)
It becomes. Note that i = 0,1,2,3,4,5.
[0085]
Alternatively, when the digital signals D0 to D5 are "L", the analog switches Tb10 to Tb15 are turned on. At this time, the conversion capacitors Cx0 to Cx5 have no potential difference between the bipolar plates, and no charge is accumulated.
Qi = 0 (2 ・ 2)
It is. Combining the formulas (2-1) and (2-2),
ΣQi = ΣCxi (Di (Vxi-Vcom)) (2.3)
It becomes. Di is “1” when it is “H” level and “0” when it is “L” level, corresponding to each signal level of the digital signals D0 to D5.
[0086]
Simultaneously with these operations, the analog switch Ts is turned on. Charges are accumulated in the reference capacitor Cs due to the potential difference between the potential Vxs of the conversion reference wiring 118 and the potential Vcom of the common potential wiring 119. If the charge at this time is Qs,
Qs = Cs (Vxs-Vcom) (2.4)
It becomes.
[0087]
Next, the signal input to the conversion pulse wiring 116 becomes “L”, and the analog switches Ta10 to Ta15, Tb10 to Tb15, and Ts are turned off. Subsequently, the coupling pulse CP is input to the coupling pulse wiring 117, and the analog switches Tc10 to Tc15 are turned on.
[0088]
Then, each of the conversion capacitors Cx0 to Cx5 and the reference capacitor Cs are connected in series. At this time, if the total charge accumulated in the conversion capacitors Cx0 to Cx5 is ΣQi ′ and the charge accumulated in the reference capacitor Cs is Qs ′,
ΣQi '= ΣCxi (Vout-Vcom) (2.5)
Qs' = Cs (Vout-Vcom) (2.6)
It becomes. Note that i = 0,1,2,3,4,5, and Vout is the potential of the output wiring 102.
[0089]
ΣQi + Qs = ΣQi '+ Qs'
Therefore, from equations (2 ・ 3) to (2 ・ 6),
ΣCxi (Di (Vxi−Vcom)) + Cs (Vxs−Vcom)
= ΣCxi (Vout−Vcom) + Cs (Vout−Vcom)
And transform this,

It becomes. Note that i = 0,1,2,3,4,5. Di is set to “1” when it is “H” level and “0” when it is “L” level corresponding to each signal level of the digital signals D0 to D5.
[0090]
The potential thus obtained is taken out from the output terminal 102a as an analog output.
[0091]
FIG. 4 is a diagram showing the D / A converter characteristics of the D / A conversion circuit 100. In the D / A conversion circuit 100, the conversion capacitors Cxi are all equal to 1.0 pF, and the reference capacitor Cs is 2.0 pF. The potentials Vx0, Vx1, Vx2, Vx3, Vx4, and Vx5 of the conversion selection wirings 110 to 115 are 0.5, 1.0, 2.0, 4.0, 8.0, and 16.0 V, which is a geometric sequence with a common ratio of 2. The potential Vxs of the conversion reference wiring 118 is 4.0V. Further, the potential Vcom of the common potential wiring 119 is a GND potential.
[0092]
As shown in FIG. 4, it can be seen that there is perfect linearity between the 6-bit digital input value and the analog output. This is because the value of the denominator (ΣCxi + Cs) in the equation (2 · 7) for deriving the analog output Vout is a constant regardless of the digital input value. Since the digital input value and the analog output have a directly proportional relationship, the D / A conversion circuit 100 has a linear characteristic. In FIG. 4, even when the digital input value is 0, the analog output is 1V. This is because charges are accumulated in the reference capacitor Cs even if the digital input value is zero.
[0093]
Next, FIG. 5 is a diagram showing a method of driving a liquid crystal display device using the D / A conversion circuit 100. In other words, it is a diagram for explaining the operation of the drive circuit for the liquid crystal display device shown in FIG.
[0094]
As shown in FIG. 5, one horizontal scanning period Th for driving the liquid crystal includes a scanning signal selection period Ts and a blanking period Tb between the selection period Ts and the next selection period Ts.
[0095]
In the selection period Ts, the digital signals D0 to D5 are taken into the latch circuits A0 to A5 by the sampling pulses SP0 to SPn during the time t0 to t1.
[0096]
The blanking period Tb is a period before shifting to the next selection period Ts, and various processes including D / A conversion are performed using this period.
[0097]
In the blanking period Tb, at time t2, the coupling pulse CP becomes “L”, the analog switches Tc10 to Tc15 are turned off, and the conversion capacitors Cx0 to Cx5 and the reference capacitor Cs are electrically disconnected. Next, at time t3, signals latched in the latch circuits A0 to A5 are transferred to the latch circuits B0 to B5 by the latch pulse LP.
[0098]
At time t4, the analog switches Ta10 to Ta15 and Tb10 to Tb15 are controlled by the signals of the latch circuits B0 to B5 and the conversion pulse XP. Of the conversion capacitors Cx0 to Cx5, charges corresponding to the “H” digital signal are accumulated, and charges corresponding to the “L” digital signal are not accumulated. At the same time, charges are accumulated in the reference capacitor Cs. In order to accumulate charges, the conversion pulse XP is in the “H” state for a long time compared to other pulses.
[0099]
At time t5, the conversion pulse XP is in the “L” state, and the charge accumulation is completed.
[0100]
At time t6, the conversion capacitors Cx0 to Cx5 and the reference capacitor Cs are combined by the combined pulse CP, and a predetermined output voltage can be taken out from the output terminal 102a.
[0101]
Next, FIGS. 6A and 6B are diagrams for explaining the inversion driving operation of the liquid crystal display device.
[0102]
In the liquid crystal driving device, inversion driving is performed for reasons such as preventing quality deterioration of the liquid crystal. Therefore, inversion drive is also performed in the drive circuit 50 (FIGS. 2 and 3) including the D / A conversion circuit 100 as shown in FIGS. 6 (A) and 6 (B). Specifically, this inversion drive is performed for each horizontal scanning line and for each screen, and is not inverted for each signal line.
[0103]
FIG. 6A shows a method of supplying the potentials Vx0, Vx1, Vx2, Vx3, Vx4, Vx5 of the conversion selection wirings 110 to 115 and the potential Vxs of the conversion reference wiring 118. FIG. 6B shows specific numerical values of the respective potentials.
[0104]
In the D / A conversion circuit 100, the conversion capacitors Cxi are all equal to 1.0 pF, and the reference capacitance Cs is 2.0 pF. Further, the potential Vcom of the common potential wiring 119 is a GND potential.
[0105]
Then, inversion driving is performed as shown in FIG. The details of the operation are well known and will not be described.
[0106]
(Adjustment method of the first embodiment)
The D / A conversion circuit 100 can perform D / A conversion by making the conversion capacitors Cx0 to Cx5 all have the same capacitance value and applying a binary weighted voltage to each. Here, while it is difficult to change the capacitance value of the capacitor after manufacturing, the voltage can be easily changed. Therefore, a voltage adjustment method when the capacitance values of the conversion capacitors Cx0 to Cx5 are different from the above-described design values will be described below.
[0107]
First, FIG. 7A shows an example in which the capacitance value of the conversion capacitor Cxi ′ is different from the design value Cxi (1.0 pF), but the average of the capacitance values is equal to the design value. In this example, the conversion selection wirings 110 to 115 are supplied with the potential Vxi ′ by adjusting the designed potential Vxi0. Note that i = 0,1,2,3,4,5. For more information,
Vxi ′ = (Cxi / Cxi ′) × Vxi0
It has been adjusted to be. For example, in the least significant bit:
Since Cx0 = 1.0pF, Cx0 ′ = 0.9pF, and Vx0 = 0.5V,
Vx0 '= (1.0 / 0.9) × 0.5 = 0.5556 V
It becomes.
[0108]
Next, FIG. 7B shows an example in which the capacitance value of the conversion capacitor Cxi ″ is different from the design value, and the average of the capacitance values is different from the design value.
Vxi ″
= (Cxi0 / Cxi ″) × (ΣCxi ″ + Cs) / (ΣCxi0 + Cs) × Vxi
The potential Vxi ″ is adjusted so that, for example, in the least significant bit,
Since Cxi = 1.0pF, Cxi ″ = 0.9pF, ΣCxi ″ + Cs = 7.4pF, ΣCxi + Cs = 8.0pF, Vx0 = 0.5V,
Vxi ″ = (1.0 / 0.9) × (7.4 / 8.0) × 0.5 = 0.5139 V
It becomes.
[0109]
7A and 7B, the potentials Vxi ′ and Vxi ″ of the conversion selection wirings 110 to 115 are completely adjusted, and the D / A converter characteristics are as shown in FIG. Exactly the same can be obtained, and even if the capacitance values of the conversion capacitors Cx0 to Cx5 are not designed values, an analog output voltage as designed can be obtained.
[0110]
Therefore, according to the driving circuit 50 for a liquid crystal display device using the D / A conversion circuit 100, image quality problems such as gradation inversion due to the inversion phenomenon do not occur at all.
[0111]
In this embodiment, the case where the conversion capacitors Cx0 to Cx5 are different from the design value is considered. However, even when the reference capacitance Cs is different from the design value, the predetermined liquid crystal application is performed by adjusting the potentials Vx0 to Vx5 and Vxs. A voltage can be obtained. In the above adjustment method, the potential is adjusted by calculation. However, adjusting the potential by trial and error according to the idea described here is also effective.
[0112]
In this example, the calculation is performed assuming that the actual values of the conversion capacitors Cx0 to Cx5 are known in advance. However, in many cases, the actual values are unknown. Even in such a case, it is possible to obtain ideal D / A converter characteristics by adjusting the potentials Vx0 to Vx5.
[0113]
Note that the D / A conversion circuit 100 is applied to a passive matrix display device, is formed on a printed substrate other than a glass substrate, or is amorphous silicon, high-temperature polysilicon, crystalline silicon, or gallium arsenide. Even if it forms with what kind of semiconductors, etc., it is effective.
[0114]
The inversion driving of the driving circuit 50 is related to whether the polarity is inverted for each screen or for each of a plurality of screens, for each horizontal scanning line or for a plurality of horizontal scanning lines, for each signal line or for each signal line. There is an effect.
[0115]
In the present embodiment, one electrode plate of the conversion capacitors Cx0 to Cx5 is connected to the common potential wiring 119, but may be connected to another potential wiring. In this embodiment, the potential Vcom is applied to the bipolar plates of the conversion capacitors Cx0 to Cx5 when the digital signals D0 to D5 are "L" (off). Instead, other potentials are used. May be applied.
[0116]
FIG. 8 shows a D / A conversion circuit 200 as a modification in consideration of these. In the D / A conversion circuit 200, one electrode plate of the conversion capacitors Cx 0 to Cx 5 is connected to the conversion reference wiring 118 instead of the common potential wiring 119. The other electrode plates of the conversion capacitors Cx0 to Cx5 are connected to the conversion reference wiring 118 via the analog switches Tb10 to Tb15. The rest is the same as the D / A conversion circuit 100 shown in FIG.
[0117]
According to the D / A conversion circuit 200, when the digital signals D0 to D5 are "L" (off), the potential Vxs is supplied to the conversion capacitors Cx0 to Cx5, but there is no potential difference between these bipolar plates. , No charge is accumulated. When the digital signals D0 to D5 are "H" (ON), charges are accumulated in the conversion capacitors Cx0 to Cx5 due to the potential difference between the potentials Vx0 to Vx5 and the potential Vxs. Since other operations are the same as those of the D / A conversion circuit 100, description thereof is omitted.
[0118]
(Second Embodiment)
Next, FIG. 9 shows a D / A conversion circuit 300 according to the second embodiment of the present invention. The D / A conversion circuit 300 is used in place of the D / A conversion circuit 100 in the driving circuit 50 for a liquid crystal display device shown in FIG. The driving method of the liquid crystal display device at that time is the same as that of the first embodiment. Further, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0119]
In the D / A conversion circuit 100 shown in FIG. 1, conversion selection wirings 110 to 115 are provided in order to supply the potentials Vx0 to Vx5 forming a geometric sequence with a common ratio of 2. In contrast, in the D / A conversion circuit 300 illustrated in FIG. 9, resistors Rx0 to Rx5 are connected in series between the high potential wiring 310 and the low potential wiring 312.
[0120]
The high potential wiring 310 is applied with a high potential VxH, and the low potential wiring 312 is applied with a low potential VxL. The resistance values of the resistors Rx0 to Rx5 are arranged in a geometric sequence with a common ratio of 2, and the highest potential Vx5 of the potentials Vx0 to Vx5 in the first embodiment is equal to the potential VxH on the high potential side. Thus, the lowest potential Vx0 in the first embodiment is set to be equal to the lower potential VxL. Thereby, also in this embodiment, potentials Vx0 to Vx5 equal to those in the first embodiment can be extracted as a divided voltage from between the resistors Rx0 to Rx5.
[0121]
Also in the present embodiment, linearity between the digital input and the analog output value can be realized as in the first embodiment.
[0122]
In this embodiment, one set of the high potential wiring 310 and the low potential wiring 312 is provided. However, two or more sets of the high potential wiring and the low potential wiring are provided, and different potentials are applied to each of them. The first embodiment and the second embodiment can be used in combination by connecting a plurality of resistors in series.
[0123]
(Third embodiment)
Next, FIG. 10 shows a D / A conversion circuit 400 according to a third embodiment of the present invention. The D / A conversion circuit 400 is also used in place of the D / A conversion circuit 100 in the driving circuit 50 for the liquid crystal display device shown in FIG. The driving method of the liquid crystal display device at that time is the same as that of the first embodiment. Further, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0124]
The D / A conversion circuit 100 shown in FIG. 1 is provided with one conversion pulse wiring 116 and a plurality of conversion selection wirings 110 to 115 in order to supply a plurality of potentials Vx0 to Vx5. On the other hand, the D / A conversion circuit 400 shown in FIG. 10 includes a plurality of conversion pulse wirings 410 to 415 and one conversion selection wiring 420 in order to supply a plurality of potentials.
[0125]
The circuit of FIG. 10 is outlined. The signals of the latch circuits B0 to B5 in the subsequent stage are inputted to the analog switches Ta10 to Ta15 by taking a logical product with the conversion pulses XP0 to XP5 of the corresponding conversion pulse wirings 410 to 415. The analog switches Ta10 to Ta15 are connected so as to control the output of the conversion selection wiring 420 for the conversion capacitors Cx0 to Cx5.
[0126]
At the same time, the signals of the latch circuits B0 to B5 are negated and logically ANDed with the corresponding conversion pulses XP0 to XP5 and input to the analog switches Tb10 to Tb15.
[0127]
FIG. 11 shows a driving method of a liquid crystal display device to which the D / A conversion circuit 400 is applied. The digital inputs D0 to D5 and the sampling pulse SR are the same as those in the first embodiment. The potential Vx is applied to the conversion selection wiring 420 and changes with time in the blanking period. The conversion pulses XP0 to XP5 are applied to a plurality of conversion pulse wirings 410 to 415.
[0128]
The operation of the drive circuit of the liquid crystal display device of this embodiment will be described with reference to FIGS. As shown in these figures, since the conversion pulses XP0 to XP5 are inputted in synchronization with the change of the potential Vx, predetermined potentials Vx0 to Vx5 are selected. If the analog switches Ta10 to Ta15 are turned on in accordance with the digital inputs D0 to D5, the selected potentials Vx0 to Vx5 are supplied to the conversion capacitors Cx0 to Cx5 to accumulate electric charges. Alternatively, if the analog switches Tb10 to Tb15 are turned on, the potential Vcom is supplied to the conversion capacitors Cx0 to Cx5, and no charge is accumulated. Thus, a predetermined analog output Vout can be taken out.
[0129]
Also in this embodiment, the same effect as that of the first embodiment can be realized.
[0130]
As a modification, a conversion selection potential that changes with time may be applied to each of the plurality of conversion selection wirings.
[0131]
(Fourth embodiment)
Next, FIG. 12 shows a D / A conversion circuit 500 according to a fourth embodiment of the present invention. The D / A conversion circuit 500 is also used in place of the D / A conversion circuit 100 in the driving circuit 50 for the liquid crystal display device shown in FIG. The driving method of the liquid crystal display device at that time is the same as that of the first embodiment. Further, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0132]
In the fourth embodiment, a predetermined analog output voltage is obtained by selecting a plurality of potentials and changing the capacitance values of the conversion capacitors. In FIG. 12, three conversion selection wirings 510 to 512 are formed. The capacitance values of the conversion capacitors Cx50 to Cx55 satisfy the following expression.
[0133]
Cx50: Cx51: Cx52: Cx53: Cx54: Cx55 = 1: 2: 1: 2: 1: 2
FIG. 13 shows capacitance values of the conversion capacitors Cx50 to Cx55 and the reference capacitor Cs according to the fourth embodiment, and values of the potentials Vx0 to Vx2 and the potential Vxs. The conversion capacitors Cx50 and Cx51, Cx52 and Cx53, and Cx54 and Cx55 are supplied with the potential from the potential Vx0, the potential Vx1, or the Vx2, respectively.
[0134]
In this embodiment, the same effect as that of the first embodiment can be realized.
[0135]
(Fifth embodiment)
Next, FIG. 14 shows a driving method of the liquid crystal display device according to the fifth embodiment. In the present embodiment, the driving circuit and the D / A conversion circuit of the liquid crystal display device are the same as those in the first embodiment or the second embodiment.
[0136]
In the driving method shown in FIG. 5, the blanking period starts after the input of the digital inputs D0 to D5 and the sampling pulse SR is completed in the selection period Ts. Then, the latch pulse LP changes from the off potential to the on potential, and again becomes the off potential. Next, the conversion pulse XP changes from the off potential to the on potential, and then changes to the off potential again. Next, the coupling pulse CP changes from the off potential to the on potential, and again becomes the off potential.
[0137]
Here, the following conditions must be satisfied. The input of the latch pulse LP is after the input of the digital inputs D0 to D5 and the sampling pulse SR, the input of the conversion pulse XP is after the input of the latch pulse LP, and the input of the combined pulse CP is the input of the conversion pulse XP It is after the input is completed.
[0138]
As long as this condition is satisfied, the conversion pulse XP and the coupling pulse CP may be turned on / off in either the selection period Ts or the blanking period Tb. Further, the input periods of the latch pulse LP and the coupling pulse CP may overlap.
[0139]
Therefore, in order to fully charge the conversion capacitors Cx0 to Cx5 and the reference capacitor Cs and supply the charges held in the conversion capacitors Cx0 to Cx5 to the reference capacitor Cs, the ON period of the conversion pulse XP is set. It is preferable to optimize the length and the length of the ON period of the combined pulse CP.
[0140]
In particular, if the blanking period Tb is shorter than the selection period Ts and the end of the ON potential of the conversion pulse XP is performed during the blanking period Tb, the conversion capacitors Cx0 to Cx5 are charged and the reference capacitor Cs is charged. May be insufficient.
[0141]
Therefore, in the present embodiment, the end of the ON potential of the conversion pulse XP is performed during the selection period Ts, so that these charges can be sufficiently performed.
[0142]
In this embodiment, the same effect as that of the first embodiment can be realized.
[0143]
This embodiment is applicable not only when the potentials Vx0 to Vx5 are given by a plurality of conversion selection wirings or by dividing resistors, but also when a time-varying potential is applied to one conversion selection wiring. can do.
[0144]
(Sixth embodiment)
Next, FIG. 15 shows a D / A conversion circuit 600 according to a sixth embodiment of the present invention. This D / A conversion circuit 600 is also used in place of the D / A conversion circuit 100 in the driving circuit 50 for the liquid crystal display device shown in FIG. The driving method of the liquid crystal display device at that time is the same as that of the first embodiment. Further, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0145]
A thin film transistor, particularly a polysilicon thin film transistor formed by a low temperature process, has a large leakage current when turned off. Therefore, in this embodiment, a pair of analog switches Ta10 to Ta15 made of thin film transistors are connected in series. According to this configuration, leakage current at the time of OFF can be reduced, and sudden deterioration of the OFF characteristic of one thin film transistor can be compensated by the other thin film transistor.
[0146]
In this embodiment, the same effect as that of the first embodiment can be realized.
[0147]
As a modification, two thin film transistors are connected in series to all the elements such as the analog switches Tb10 to Tb15, Tc10 to Tc15 and Ts, or the shift register 20 and the latch circuits A0 to A5 and B0 to B5 shown in FIG. A configuration for connecting to the terminal can be considered. A configuration in which three or more thin film transistors are connected in series is also conceivable.
[0148]
(Seventh embodiment)
Next, FIG. 16 shows a D / A conversion circuit 700 according to a seventh embodiment of the present invention. The D / A conversion circuit 700 is also used in place of the D / A conversion circuit 100 in the driving circuit 50 for the liquid crystal display device shown in FIG. The driving method of the liquid crystal display device at that time is the same as that of the first embodiment. Further, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0149]
In addition to a high threshold voltage, a MOS transistor formed of a thin film, particularly a polysilicon thin film formed by a low temperature process, has a small on-state charging current. Since a positive potential is applied to the gate of the n-channel transistor when it is turned on, if the source or drain potential is high, the difference between the potential and the gate potential is reduced, and the operation speed is reduced. In addition, since a negative potential is applied to the gate when the p-channel transistor is turned on, if the source or drain potential is low, the difference between the potential and the gate potential becomes small, and the operation speed becomes slow.
[0150]
Therefore, in the seventh embodiment, analog switches Tb70 to Tb75 having a CMOS structure in which an n-channel transistor and a p-channel transistor are connected in parallel are employed. Good charge characteristics can be obtained regardless of the source or drain potential.
[0151]
In this embodiment, the same effect as that of the first embodiment can be realized.
[0152]
The CMOS structure can be applied to all the elements such as the analog switches Ta10 to Ta15, Tc10 to Tc15 and Ts, or the shift register 20 and the latch circuits A0 to A5 and B0 to B5 shown in FIG. .
[0153]
(Eighth embodiment)
Next, FIGS. 17A and 17B show a driving method of the liquid crystal display device according to the eighth embodiment. In the present embodiment, the driving circuit and the D / A conversion circuit of the liquid crystal display device are the same as those in the first embodiment.
[0154]
FIG. 17A shows how to apply the potentials Vx0 to Vx5, Vxs, and Vcom, and FIG. 17B shows these potentials. The conversion capacitors Cx0 to Cx5 are all equally 1.0 pF, and the reference capacitor Cs is 2.0 pF.
[0155]
In the present embodiment, driving is performed such that the potentials Vx0 to Vx5 and the potential Vxs are inverted for each screen and for each horizontal scanning line but not for each signal line. The polarity of the potential Vcom is inverted in synchronization with the potentials Vx0 to Vx5 and Vxs. However, the reverse polarity is reversed.
[0156]
The feature of this embodiment is that the potential Vcom is inverted in polarity. This potential Vcom is applied to one of the electrodes that sandwich the liquid crystal. The analog output Vout from the output terminal 102a (see FIG. 1) is applied to the other electrode. The potential difference between the two electrodes can be formed by reversing the polarity of the potential Vcom. This potential difference becomes part of the voltage required for driving the liquid crystal. Therefore, when a bias voltage is required, the analog output Vout when the digital input value is 0 may be small. That is, the voltage applied to the reference capacitor Cs can be reduced.
[0157]
In this embodiment, the one-side amplitude of the potential Vcom is 1V, and the potential Vxs is 0V.
[0158]
When the amplitude of the potential Vcom is further increased, in order to obtain the same D / A converter characteristics, it is necessary to drive the potential Vxs in an inverted manner. The inversion of the potential Vxs is opposite in polarity to the potentials Vx0 to Vx5. Further, by adjusting the amplitudes of the potentials Vcom and Vxs, it is possible to reduce the voltage value of the power supply voltage and the voltage level.
[0159]
Also in this embodiment, the same effect as that of the first embodiment can be realized.
[0160]
(Ninth embodiment)
Next, FIG. 18 shows a driving method of the liquid crystal display device according to the ninth embodiment. In the present embodiment, the driving circuit and the D / A conversion circuit of the liquid crystal display device are the same as those in the first embodiment.
[0161]
FIG. 18A shows how to apply the potentials Vx0 to Vx5, Vxs, and Vcom, and FIG. 18B shows the values of the potentials Vx0 to Vx5, Vxs, and Vcom. In the present embodiment, driving is performed in which the potentials Vx0 to Vx5 and Vxs are inverted for each screen and for each horizontal scanning line but not for each signal line. The potential Vcom is a constant potential.
[0162]
A feature of the present embodiment is that the potentials Vx0 to Vx5 and the potential Vxs are inverted in phase with opposite phases. Therefore, in the D / A conversion circuit 100 shown in FIG. 1, the charges stored in the reference capacitor Cs and the charges stored in the conversion capacitors Cx0 to Cx5 have opposite polarities. When the charge of the reference capacitor Cs and the charges of the conversion capacitors Cx0 to Cx5 are combined, the total charge is reduced, and so-called subtraction type D / A conversion different from the conventional addition type can be performed. .
[0163]
FIG. 19 shows the D / A converter characteristics according to this embodiment. Since it is a subtraction type, the slope is opposite to that shown in FIG. 4, but the analog output is 1 V to 5 V and complete linearity is realized over all digital input values (0 to 63). I understand.
[0164]
In this embodiment, the same effect as that of the first embodiment can be realized.
[0165]
In the above embodiment, the amplitude of the potentials Vcom and Vxs can be adjusted to reduce the voltage value of the power supply voltage and the number of voltage levels. An example thereof will be described with reference to FIGS. 20 (A) and 20 (B).
[0166]
FIG. 20A shows how to apply the potentials Vx0 to Vx5, Vxs, and Vcom in the modification of the ninth embodiment, and FIG. 20B shows the values of the potentials Vx0 to Vx5, Vxs, and Vcom. As shown in these figures, the potential Vcom is also inverted in polarity in synchronization with the potentials Vx0 to Vx5 and the conversion reference potential Vxs. The polarity reversal of the potential Vcom is in the opposite phase to the polarity reversal of the potential Vxs.
[0167]
As described above with respect to the eighth embodiment, the potential Vcom is applied to one of the electrodes sandwiching the liquid crystal, and a part of the voltage necessary for driving is borne. Therefore, also in this modified example, since the potential Vcom whose polarity is inverted is applied to one electrode, the potential Vxs applied to the other electrode may be small. Specifically, the amplitude of the potential Vcom is 3V, and the amplitude of the potential Vxs is 8V with reverse polarity. This value is extremely small compared to the value shown in FIG. 18, and is effective in reducing power consumption.
[0168]
The liquid crystal display device according to the present invention includes not only a direct view type but also a projection type.
[0169]
The D / A conversion circuit according to the present invention can also be applied to a known liquid crystal optical device such as an optical shutter.
[0170]
[Brief description of the drawings]
FIG. 1 is a diagram showing a D / A conversion circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a drive circuit for a liquid crystal display device according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a liquid crystal display device according to the first embodiment of the present invention.
FIG. 4 is a diagram showing D / A converter characteristics according to the first embodiment of the present invention.
FIG. 5 is a diagram showing a driving method of the liquid crystal display device according to the first embodiment of the present invention.
6A and 6B are diagrams illustrating an inversion driving operation of the liquid crystal display device. FIG.
FIGS. 7A and 7B are diagrams illustrating a method of adjusting a conversion capacitor and a potential in the first embodiment.
FIG. 8 is a diagram showing a modification of the first embodiment of the present invention.
FIG. 9 is a diagram showing a D / A conversion circuit according to a second embodiment of the present invention.
FIG. 10 is a diagram showing a D / A conversion circuit according to a third embodiment of the present invention.
11 is a diagram showing a driving method of a liquid crystal display device to which the D / A conversion circuit shown in FIG. 10 is applied.
FIG. 12 is a diagram showing a D / A conversion circuit according to a fourth embodiment of the present invention.
FIG. 13 is a diagram illustrating a capacitance value and a potential of a conversion capacitor according to a fourth embodiment.
FIG. 14 is a diagram showing a driving method of a liquid crystal display device according to a fifth embodiment of the present invention.
FIG. 15 is a diagram showing a D / A conversion circuit according to a sixth embodiment of the present invention.
FIG. 16 is a diagram showing a D / A conversion circuit according to a seventh embodiment of the present invention.
FIGS. 17A and 17B are diagrams illustrating a driving method of a liquid crystal display device according to an eighth embodiment of the present invention.
18A and 18B are diagrams showing a method for driving a liquid crystal display device according to the ninth embodiment of the present invention.
FIG. 19 shows D / A converter characteristics of the ninth embodiment.
FIGS. 20A and 20B are diagrams showing a modification of the driving method of the ninth embodiment.
FIG. 21 is a diagram showing a D / A conversion circuit using a conventional binary load capacitor.
FIG. 22 is a diagram illustrating an example of D / A converter characteristics of a conventional D / A converter.
[Explanation of symbols]
110-115, 420 Conversion selection wiring
102 Output wiring
118 Conversion reference wiring (reference wiring)
119 Common wiring (reference wiring)
310 High-potential wiring
312 Low potential wiring
410 to 415 Conversion pulse wiring
Cx0 to Cx5 conversion capacity
D0 to D5 Digital signal
Rx0 ~ Rx4 resistance
Ta10 to Ta15, Tb10 to Tb15, Tc10 to Tc15, Ts Analog switch (switch)

Claims (13)

In a D / A converter for converting an n-bit (n is a natural number) digital signal Di (i = 1, 2,..., n) into an analog output Vout,
N conversion capacitors Cxi corresponding to each bit of the digital signal Di;
At least one conversion selection wiring to which n kinds of potentials Vxi corresponding to each bit of the digital signal Di are supplied;
Output wiring for taking out the analog output Vout;
A first reference wiring having a potential Vs1 connected to one electrode plate of the conversion capacitor Cxi;
A second reference wiring having a potential Vs2;
A reference capacitor Cs formed in the output wiring and storing a reference charge by a potential difference between the potentials Vs1 and Vs2 in the first and second reference wirings;
Have
The other electrode plate of the conversion capacitor Cxi corresponding to the ON digital signal Di is connected to the conversion selection wiring, and the conversion charge is accumulated in the conversion capacitor Cxi by the potential difference between the corresponding potentials Vxi and Vs1,
The other electrode plate of the conversion capacitor Cxi corresponding to the off digital signal Di is connected to the first reference wiring,
After the conversion charge is accumulated, the other electrode plate is electrically disconnected from the conversion selection wiring and the predetermined wiring, and is connected to the output wiring so that the conversion charge and the reference charge are Supply analog output Vout corresponding to the total electric charge,
The analog output Vout is
Vout = (ΣCxi (DiVxi + Vs1 (1-Di)) + CsVs2) / (ΣCxi + Cs)
[Di is 1 when the digital signal Di is on and 0 when it is off. ]
A D / A converter represented by The D / A converter according to claim 1, wherein
A first switch connected between the other electrode plate of the conversion capacitor Cxi and the conversion selection wiring;
A second switch connected between the other electrode plate of the conversion capacitor Cxi and the predetermined wiring;
A third switch connected between the other electrode plate of the conversion capacitor Cxi and the output wiring;
A D / A converter having: The D / A converter according to claim 1, wherein
A first switch connected between the other electrode plate of the conversion capacitor Cxi and the conversion selection wiring;
A second switch connected between the other electrode plate of the conversion capacitor Cxi and the first reference wiring;
A third switch connected between the other electrode plate of the conversion capacitor Cxi and the output wiring;
A fourth switch for controlling application of a voltage from the first and second reference wires to the reference capacitor Cs;
A D / A converter having: The D / A converter in any one of Claims 1-3 WHEREIN:
A D / A converter in which n types of potential Vxi are supplied by n conversion selection wirings. The D / A converter in any one of Claims 1-3 WHEREIN:
A high potential wiring, a low potential wiring, n-1 resistors connected in series between the high potential wiring and the low potential wiring;
Have
The conversion selection wiring is directly connected to the wiring between the high potential wiring and the resistor directly connected to the high potential wiring, the wiring connecting adjacent resistors, and the low potential wiring and the low potential wiring. A D / A converter configured by wiring between the resistors.   The D / A converter in any one of Claims 1-3 WHEREIN:
  There is one conversion selection wiring, and the potential supplied to this conversion selection wiring changes with time so that n kinds of potentials V xi D / A converter to which is supplied. The D / A converter according to claim 6 , wherein
N conversion pulse wirings corresponding to the n conversion capacitors Cxi,
A pulse signal is applied to each conversion pulse wiring when the potential that changes in the conversion selection wiring becomes the potential Vxi supplied to the corresponding conversion capacitor Cxi,
A D / A converter in which a potential Vxi is supplied to the conversion capacitor Cxi in accordance with the pulse signal. In D / A converter as claimed in any one of claims 7,
The n types of potentials Vxi supplied to the conversion selection wiring are D / A converters that form a geometric sequence with a common ratio of 2. One of the substrates in the liquid crystal panel,
A driving circuit for driving the liquid crystal panel, a pixel electrode for applying a voltage to the liquid crystal, and a thin film transistor for controlling supply of a potential to the pixel electrode,
The said drive circuit is a liquid crystal panel board | substrate containing the D / A converter in any one of Claims 1-8. One of the substrates in the liquid crystal panel,
A driving circuit for driving the liquid crystal panel, a pixel electrode for applying a voltage to the liquid crystal, and a thin film transistor for controlling supply of a potential to the pixel electrode,
The drive circuit includes a D / A converter according to any one of claims 1 to 7,
At least one of the conversion capacitor Cxi and the reference capacitor Cs is a liquid crystal panel substrate manufactured on the same substrate by a manufacturing process common to the thin film transistor. A liquid crystal display device in which the liquid crystal panel substrate according to claim 9 or 10 is used. The liquid crystal display device according to claim 11 .
One horizontal scanning period includes a scanning signal selection period and a blanking period between the selection period and the next selection period.
A liquid crystal display device in which accumulation of the total charge and supply of an analog output Vout are performed in the blanking period. The liquid crystal display device according to claim 11 .
One horizontal scanning period includes a scanning signal selection period and a blanking period between the selection period and the next selection period.
In the blanking period, the accumulation of the total charge is started,
A liquid crystal display device in which the accumulation of the total charge is completed and the analog output Vout is supplied in the selection period of the next horizontal scanning period.

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