JPH05281920A - Decoder circuit and display device - Google Patents
Decoder circuit and display deviceInfo
- Publication number
- JPH05281920A JPH05281920A JP4079945A JP7994592A JPH05281920A JP H05281920 A JPH05281920 A JP H05281920A JP 4079945 A JP4079945 A JP 4079945A JP 7994592 A JP7994592 A JP 7994592A JP H05281920 A JPH05281920 A JP H05281920A
- Authority
- JP
- Japan
- Prior art keywords
- data
- display device
- capacitors
- decoder
- switches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Transforming Electric Information Into Light Information (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Analogue/Digital Conversion (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＮ個の２値データから２
N 個のデータに変換するデコーダ回路に関する。特に、
液晶表示装置のデータドライバの構成に関する。BACKGROUND OF THE INVENTION The present invention uses 2 binary data from N binary data.
The present invention relates to a decoder circuit that converts N pieces of data. In particular,
The present invention relates to the configuration of a data driver of a liquid crystal display device.
【０００２】[0002]
【従来の技術】従来の、Ｎ個の２値データから２N 個の
データに変換するデコーダ回路の応用例としては、「１
９９１ インターナショナル・ディスプレイ・リサーチ
・コンファレンス、ｐ．１１１−１１４、岡田他」があ
る。図２は３入力から８出力に変換する代表的なデコー
ダ回路の例である。本図においてＤＡＴＡ１−はＤＡＴ
Ａ１＋の反転データであり、ＤＡＴＡ２、ＤＡＴＡ３も
同様である。３つの２値入力データの組合せは８種類あ
るから、デコーダ部の８つのＡＮＤゲートのうちどれか
ひとつが選択レベルとなり、バッファ部のスイッチをＯ
Ｎさせる。従って出力端子ＶＯＵＴには、８つの電圧Ｖ
１〜Ｖ８のいずれかが出力されることとなる。2. Description of the Related Art As a conventional application example of a decoder circuit for converting N binary data into 2 N data, "1.
991 International Display Research Conference, p. 111-114, Okada and others ”. FIG. 2 shows an example of a typical decoder circuit for converting 3 inputs to 8 outputs. In the figure, DATA1- is DAT
This is the inverted data of A1 +, and the same applies to DATA2 and DATA3. Since there are eight kinds of combinations of three binary input data, one of the eight AND gates in the decoder section becomes the selection level, and the switch in the buffer section is turned on.
Let N. Therefore, the output terminal VOUT has eight voltages V
Any one of 1 to V8 will be output.
【０００３】[0003]
【発明が解決しようとする課題】しかし、前述の従来技
術には以下に述べるような課題がある。However, the above-mentioned prior art has the following problems.
【０００４】一般に、フルカラー液晶表示装置のデータ
ドライバのように、デジタル入力で画像信号を構成する
場合には、７ビットや８ビットといった多階調の信号が
必要になる。ところが、図２の方法で８ビット入力のデ
コーダを構成すると、ＡＮＤゲートの数だけでも２５６
個必要となる。これでは素子数と回路面積が激増し、極
めて高価な回路になってしまうほか、表示装置全体の大
きさや重量も増大してしまう。Generally, in the case of forming an image signal by digital input like a data driver of a full color liquid crystal display device, a multi-gradation signal of 7 bits or 8 bits is required. However, if an 8-bit input decoder is constructed by the method of FIG. 2, the number of AND gates is 256.
You need one. This leads to a drastic increase in the number of elements and the circuit area, resulting in an extremely expensive circuit, and also in the size and weight of the entire display device.
【０００５】本発明のデコーダ回路はこの様な課題を解
決するものであり、その目的とするところは、入力ビッ
ト数が増加しても回路規模があまり増加しないデコーダ
回路を実現することにある。The decoder circuit of the present invention solves such a problem, and an object thereof is to realize a decoder circuit whose circuit scale does not increase much even if the number of input bits increases.
【０００６】[0006]
【課題を解決するための手段】本発明のデコーダ回路
は、容量比が１、２、４、８．．．２(N-1) となってい
るＮ個の容量とＮ個のスイッチを備え、前記Ｎ個のスイ
ッチのゲートがＮ個の２値データにそれぞれ接続されて
いることを特徴とする。The decoder circuit of the present invention has a capacitance ratio of 1, 2, 4, 8. ． ． It is characterized in that it has N capacitors of 2 (N-1) and N switches, and the gates of the N switches are connected to N binary data, respectively.
【０００７】[0007]
【実施例】本実施例を以下図面に基づいて説明する。図
１は本発明のデコーダ回路の回路図の例である。本図に
おいて容量Ｃ１、Ｃ２、Ｃ３の大きさをそれぞれＣ１、
Ｃ２、Ｃ３とし、出力端子ＯＵＴに接続される負荷の容
量をＣ０とすると、このデコーダ回路は３ビットの入力
信号を０ボルトからＶＤＤ・（Ｃ１＋Ｃ２＋Ｃ３）／
（Ｃ０＋Ｃ１＋Ｃ２＋Ｃ３）ボルトまでの間の電圧に変
換することができる。もし、Ｃ１＝４Ｃｚ、Ｃ２＝２Ｃ
ｚ、Ｃ３＝Ｃｚであれば、０ボルトからＶＤＤ・７Ｃｚ
／（Ｃ０＋７Ｃｚ）ボルトまでの８等分された電圧に変
換することができる。 次に、この回路の動作について
説明する。まず、出力リセット端子ＲＳＥＴがハイレベ
ルになると、出力端子ＯＵＴは０Ｖとなる。この時、書
き込み端子ＳＥＴをローレベルにしておくと、スイッチ
はすべてＯＦＦ状態となる。次にＲＳＥＴをローレベル
にし、ＳＥＴをハイレベルにする。すると出力端子を０
ＶにリセットしたトランジスタはＯＦＦ状態となり、３
つのスイッチのうちＤＡＴＡの＋側がハイレベルで−側
がローレベルのものがそれぞれＯＮ状態となる。従って
３つのスイッチのＯＮとＯＦＦの組合せによって、８種
類の電圧が出力端子ＯＵＴに与えられることになる。こ
こでは、３つのスイッチをアナログスイッチで構成した
ため、ＶＤＤを変化させると任意の出力電圧範囲を選ぶ
ことができるが、これらのスイッチをデジタル式にする
こともできる。DESCRIPTION OF THE PREFERRED EMBODIMENTS This embodiment will be described below with reference to the drawings. FIG. 1 is an example of a circuit diagram of a decoder circuit of the present invention. In the figure, the sizes of the capacitors C1, C2, and C3 are respectively C1,
Assuming that C2 and C3 and the capacitance of the load connected to the output terminal OUT are C0, this decoder circuit changes the input signal of 3 bits from 0 volt to VDD. (C1 + C2 + C3) /
It can be converted to a voltage up to (C0 + C1 + C2 + C3) volts. If C1 = 4Cz, C2 = 2C
If z and C3 = Cz, from 0 volt to VDD.7Cz
It can be converted into eight equal voltages up to / (C0 + 7Cz) volts. Next, the operation of this circuit will be described. First, when the output reset terminal RSET becomes high level, the output terminal OUT becomes 0V. At this time, if the write terminal SET is set to the low level, all the switches are turned off. Next, RSET is set to low level and SET is set to high level. Then the output terminal becomes 0
The transistor reset to V is turned off and 3
Of the two switches, the + side of DATA is at high level and the-side of DATA is at low level, respectively. Therefore, eight types of voltages are applied to the output terminal OUT by the combination of ON and OFF of the three switches. Here, since the three switches are configured by analog switches, an arbitrary output voltage range can be selected by changing VDD, but these switches can be digital type.
【０００８】図３は、本発明のデコーダ回路を液晶表示
装置に応用した例である。一般に、セグメント表示以外
の液晶表示装置はドットマトリクス方式を用いており、
画素マトリクス部とそれを駆動するデータドライバ部及
び走査ドライバ部とから成る。FIG. 3 shows an example in which the decoder circuit of the present invention is applied to a liquid crystal display device. In general, liquid crystal display devices other than segment display use a dot matrix system,
The pixel matrix section includes a data driver section and a scan driver section that drive the pixel matrix section.
【０００９】薄膜トランジスタ（以下ＴＦＴと略記）を
各画素に配置したＴＦＴ方式の場合、画素マトリクス部
は直交する信号線３３と走査線３４、及びそれらの交点
に配置されるＴＦＴ３１と液晶３２から成る。各データ
ドライバ出力は信号線３３に、走査ドライバ出力は走査
線３４に接続され、選択パルスが走査線に印加されると
ＴＦＴは導通状態となり、信号線のデータを液晶に書き
込む。データドライバ部は、シフトレジスタとデータラ
インＤＡＴＡ１〜３、サンプリングラッチＡ１〜３、ホ
ールドラッチＢ１〜３、及びデコーダ回路とから成る。
このデコーダ回路には図１に示すものを用いる。In the case of the TFT system in which a thin film transistor (hereinafter abbreviated as TFT) is arranged in each pixel, the pixel matrix portion is composed of signal lines 33 and scanning lines 34 which are orthogonal to each other, and TFTs 31 and liquid crystals 32 which are arranged at their intersections. The output of each data driver is connected to the signal line 33, and the output of the scan driver is connected to the scan line 34. When a selection pulse is applied to the scan line, the TFT becomes conductive and the data of the signal line is written in the liquid crystal. The data driver section includes shift registers, data lines DATA1 to DATA3, sampling latches A1 to B3, hold latches B1 to B3 and a decoder circuit.
The decoder circuit shown in FIG. 1 is used.
【００１０】次に、このデータドライバ部の動作につい
て説明する。シフトレジスタは内部のクロックに同期し
て、スタートパルスＳＰを一段ずつ後段へとシフトさせ
る。サンプリングラッチＡ１、Ａ２、Ａ３は、それぞれ
データラインＤＡＴＡ１、ＤＡＴＡ２、ＤＡＴＡ３の２
値データを、シフトレジスタの出力と同期して取り込
む。すべてのサンプリングが終了した後、ラッチパルス
ＬＰによって、サンプリングラッチＡ１、Ａ２、Ａ３の
データがそれぞれホールドラッチＢ１、Ｂ２、Ｂ３に転
送される。デコーダ部は、ホールドラッチＢ１、Ｂ２、
Ｂ３のデータとその反転データに基づいて前述のように
容量に蓄積された電荷を信号線に放電する。一般に、液
晶表示装置の信号線の配線容量のばらつきは極めて小さ
いため、この方法によって正確な階調表示が可能とな
る。Next, the operation of the data driver section will be described. The shift register shifts the start pulse SP to the subsequent stages one by one in synchronization with the internal clock. The sampling latches A1, A2, and A3 are two of the data lines DATA1, DATA2, and DATA3, respectively.
Value data is fetched in synchronization with the output of the shift register. After all the sampling is completed, the latch pulse LP transfers the data in the sampling latches A1, A2, and A3 to the hold latches B1, B2, and B3, respectively. The decoder section includes hold latches B1, B2,
Based on the data of B3 and its inverted data, the charge accumulated in the capacitor is discharged to the signal line as described above. In general, the variation in the wiring capacitance of the signal lines of the liquid crystal display device is extremely small, so that accurate gradation display can be performed by this method.
【００１１】本図では、薄膜トランジスタ（以下ＴＦＴ
と略記）を各画素に配置したＴＦＴ方式の画素マトリク
スを示したが、ＴＦＴの代わりに薄膜ダイオードなど非
線形素子を用いたものや、スイッチング素子を用いない
単純マトリククス方式の液晶表示装置にも適用できる。
また、多結晶シリコン等の比較的移動度の高いＴＦＴを
用いた液晶表示装置の場合には、ＴＦＴによって同一基
板上に走査ドライバとデータドライバを作製することも
可能である。特に、ＴＦＴにおいては半導体基板上のト
ランジスタに比べて特性のばらつきが大きく、アナログ
バッファ回路を用いたアナログ線順次データドライバを
構成するのが極めて困難なため、本発明のように簡単な
回路構成で多ビットのデジタル線順次データドライバを
構成できる方法は非常に実用的である。In this figure, a thin film transistor (hereinafter referred to as a TFT
Is a TFT type pixel matrix in which each pixel is arranged. However, it is also applicable to a non-linear element such as a thin film diode instead of a TFT, or a simple matrix type liquid crystal display device that does not use a switching element. ..
Further, in the case of a liquid crystal display device using a TFT having a relatively high mobility such as polycrystalline silicon, it is possible to fabricate the scan driver and the data driver on the same substrate by using the TFT. In particular, a TFT has a large variation in characteristics as compared with a transistor on a semiconductor substrate, and it is extremely difficult to configure an analog line sequential data driver using an analog buffer circuit. Therefore, a simple circuit configuration as in the present invention is used. The method by which a multi-bit digital line sequential data driver can be constructed is very practical.
【００１２】[0012]
【発明の効果】以上述べたように本発明のデコーダ回路
は、入力信号のビット数が増加しても回路規模があまり
増加しないため、多ビットのデコーダを小さな面積で低
コストで実現できる。特に、液晶表示装置のデータドラ
イバにおいては、完全にデジタル信号だけでインタフェ
ースができるため、コンピュータ用や航空機用のディス
プレイにおいては外部回路の規模も減少し、ノイズの影
響も受けにくくなり、画面の均一性が向上する。また、
ＴＦＴを用いたデジタル線順次データドライバも簡単に
構成できるため、超小型で信頼性の高い液晶表示装置を
実現できる。As described above, in the decoder circuit of the present invention, the circuit scale does not increase much even if the number of bits of the input signal increases, so that a multi-bit decoder can be realized in a small area and at low cost. In particular, since the data driver of the liquid crystal display device can be interfaced with only digital signals, the scale of the external circuit is reduced in a computer or aircraft display, and it is less susceptible to noise, and the screen is uniform. The property is improved. Also,
Since a digital line-sequential data driver using a TFT can be easily constructed, an ultra-compact and highly reliable liquid crystal display device can be realized.
【図１】 デコーダの等価回路図。FIG. 1 is an equivalent circuit diagram of a decoder.
【図２】 従来のデコーダの等価回路図。FIG. 2 is an equivalent circuit diagram of a conventional decoder.
【図３】 液晶表示装置の等価回路図。FIG. 3 is an equivalent circuit diagram of a liquid crystal display device.
３１ ＴＦＴ ３２ 液晶 ３３ 信号線 ３４ 走査線 31 TFT 32 Liquid crystal 33 Signal line 34 Scanning line
Claims (2)
変換するデコーダ回路において、容量比が１、２、４、
８．．．２(N-1) となっているＮ個の容量とＮ個のスイ
ッチを備え、前記Ｎ個のスイッチのゲートが前記Ｎ個の
２値データにそれぞれ接続されていることを特徴とする
デコーダ回路。1. A decoder circuit for converting N binary data into 2 N data, wherein a capacitance ratio is 1, 2, 4,
8. ． ． 2 (N-1) N capacitors and N switches, and the gates of the N switches are connected to the N binary data, respectively. ..
駆動されるドットマトリクス型の液晶表示装置におい
て、前記データドライバにはＮビットのシフトレジス
タ、Ｎ本のデータライン、Ｍ×Ｎビットの２段ラッチ、
Ｍ×Ｎ個のスイッチと容量を備え、前記シフトレジスタ
の各出力にはそれぞれＮビットの第一のラッチのゲート
が接続され、前記第一のラッチの入力部は前記Ｎ本のデ
ータラインに接続され、出力部は次段のＮビットの第二
のラッチに接続され、前記第二のラッチの出力は、前記
Ｎ個のスイッチと容量とに接続され、前記Ｎ個の容量の
大きさの比が１、２、４、８．．．２(N-1) となってい
ることを特徴とする表示装置。2. A dot matrix type liquid crystal display device driven by a data driver and a scan driver, wherein the data driver includes an N-bit shift register, N data lines, and M × N-bit two-stage latches.
A gate of an N-bit first latch is connected to each output of the shift register, and the input of the first latch is connected to the N data lines. The output unit is connected to the second N-bit second latch, and the output of the second latch is connected to the N switches and capacitors, and the ratio of the sizes of the N capacitors is determined. Is 1, 2, 4, 8. ． ． A display device characterized in that it is 2 (N-1) .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07994592A JP3331617B2 (en) | 1992-04-01 | 1992-04-01 | Decoder circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07994592A JP3331617B2 (en) | 1992-04-01 | 1992-04-01 | Decoder circuit and display device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002137589A Division JP3632678B2 (en) | 2002-05-13 | 2002-05-13 | Decoder circuit and liquid crystal display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05281920A true JPH05281920A (en) | 1993-10-29 |
| JP3331617B2 JP3331617B2 (en) | 2002-10-07 |
Family
ID=13704450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07994592A Expired - Lifetime JP3331617B2 (en) | 1992-04-01 | 1992-04-01 | Decoder circuit and display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3331617B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11214700A (en) * | 1998-01-23 | 1999-08-06 | Semiconductor Energy Lab Co Ltd | Semiconductor display device |
| US6542143B1 (en) | 1996-02-28 | 2003-04-01 | Seiko Epson Corporation | Method and apparatus for driving the display device, display system, and data processing device |
| US6873312B2 (en) | 1995-02-21 | 2005-03-29 | Seiko Epson Corporation | Liquid crystal display apparatus, driving method therefor, and display system |
| JP2007053459A (en) * | 2005-08-16 | 2007-03-01 | Sanyo Epson Imaging Devices Corp | Digital analog converting circuit |
-
1992
- 1992-04-01 JP JP07994592A patent/JP3331617B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6873312B2 (en) | 1995-02-21 | 2005-03-29 | Seiko Epson Corporation | Liquid crystal display apparatus, driving method therefor, and display system |
| US6542143B1 (en) | 1996-02-28 | 2003-04-01 | Seiko Epson Corporation | Method and apparatus for driving the display device, display system, and data processing device |
| USRE41216E1 (en) | 1996-02-28 | 2010-04-13 | Seiko Epson Corporation | Method and apparatus for driving the display device, display system, and data processing device |
| JPH11214700A (en) * | 1998-01-23 | 1999-08-06 | Semiconductor Energy Lab Co Ltd | Semiconductor display device |
| JP2007053459A (en) * | 2005-08-16 | 2007-03-01 | Sanyo Epson Imaging Devices Corp | Digital analog converting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3331617B2 (en) | 2002-10-07 |
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