JPH0363077B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a driving method for a liquid crystal display device that enables high duty.

Conventionally, liquid crystal display devices have been widely used in desktop electronic calculators and electronic clocks, but in recent years, as microcomputers have become lower in cost and higher in performance, small, thin, and low power consumption liquid crystal display microcomputers and portable microcomputers have become popular. Applications to terminals have become possible. For such uses, the panel area is large and it is necessary to display many characters and pictures at the same time. For example, for word processors, it is necessary to simultaneously display 20 lines of 64 alphanumeric characters. Multiplex drive is essential at this time, but the drive duty at this time is 1/160. On the other hand, the response speed of the liquid crystal itself is slow, and as a result, the duty that can be driven is currently limited to 1/16 using the normal voltage averaging method, which is an order of magnitude worse than required. Therefore, as a means to improve this drive duty, a method has been proposed in which the liquid crystal is driven via a nonlinear element or a switching element to increase the drive margin.
Nonlinear elements include metal-insulator-metal (MIM) elements, varistor elements, diode elements, etc., and switching elements include thin film transistors made of compound semiconductors and amorphous silicon. Figure 1 shows the typical electrical characteristics of a nonlinear element, and the rising voltage of the current near use is called the threshold value Vth. FIG. 2 is a schematic diagram of a matrix display using this nonlinear element.
It consists of n×m display dots connected to write selection signals T ₁ to Tm called timing lines during time-division driving and data signals D ₁ to Dn for writing display data to selected cells, respectively. Here, the nonlinear element 1 and the liquid crystal element 2 are arranged in series between the timing line and the data line to form a display cell 3. Figure 3a
is the configuration of one cell, and b is its equivalent circuit. Here, R _LC and R _NL are the respective equivalent resistances, C _LC and C _NL are the respective equivalent capacitances, and the nonlinear element is the constant resistance R _NL
It is expressed as. FIG. 4 shows respective waveforms of applied driving waveforms based on the conventional voltage averaging method in order to explain the operating principle. During the selection time, that is, the write time tw, the write signal is sent from the data line Di.
It is written to the LCD depending on whether it is ON or OFF.
When ON, the potential difference between Di and Ti is large, and when OFF, a small potential difference is applied, and a voltage is applied to the equivalent capacitance _CLC of the liquid crystal via the equivalent resistance of the nonlinear element.
At the time of this selection, R _NL <R _LC . Next, when writing is completed, the potential between Di and Tj becomes smaller, so R _NL < R _LC , and the written voltage is stored as a charge in C _LC , and R _LC・C _LC
The discharge occurs according to the time constant of 10.
msec or more, and therefore, if the write operation is performed again within 10 msec, the liquid crystal operates as if a certain potential was always applied even during the non-selection period. The voltage applied between the electrodes of the liquid crystal at this time
If the effective value of V _LC is such that when ON, V _DNR is greater than the liquid crystal lighting voltage, and V _OFFR is less than the non-lighting voltage, ON-OFF control of the liquid crystal can be performed successfully, and a display that meets the purpose can be obtained. In the commonly used matrix display that does not use such elements, a voltage is applied only when a selection is made, but by using a nonlinear element like this, it is possible to maintain the voltage applied when a selection is made even when a selection is not made. This is the principle that can improve drive duty. The operating principle of the switching element is almost the same. FIG. 5 shows an example of the operation when a drive waveform based on the conventional voltage averaging method is applied to such a matrix display. In order to drive the liquid crystal with alternating current, the polarity is reversed every half of the frame period T _F. Also, A,
In section B, the relationship between lighting and non-lighting of the selected cell and the non-selected cell is reversed, and in sections C and D, the relationship is the same. Drive is V-5V method (when selected, ON)
5V _L (method in which V _L is applied when not selected). First, in sections A and B, only the cell itself is lit in Di (ON), and the other cells are not lit. The write voltage V _N at the time of selection is a lighting signal, so it is lower than the applied voltage 5V _L.
Vth is slightly smaller than the voltage dropped. i.e. V _N 5V _L
At the same time as -Vth is switched to non-selection, the data line signal changes to a non-lighting signal, so as shown in Figure 4, V _N
The potential of the voltage and the voltage of the data line, that is, the voltage applied to the nonlinear element is (V _N +V _L ), that is, (6V _L −Vth), which is larger than the Vth of the nonlinear element, so
The nonlinear element has a low resistance and easily discharges toward the nonlinear element as shown in E in the figure. For this reason, when only the cell is lit and the other cells are not lit, as shown in the figure,
The effective value of ON V _ONR becomes considerably small. On the other hand, if only one cell is not lit and the other cells are lit, when Di (OFF) is applied to the data line, the write voltage V _F
becomes V _F =3V _L −Vth. After this, when it switches to non-selection, the voltage applied to the nonlinear element is V _F −
V _L is (2V _L −Vth), which is lower than Vth, so the nonlinear element has a high resistance, and only the liquid crystal side discharges, and the write voltage is maintained as shown in the figure.
Therefore, the effective value is high. As a result, in sections A and B,
V _ONR /V _OFFR is less than 1, which is a reverse development, that is, the light does not come on when it should be on, and it comes on when it is not on, which is really bad.

On the other hand, in sections C and D, all cells are in a lit or non-lit state. First, when it is turned on, up to V _N is written in the same way as before, but even if it is switched to non-selection, the lighting signal is maintained on the data line, so
The voltage applied to the nonlinear element is (5V _L −Vth−V _L =
4V _L −Vth) and since this voltage is lower than Vth, the nonlinear element maintains a high resistance and therefore V _LO
(ON) remains at high voltage for half a frame.
On the other hand, when the lights are off, there is not much difference between the A and B sections. Therefore, in this case, the effective value V _ONR when lit and the value when not lit are
The ratio of V _OFFR is larger than 1, and lighting and non-lighting are well controlled. In this way, the display pattern, that is, the waveform of the data line signal (the ratio of the number of lights on and off), changes the effective value, especially on the ON side, and this has the serious drawback that the display may not be well controlled. be. A similar result occurs in the switching element because the leakage is not completely zero when it is OFF.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for driving a liquid crystal panel that enables stable control of lighting and non-lighting regardless of the display method.

The present invention provides a driving method in which the average voltage of the data line signal is constant within a half frame or one frame period, regardless of the signal (whatever the ratio of non-lighting to lighting). Basic.
For example, if we compare the effective values applied to a cell with a liquid crystal in sections A and C and B and D in FIG. The effective value is the lowest when all cells are lit, and the effective value is highest when all cells are lit, and the effective value changes depending on the ratio of lit and non-lit signals in a half frame of the data line.
In other words, the average value of the data line potential changes depending on the ratio of lighting and non-lighting signals, and thereby changes with the effective value applied to the liquid crystal cell. That is, in the sections A and C, the average voltage of the data line approaches OV as the number of non-lighting signals increases, and conversely, as the number of lighting signals increases, it approaches 2V _L. Therefore, it is sufficient that the average voltage of the data line signal is constant or close to constant regardless of the ratio of lighting and non-lighting signals.

FIG. 6 shows an example of a drive waveform when the average voltage of the data line is constant. Although the drive level is V-5V, it can also be V-3V, which is common to the V-NV system. In the conventional case of FIG. 5, a certain line is selected by the timing line, and immediately after that period ends, the line moves to the selected section of the next line. In the method of the present invention shown in FIG. 6, once one line has been selected, a period in which no line is selected is inserted. For convenience, the selected period will be referred to as a write cycle (WC), and the period in which no line is selected will be referred to as a dummy cycle (DC). First, during the first half of the Ti (j-1) period, the j-1 line is selected by the timing signal Tj-1, and the pixel (j-1) is connected to the data line Di.
A lighting signal is applied by the signal. During this time, a relatively high voltage is applied to the liquid crystal pixel via the nonlinear element, and the pixel lights up. Next, in the latter half of the same period, the timing signal Tj-1 returns to its original state, and at this time a state occurs in which no line is selected. During this time, the signal on the data line Di is set opposite to the first half (if the first half is a lighting signal, the second half is a non-lighting signal). When the timing signal during this period maintains the selection side potential, that is, the first half, it is called a write cycle, and when no line is selected, it is called a dummy cycle. In this way, a dummy cycle is inserted after a write cycle, and the signal on the data line in the dummy cycle is reversed with respect to the write cycle. As a result, if the write cycle and dummy cycle take the same time, the average value of the voltage within a half frame for any data line is constant regardless of the display pattern, and the V-5V method shown in Figure 6 In other words, A
The value is constant at V _L in the frame and 4V _L in the B frame. As a result, the average potential of the data line differs depending on the display pattern, which affects the effective potential applied to the liquid crystal display, resulting in an incomplete display state. is also written to each pixel, the effective voltage becomes constant, and a stable and complete display pattern can be obtained. In this method, the arrangement of dummy cycles and write cycles can be reversed, or the line can be divided into several blocks and a dummy cycle and write cycle can be assigned to each block (the lines within a block can be written continuously). , then provide a dummy cycle). Also, rather than keeping the average value on the data line constant, for example, even if the ratio of the write cycle and dummy cycle periods deviates to 2:1, the display pattern on each pixel will have a slight effect, but it is not practical. Of course, there is no problem as long as it is within an acceptable range.

Furthermore, the fact that the drive voltage can be done at the drive level using the conventional voltage averaging method is the 6th aspect of the V-5V method.
Although illustrated in the figure, experiments have shown that the average value on the data line side does not necessarily have to match the non-selected level of the timing signal. 6th
In the figure, in the A frame, the average value of the data line is equal to the non-selected level V _L of the timing line, and in the B frame, it is also 4V _L. However, if the average value of the data line is set between 0 and _VL in the A frame, the effective value can be obtained more effectively with the same voltage. To do this, for example, the lighting level of the data line is 0 and the non-lighting level is 2V _L , but the entire level used for data is offset by △V to the negative side, or the lighting level remains 0V and it is not lit. Possible means include offsetting the level to the negative side (that is, shifting the vibration of the data line from 2V _L ), or using both at the same time.

The driving method shown in the present invention can also be applied to a liquid crystal display using switching elements.

FIG. 7 shows an example of a cell that drives a liquid crystal 11 using a MOS transistor 10 as a switching element. Thin film transistors (TFTs) are often used as common elements. TFT has a large leakage when it is OFF, and at this time, the way the charge held in the liquid crystal cell is discharged differs depending on the display pattern, that is, the magnitude of the average voltage of the data line.Therefore, like nonlinear elements, depending on the display pattern, The effective value voltage applied to the liquid crystal cell varies.

FIG. 8 shows a driving method that eliminates this effect by applying the present invention. The gate of the timing line is always turned on to select the line, so in this case the signal has the same polarity in every frame. Data is written on the data line between line cycles, and then an inverted signal is applied during the dummy cycle. As a result, the average value of the potential of the data line is always 0V regardless of the display pattern. Also, in this case, the average value of the data line does not necessarily have to be 0V as shown in the figure. This means selecting the optimum value depending on the OFF leakage characteristics and ON characteristics of the transistor. It is clear that other variations are possible as well as non-linear elements.

FIG. 9 is an example of a circuit for realizing a driving method in which a dummy cycle is inserted according to the present invention. The n-bit shift register 20 serially transfers n input data D _D signals using the clock _φ1 , and stores the display data in the shift register before selecting one of the displayed n lines. When selected, the latch clock L
is transferred to the n-bit latch 21 in parallel. The exclusive OR 22 has a function of inverting the data line signal during the dummy cycle period. The selection gate 23 selects d ₁ according to the outputs E ₁ to En.
Select one of the _d2 levels and output to the _D1 to Dn lines. The levels of d ₁ and d ₂ are exchanged every half frame as shown in the figure. On the other hand, the m-bit shift register 24 sequentially shifts the line to 1 by the timing line.
In order to select one by one, a start pulse is applied to the input data DT, and then data of "1" is sequentially transferred by the clock _φ2 . As a result
“1” is sequentially output to S ₁ to Sm. The AND gate 25 is gated by the clock φ ₂ to provide a non-selection signal during the dummy cycle.
The selection gate 26 selects the level of d ₁ or d ₂ according to the outputs A ₁ to Am and outputs it to T ₁ to Tm, which are replaced every half frame.

FIG. 10 shows an example of the selection gates 23, 26, which are composed of two transmission gates consisting of P channel transistors 31, 33 and N channel transistors 32, 34.

FIG. 11 shows the operation timing of FIG. 9. It can be seen that, compared to the conventional circuit shown in FIG. 5, the circuit shown in FIG. 9 only requires the addition of an exclusive OR 22 and an AND gate 25, making it possible to implement the dummy cycle insertion drive according to the present invention relatively easily.
In FIG. 9, to realize the waveform of FIG. 8 using TFT, the selection gate 25 may be replaced with an inverter, and the selection gate 22 may be replaced with an exclusive OR gate.

In this way, the present invention ensures that the average value on the data line side is always constant regardless of the display format.The effective value at a selected point is not affected by the effective value at other points. Moreover, since it is always stable, it is possible to display not only mere "1" and "0" display, that is, graphic display, but also image display, that is, gradation display. In the conventional multiplex drive method, when using a simple amplitude modulation method for the drive circuit, the effective value at a certain point is affected by the effective value at other points as described above, so it is difficult to display gradations by delicate effective value control. Although this was impossible, if we use a driving method that keeps the average value constant regardless of the waveform as in the present invention, the interval display becomes
This can be realized using the amplitude modulation method.

FIG. 12 shows a specific drive waveform for gradation display using a nonlinear element based on the amplitude modulation method used in the present invention, with only half a frame extracted. Basically, this is realized by replacing the signal Di on the data line shown in FIG. 6 with a signal DN that is amplitude-modulated so as to provide a voltage level corresponding to the gray scale. First, considering the M-1st selection line, in the selection period P _M-1, a signal of -VE is applied to the voltage amplitude VS according to the gradation during the write time W _M-1 , and during the dummy period D _M- In _{step 1} , apply an amplitude +VE that is exactly opposite to the voltage applied during writing. The same applies to the selection periods P _M and P _M+1 , and the magnitude of VE determines the gradation.

FIG. 13 is a graph showing the correspondence of gradation signals, in which the horizontal axis plots the applied voltage (VT-VE) and the contrast C corresponding to this voltage. It is sufficient to apply a voltage as VE according to the required gradation with contrast between 0% and 100%.

As a result, using the driving method shown in Figure 12, the average value of the data line is always kept at a constant voltage, making it possible to stably display gradations that manipulate delicate voltages using the amplitude modulation method. For example, in the case of TV image display, the amplitude of the video signal is directly applied as a contrast signal, as is done in a normal CRT, so it has the great advantage that it can be realized without using any special circuit for video signal processing. . The chart shown in FIG. 12 is only a portion taken out, and when the polarity is inverted for each frame, the polarity of the applied signal is also reversed. Further, although the average value level of the data line is set to V _L in FIG. 12, even if it deviates from this level, the drive can be performed without changing the effect. Further, even in a format using a switching element as shown in FIG. 8, it is impossible to display gradations using the amplitude modulation method in which the dummy cycle of the present invention is inserted.

FIG. 14 shows an example of a drive circuit for gray scale display using the amplitude modulation method used in the present invention, and FIG. 15 shows its operating waveforms. Shift register 35, shift register 36, and AND gate 46 function in the same manner as in FIG. 9th
What differs from the diagram is the signal placed on the data line DN and the drive circuit. The video signal V _SO is the output of the positive amplifier 30, the delay line 32 for one scanning line, and the signal via the negative amplifier 31, and is turned on by the ON switch 33 by the write cycle φ and by the dummy cycle φ.
A positive and negative mixed video signal is sent to the video signal line VS via the switch 34 that is turned on. An example of the VS signal pattern is shown in FIG. 15. When the Nth output QN of the shift register 35 for data scanning is turned on, QN
The video signal at the timing when the transistor 37 turns on is sampled and held in the capacitor 38 by the transistor 37. Like this from the beginning to the end,
When the data is held by each sample and hold circuit, the charge in the capacitor 40 is discharged by the signal I, and then the sampled and held data is transferred to the transistor 39 by the latch pulse L.
The signal is transferred to the next sample and hold capacitor 40 via . Thereafter, data is loaded onto the data line DN by an amplifier made up of transistors 41 and 42 to drive a nonlinear element 44 and a liquid crystal cell 43 made of liquid crystal 45. To explain with reference to FIG. 15, the video signal V _S-1 is a signal half a cycle before the data actually placed on the DN. That is, in the write cycle W _M , the sampled and held signal is outputted to the DN line in the dummy cycle DM. At the same time, the signal sampled and held in the dummy cycle DM is DN in the next write cycle W _M+1 .
Output to line. First, during the write cycle W _M , the video signal V _S is sampled and held using the outputs Q ₁ to QE of the shift register. Next, after the charge accumulated in the capacitor 40 is discharged by the discharge pulse I, the new data is held in the capacitor 40 again by the latch pulse L, and from immediately after this, until the next latch pulse is input, the data is transferred to the DN line via the buffer. Data is output and retained. The method shown in Figure 14 is based on the video input signal.
The V _S line is originally mixed with an inverted signal for dummy cycles, but other video input signals
There is a method of using V _S of the same polarity and creating signals with inverted polarity for the write cycle and dummy cycle separately for each line.

FIG. 16 shows an example of this method. It has a buffer 60 consisting of transistors 52 and 54 and a buffer 61 with an amplification factor of 1 consisting of transistors 53 and 55. During the write cycle, the transistor 57 is turned on by φ, and a signal with the same polarity as the video signal V _SO is also output during the dummy cycle. Transistor 56
turns on, and a signal with the opposite polarity to the video signal _VSO is applied to the DN line.

In the systems shown in FIGS. 14 and 16, the signal applied to the data line during the dummy cycle is a signal with a polarity opposite to that of the immediately preceding write cycle. On the other hand, in order to keep the average value of the data line constant regardless of the display pattern, during the dummy cycle, the timing line during the write cycle (Fig.
It is also possible to calculate the total average value (T ₁ to Tm) and apply a reverse voltage of the total average value during the write cycle, regardless of which timing line is selected in the dummy cycle.

FIG. 17 shows this specific circuit. A switched capacitor integrator is configured by transistors 75 and 77, capacitors 76 and 80, and an operational amplifier 79, and the output of the operational amplifier 79 is such that the total average value of each timing line of the video signal input is always output. . Therefore, during the write cycle, the transistor 82 is
When turned on, the output of the operating amplifier 78 is applied to the line. This output data naturally differs depending on the display cell to be written by the selected timing line. On the other hand, the data output when the transistor 81 is turned ON during the dummy cycle period is an integrated output, so the data output in any dummy cycle is almost the same within a period of about -frames.

As described above, in the present invention, by adding a dummy cycle before or after a write cycle, it is possible to keep the average value of the voltage applied to the data line constant. As a result, no matter what the display pattern is, the effective value of a certain pixel is stable without being affected by the effective value of other pixels, so the same contrast can be obtained no matter what the display pattern is.

[Brief explanation of drawings]

FIG. 1 shows the characteristics of the nonlinear element, FIG. 3 shows its equivalent circuit, and FIG. 4 shows its basic operation. FIG. 2 shows a matrix liquid crystal display in which nonlinear elements are arranged, and FIG. 5 shows its operating waveforms. FIG. 6 is an example of a method of inserting and driving a dummy cycle according to the present invention. FIG. 7 shows a display cell using switching elements, and FIG. 8 shows drive waveforms when the dummy cycle insertion drive method of the present invention is applied. FIG. 9 shows an example of a drive circuit that realizes dummy cycle insertion drive using a nonlinear element.
The figure shows a specific example of the selection gate 23 or 26, and FIG. 11 shows its operating waveform. 20...Shift register for data transfer, 24...Shift register for timing line selection, 21...Latch, FIG. 12 is an example of a dummy cycle insertion drive waveform when performing gradation display by a switching element. Further, FIG. 13 shows a contrast curve of the liquid crystal cell with respect to applied voltage. FIG. 14 shows an example of a drive circuit for dummy cycle insertion drive for gradation display. FIG. 15 shows its operating waveform. 16th
FIG. 17 shows an example of a data signal generation circuit applied during a dummy cycle.

Claims (1)

[Claims] 1. A liquid crystal sealed in a pair of substrates, signal lines and scanning lines arranged in a matrix on one of the substrates, and pixels provided at intersections of the signal lines and scanning lines. In a liquid crystal display device having an electrode and a thin film transistor connected to the pixel electrode, a data signal applied to the signal line is divided, and the data signal applied to the data line is divided into a first period and a second period of one selection period of the data line. It has a data line drive circuit that inverts the polarity of the divided data signal and applies it to the data line, and the first data signal applied to the data line during the first period has a display level of the data line. A liquid crystal display device, wherein the second data signal applied to the data line during the second period is a non-display level signal of the data line.