SE466423B - SET AND DEVICE FOR ELIMINATION OF OVERHEALING IN MATRIX ADDRESSED THINFILM TRANSISTOR IMAGE UNITS WITH LIQUID CRYSTALS - Google Patents

Description

"4e6,423 switches are usually based on either amorphous silicon technology or polycrystalline silicon technology. At present, amorphous silicon technology is preferred because it requires a lower treatment temperature. The above construction method provides a rectangular set of capacitor-like circulating elements. The application of a voltage to the pixel electrode provides an electro-optical conversion of the liquid crystal material. This conversion is the basis for the text display or graphical information seen on the device. It is pointed out that the invention is particularly applicable to the one described above. the pixel unit, in that each of the pixel electrodes is connected to its own semiconductor switch, which can be switched on or off, so that each individual pixel element can be regulated by means of signals supplied to it with the same semiconductor switches connected thereto. such as electron valves for depositing charge on individual pixel electrodes.

Each transistor is supplied with a scan line signal and a data line signal. In general, there are M data lines and N scan lines. Typically, the gate of each transistor switch is connected to a scan line, and the source electrode or d-electrode of the transistor is connected to a data line.

When the device is operating, a signal level is established on each of the M data lines. At this point, one of the N-scan lines is activated so that the voltages that occur on the data lines are applied to the pixel electrodes through their respective semiconductor switch elements. A necessary consequence of the described arrangement is that each pixel electrode on both sides is surrounded by data wires.

One of the data wires is the data wire connected to the pixel electrode. However, the second data line is connected to an adjacent pixel electrode. However, the second data line of the 4ee'42 is connected to an adjacent pixel electrode. The latter data line carries another information signal. This structure also includes certain capacitive features. In particular, the pixel electrode and its opposing ground plane electrode part form a capacitive structure. Furthermore, there are parasitic capacitances between each data line and its surrounding pixel electrode elements. A parasitic capacitance also exists between the source electrode of the semiconductor switching element and the d-electrode. The parasitic capacitances allow unwanted signals to be applied to the pixel electrodes.

In a typical sequence of operations, desired voltage levels are established on the data lines, and a scan line is activated, so that these voltages are applied to a single row of pixel electrodes. After a sufficient time for charging the capacitor with liquid crystals, another scanning line is activated, and a different set of data voltages is applied to a different pixel line. Typically, an adjacent pixel row is selected for writing video information. Thus, in a typical operation, one line of the imaging device may be written at a time, from the top of the screen to the bottom of it. In television applications, this writing takes place from top to bottom in approximately 1/30 or 1/60 second. During this time period, a complete image is thus displayed on the screen. This image can include both text and graphic information.

As is well known in electrical technology, capacitive effects are generally proportional to area and inversely proportional to distance. Thus, in high-resolution imaging devices with liquid crystals, the effects of parasitic capacitance are particularly undesirable due to the requirement for a small distance between the lines. In typical applications referred to herein, such as television technology, the pixel electrodes have a side of about 100 microns and are separated by a gap 466,425 of about 10 microns, with an area of about 10 x 10 microns being deposited from each pixel for placement of its semiconductor switch elements. Thus, it is found that in high-resolution thin film transistor matrix addressed image units with liquid crystals, the parasitic capacitance between the data lines and the pixel electrode is not insignificant in comparison with the pixel capacitance. It is also observed that the parasitic capacitance between the data lines and the pixel electrode is increased by the presence of parasitic capacitance from the source electrode to the d-electrode in the switching element itself. When such a picture unit operates, the voltage at a pixel is determined during its radar address time. The semiconductor switch is then switched off, and the voltage should remain constant until the image display is renewed. However, each change in the voltage on an adjacent data line causes a change in the voltage on the pixel. In many drive arrangements, the effective value voltage on a data line typically varies between 0 and 5 volts, depending on how many elements in the column are on.This leads to an uncertainty or overheating of the voltage at the pixel. The maximum value for this voltage is 2 * ßCD + CSD) / CLC] * 5 volts. Here, CD is the parasitic capacitance arising from the proximity of the data wires to the data point electrode, CSD is the parasitic capacitance of the switch from source electrode to d-electrode, and CLC is the capacitance connected to the liquid crystal cell structures themselves. Factor 2 is obtained by having two data wires adjacent to each pixel electrode. In a design where there are approximately 100 pixels per 2.5 cm, this gives a maximum voltage error of an effective value of approximately 0.2 volts. Although this is not critical for on-board imaging devices, it is of significant importance for grayscale imaging devices, where changes in the effective voltage value of 0.05 volts are visible. t 'n. n c4ee'423 One way to reduce crosstalk of the kind discussed above is to use a memory capacitor in parallel with CLC. This reduces the maximum fault voltage. However, this method is undesirable, as it usually requires additional processing steps, as it may cause further defects and as it reduces the active area of the pixel elements.

According to a preferred embodiment of the present invention, a matrix-addressed image unit device with liquid crystals with means for successively supplying the scanning lines with an activation signal also comprises means for supplying the data lines with a plurality of data signals.

According to the present invention, these data signals are operative for a period of time between successively activated scan line activation signals, so that during a first part of this time the desired voltage levels are applied to the data lines. During a second part of this time period, corrective voltage levels are applied to the data lines, so that over these whole time periods a voltage of approximately constant effective value is applied to at least some of these data lines. According to another embodiment of the present invention, an image unit with liquid crystals is caused to operate so that this voltage of constant effective value is reached. According to another embodiment of the present invention, a plurality of scan line time periods are allowed to elapse before a corrective voltage level is achieved, so that again a voltage of approximately constant effective value is reached over a specified time period. When liquid crystal imaging units are made to operate in this manner, the uncertainty in the voltage of a pixel element caused by parasitic capacitance between the data leads and the pixel electrode is eliminated. A number of bodies for achieving these results are offered here.

An object of the invention is thus to eliminate interference in thin film transistor matrix addressed image units with liquid crystals which are caused by the presence of parasitic capacitance effects.

Another object of the invention is to provide a method and means for causing a liquid crystal display device to operate in such a way that the presence of a data line waveform of a voltage of substantially constant effective value is achieved.

A further object of the invention is to drive liquid crystal displays in such a way that the voltage induced by the parasitic capacitance on a pixel electrode is the same for all pixel elements, in particular all pixel elements located in a single column. .

A further object of the invention is to reduce the uncertainty in the pixel voltage level, so that there is a constant shift, which can be used to compensate by suitable additive scaling of the data voltages. Yet another object of the present invention is to improve the operation of both liquid crystal and non-gray liquid crystal imaging devices.

Finally, it is an object of the present invention, which is not limited thereto, to eliminate crosstalk in liquid crystal imaging devices.

The invention is explained in more detail below with reference to the accompanying drawings.

Fig. 1 is a diagram generally illustrating the structure of the present invention; Fig. 2 is a schematic electrical circuit diagram now showing a portion of the pixel array shown in Fig. 1, showing in particular the presence of the parasitic capacitors whose effects are sought to be mitigated by the invention, Fig. 3 is a diagram where voltage is plotted against time for specified data line and scan line signals, Fig. 4 is a diagram showing voltage as a function of time for a data line, where the effective value is corrected. The voltage is applied after a specified plurality of scan line activation periods, Fig. 5 is a schematic diagram illustrating a method of supplying effective value voltage correction waveforms for the situation in which an on-off imaging unit is used; Fig. 6 is a schematic diagram which shows a variant of the circuit shown in Fig. 5, Fig. 7 is a schematic diagram of an analog effective value voltage com pension arrangement for greyscale imaging devices, and Fig. 8 is a schematic diagram showing an alternative digital grayscale imaging compensation system.

Fig. 1 is an overall view of a liquid crystal display device 10. The primary component of such a device is a set of individually adjustable imaging elements. Typically, this set is arranged in one. rectangular network, where each network site comprises a transparent pixel electrode and its associated semiconductor switch, which supplies a voltage to the associated pixel electrode. There are typically as many semiconductor switches as pixel electrodes. However, it is pointed out that this is not required for the operation of the present invention. Although it is stated that the pixel array is generally in the form of a rectangular network, the present invention is not limited to the use of structures in the form of rectangular networks. For ease of presentation and understanding, the pixel array 20 may be considered to be a rectangular pixel array, which is arranged to include M columns and N rows. The data drive 30 is supplied with serial data, which represents video information in analog or digital form.

A pixel clock, which typically operates at M times the frequency of the specified clock, is used to provide proper timing of the data drive 30.

The data drive 30 thus typically possesses M discharges. These outputs are typically all valid at a given time, at which the scan drive 40, under control of the lead clock signal, allows data from the M output drive lines to be applied to a series of pixel electrodes by means of a semiconductor switch located at the intersection of the mth and data drives. nth scan scan drive line. Thus, it is clear that there is a scan drive line for each row in the pixel array 20. Thus, there are generally N leads from the scan drive 40.

The problem obtained due to the arrangement of pixel electrode and data electrode is shown in particular in Fig. 2. Particular attention is paid to the pixel electrode connected to the middle data line and the nth scan line. It is observed that a capacitive circuit element CLC is present due to the presence of the pixel electrode 21 together with its opposite ground plane electrode part (not visible) and the associated liquid crystal material (also not visible).

Fig. 2 also shows the presence of the CSD of the parasitic capacitor from the source electrode to the d-electrode, which is connected to the switching element 25. This capacitance is denoted by the symbolic CSD of 4es'42. Fig. 2 further shows the presence of the parasitic capacitance CD, which is present between the mth data line and the indicated pixel electrode 21. (Other pixel electrodes are shown but are not provided with reference numerals.) It further appears that a parasitic capacitance is present between the pixel electrode 21 and the data line (m + 1) to the right of the same in Fig. 2. However, it is assumed here that this capacitance is taken into account when determining the value for CD, with to which it is connected. It is also noted that the capacitance CD and the capacitance CSD are effectively parallel, so that their effects are additive. Furthermore, it appears that the data lines have the reference numeral 24 and likewise that the scan lines have the reference numeral 22.

The problem solved by the invention will now be considered further with a more accurate analysis of Fig. 2. In particular, it is observed with respect to the pixel electrode 21 that the voltage signals appearing on the data line (m + 1) can be applied to the pixel electrode 21 by its capacitive connection (not shown, see above) to this data line, which is present due to the necessary proximity between the pixel electrode 21 and the data line (m + 1). Similarly, signals applied to the data line m may also appear on the pixel electrode 21, even if the semiconductor switch 25 is turned off due to voltages applied to the data line m, since the parasitic capacitance CSD can connect the data line m to the pixel electrode 21. Likewise, the pixel electrode 21 is also capacitively connected via CD to the data line m for the same reason as it is connected to the data line (m + 1). During time intervals, during which information is supplied to other lines (for example, the scan line (n + 1) or the scan line (n + 2), active), false signals can also be supplied to line n. This is the problem the present invention seeks to alleviate. For illustrative purposes, the parasitic capacitances are shown only for the cell in row n and column m. Although these effects are present for all pixel cells, they are considered for illustrative purposes only for the above-mentioned cell.

The method of solving the above-mentioned crosstalk problems is illustrated in Fig. 3. In particular, the first waveform shown therein illustrates two ways of solving the problem. Time periods T1 and T2 are associated with one of these modes. The time period T3 is associated with another of these methods. They are displayed in the same time scale only for the sake of simplicity.

First, the mode of operation of the present invention during time periods T1 and T2 is considered. The crosstalk correction method shown for the time period T1 + T2 is applicable to binary (ie on-off) picture units. In particular, the waveform shown in the first two diagrams of Fig. 3 illuminates the signals intentionally applied to the pixel electrode in the second row and middle column. When the scan line n is active (such as during the first half of the period T1), a "1" is written on the pixel electrode. During the second half of the period T1, a "0" is applied to the data line, even if it is not written in the pixel electrode, since the scan pulse is not active during the second half of the same. The opposite situation applies if, during the period T1, it is desired to enter a binary "0" in the same pixel cell. Thus, over the time period T1, there is a voltage of constant effective value, which is applied to the data line m. A compensating voltage can be applied to counteract this voltage of constant effective value, so that a better screen image is obtained.

Attention is now focused on the way to eliminate interrogation shown in the period T3. It is again pointed out that these two different ways are shown in the same figure, for the sake of simplicity only and for comparative purposes. In general, the voltage waveforms shown for the data line m in the period T3 are of a type other than the simple binary complements, which are shown for those supplied during the time period T1 + T2. Especially oc: 4e6'42; 11, the manner shown by the waveform on the data line m during the period T3 is applicable to the situation in which grayscale display units are used. For gray-scale imaging units, a voltage V1, for example 0 3 V1 í Vmax, is applied during the first half of the line address time, and its rms complement is applied during the second half.

In particular, its rms value complement is calculated as: During the time period T3, the data line m is thus supplied with two special voltages. During the first half of the time period, the voltage V1 is applied. During the second half of the time period T3, the voltage applied to the data line, V2, is its effective value complement. Again, this ensures a constant rms value voltage on the data line m. It is further pointed out that if higher voltages than V0 = Vmax are available, the correction can be applied over a shorter period of time to generate the same constant rms voltage levels. The time interval T3 does not have to be divided into two equal parts. Another embodiment of the invention is shown in Fig. 4. However, the main elements in question are nevertheless the same.

After a certain number of radar address times, the Nmax correction voltage of the data line m, so that over an extended period of time a supply time is applied, the rms value voltage has a constant value. As shown in Fig. 4, the voltage applied during the correction interval is selected to be the rms value complement to the average voltage applied during the Nmax radar address times. It should be noted that Fig. 4 shows relative values and time control, and that especially during the radar address times shown, it is not necessarily the case that all the data values are binary values. In the embodiment shown in Fig. 4, all the data lines are addressed in the normal way, after which an effective value correction waveform is applied, so that a constant effective value voltage is maintained on the data line over the entire interval (line address times + correction interval). If the same amplitude is applied during the correction, the correction time interval is equal to Nmax line address times. If double the maximum data voltage is available, only a quarter of the line address time is required.

Digital means for performing the method shown during periods T1 and T2 in Fig. 3 are shown in Figs. 5 and 6. It should be particularly noted that XOR circuits 31 can be used to perform the above-mentioned desired binary completion operation. For a two-level imaging unit, this circuit provides a waveform of constant effective value, which is generated by inverting data for half of the line address time, which activates the scan output signal for the non-inverted half of the line address time. This is accomplished with an XOR gate on each data drive output as shown in Fig. 5 or by using an XOR gate on the serial data input line to a shift register in the data drive stage 30. In this latter embodiment, data is entered in the data drive stages twice for each line address time. It is also pointed out that in this latter embodiment only a single XOR circuit 32 needs to be used (see Fig. 6).

For a multi-level or grayscale display unit, embodiments of the above-described corrective mode are shown in Figs. 7 and 8.

In particular, in the circuit shown in Fig. 7, analog sample and hold drive stages 55 and 56 are used. The rms value component is generated using analog circuits, for example the squared 51, the adder / subtractor 52, the square root calculator 53 and the switch 54, which by scanning activation the signal is selected to select raw input line video data or analog video data, which are processed to provide rms complementary values. Timing signals applied to samples and hold circuits 55 and 56 ensure that valid data is simultaneously available for a single selected row of the imaging unit in accordance with what '4a6'42s 13 is determined by its associated video imaging data.

A second embodiment of the effective value complement generating means is shown in Fig. 8. In this embodiment, digital data and a look-up table (LUT) are used for determining the effective value complement. Digital-to-analog converter 66 was used as the data line driver. In particular, Fig. 8 shows the situation in which video data is inserted in digital form, eight bits being assigned to determine one of 256 grayscale levels that can be applied to the pixel electrodes. In particular, the data look-up table 60 is supplied, which (for example) represents a 256 x 256 element ROM, which is used to determine the effective value complement for any of the possible 256 input combinations. The scan enable signal controls the switch 64, which selects either the raw digital data or digital data being processed to determine their rms value complement. See, for example, the waveform shown during the second half of the time period T3 in the first diagram shown in Fig. 3. These eight bits of binary data are fed to the data bus and the data latches 65. Each of these latches drives a digital-to-analog converter 66, which is used to drive the various data lines in the pixel array. In this way, the desired rms voltage waveform is supplied to the data lines, so that the desired constant rms voltage is achieved.

It is thus clear that the method and apparatus according to the invention are suitable for eliminating crosstalk in matrix-addressed image units with liquid crystals.

More specifically, it appears that the method and apparatus according to the invention offer means for compensating for additional signals which are possibly supplied to the various pixel elements in an undesired manner. It is clear that this method is of particular importance for high-resolution imaging devices due to the higher parasitic effects due to denser structures. Thus, the uncertainty in the voltage of an element caused by the parasitic capacitance between the data wires and the pixel electrodes is removed. It is emphasized that the method according to the invention is easily feasible and solves a significant problem in the production of high-resolution imaging devices with liquid crystals. Although the invention has been described in detail with respect to certain preferred embodiments thereof, these may be modified and modified by those skilled in the art. The appended claims are intended to cover all such modifications and changes as fall within the scope of the invention.

Claims (9)

4eeå423 15 PATENT REQUIREMENTS A picture unit device (10), characterized by a plurality of pixel electrodes (21), which are arranged in a mains pattern on a first insulating substrate, a plurality of semiconductor switching devices (25), which are so connected to the corresponding pixel electrodes (21) that are connected thereto, a second substrate, on which is arranged at least one ground plane electrode, which second substrate is arranged next to the first substrate and at a predetermined distance therefrom, a material with liquid crystals arranged between the substrates, so that the pixel electrodes (21), the ground plane electrode or ground plane electrodes and the liquid crystal material form electrical devices with capacitive characteristics, a plurality of electrically conductive scanning leads (22), each connected to a plurality of those with a row of the pixel electrode network connected semiconductor switching devices (25), a plurality of electrically conductive data lines (24), s if each is connected to a plurality of the semiconductor switching devices (25) connected to a column of the pixel electrode network, means (40) for sequentially supplying a unipolar activation signal to the scanning lines (22), and means (30) for supplying a plurality of unipolar data signals to the data lines (24), which data signals are operative during a period of time between initiating successively activated scan line activation signals, so that during a first part of said time period desired voltage levels are applied to the data lines and during a second part of said time period, corrective voltage levels are applied to the data lines, so that during said time period an approximately constant effective value voltage is applied to 466,423 at least some of the data lines. Device according to claim 1, characterized in that the corrective voltage levels are binary complements of the desired voltage levels. Device according to Claim 1, characterized in that the corrective voltage levels represent the effective value complement of the desired voltage levels. in Device according to claim 1, characterized in that the first part of said time period and the second part of said time period are of equal duration. 5. A method of driving a thin film transistor array-addressed imaging unit (10) having liquid crystals with scanning lines (22) extending in a first direction and data lines (24) extending in a second direction, k characterized in that a single-pole activation signal is successively applied to the scan lines (22), and that a plurality of single-pole data signals are supplied to the data lines (24), which data signals are operative for a period of time between initiating successively activated scan line activation signals part of said time period desired voltage levels are applied to the data lines and during a second part of said period corrective voltage levels are applied to the data lines, so that during said time period an approximately constant effective value voltage is applied to at least some of the data lines. 6. A method according to claim 5, characterized in that the corrective voltage levels are the binary complement of the desired voltage levels. 4e6i423 I? Method according to claim 5, characterized in that the corrective voltage levels represent the effective value complement of the desired voltage levels. 8. A method according to claim 5, characterized in that the first part of said time period and the second part of said time period are of equal duration. A picture unit device (10), characterized by a plurality of pixel electrodes (21) arranged in a mains pattern on a first insulating substrate, a plurality of semiconductor switching devices (25), so connected to the corresponding pixel electrodes (21), that they are connected to these, a second substrate, on which at least one ground plane electrode is arranged, which second substrate is arranged next to the first substrate and at a predetermined distance therefrom, a material with liquid crystals arranged between the substrates, so that the pixel electrodes ( 21), the ground plane electrode or ground plane electrodes and the liquid crystal material form electrical devices with capacitive characteristics, a plurality of electrically conductive scanning leads (22), each of which is connected to a plurality of semiconductor switching devices (25), connected to a row of the pixel electrode network, a plurality of electrically conductive data lines (24), which were and one is connected to a plurality of semiconductor switching devices (25) connected to a column of the pixel electrode network, means (40) for sequentially supplying a unipolar activation signal to the scanning lines (22), and means (30) for supplying a plurality of unipolar data signals to the data lines (24), which means are operative for a period of time equal to a multiple of the period of time between successive supplies of the scan line activation signals, so that during said extended period, different desired voltage levels are applied to the data lines, and that for a period after this extended period a corrective voltage level is applied to the data lines, so that over the extended period and the subsequent period an approximately constant effective value voltage is applied to at least some of the data lines. .