JP3683973B2 - Display device - Google Patents

Description

とする。
【００４１】
時刻ｔ＝０のとき、対向電極Ｐの電位ＶLCがＥであったとする。対向電極Ｐの電位ＶLCは、
【００４２】
【数２】

接続点Ｓの電位ＶCDは、
【００４３】
【数３】

と表される。また、電荷転送時におけるスイッチＳＷ３及びインダクタＬを流れる電流ｉ（ｔ）は、
【００４４】
【数４】

と表される。ｉ（ｔ）＝０となったとき、対向電極容量ＣLCD から電荷保存用キャパシタＣD への電荷転送が終了する。このとき、
【００４５】
【数５】

であるから、
【００４６】
【数６】

のときに電荷転送が終了する。
【００４７】
図４は、スイッチＳＷ３がオンの状態における対向電極Ｐの電位ＶLC（ｔ）、接続点Ｓの電位ＶCD（ｔ）、電流ｉ（ｔ）の変化を示すグラフである。
【００４８】
ｎ＝１のとき、
【００４９】
【数７】

となり、制御信号φ３のＨＩＧＨレベル期間がこのｔと等しければ、スイッチＳＷ３のオン期間に電荷が完全に転送される。
【００５０】
一例として、
スイッチＳＷ３のオン抵抗Ｒ＝０Ω
対向電極容量ＣLCD の容量＝電荷保存用キャパシタＣD の容量＝３００ｎＦ
インダクタＬのインダクタンス＝２．７μＨ
とすると、
制御信号φ３のＨＩＧＨレベル期間＝２．００μｓｅｃ
となる。このとき、
ｉ（ｔ）＝０
ＶLC（ｔ）＝０
ＶCD（ｔ）＝Ｅ
となり、電荷はすべて対向電極容量ＣLCD から電荷保存用キャパシタＣD に転送される。同様に、電荷保存用キャパシタＣD から対向電極容量ＣLCD に電荷を戻すときも損失はなく、対向電極Ｐの電位は再びＥに戻る。
【００５１】
１走査線時間を３０μｓｅｃとしても、電荷転送時間は微小時間であるため、対向電極Ｐの電位ＶLC（ｔ）の変位はほぼ方形波として表されるため、対向電極Ｐには略方形波電位が与えられることになる。
【００５２】
スイッチＳＷ３のオン抵抗Ｒ＝０の場合は電荷損失がないので、電荷転送後の接続点Ｓの電位ＶCDはＥとなり、再び対向電極容量ＣLCD に電荷を戻した後の対向電極Ｐの電位ＶLCもＥとなる。従って、この場合は補正電圧を得るための外部からの電荷の供給は不要であり、対向電極Ｐの電位ＶLC（ｔ）は、０ＶとＥとをとる方形波となる。
【００５３】
しかしながら、通常は、電荷の損失が生ずる。例えば、
スイッチＳＷ３のオン抵抗Ｒ＝１Ω
とすると、
ｔ＝制御信号φ３のＨＩＧＨレベル期間＝２．０１μｓｅｃ
となり、対向電極容量ＣLCD から電荷保存用キャパシタＣD に電荷転送の際、対向電極容量ＣLCD に蓄えられていた電荷の一部は抵抗で消費され、接続点Ｓの電位ＶCDは、
ＶCD（ｔ）＝０．８４Ｅ
となる。従って、再度電荷保存用キャパシタＣD の電荷を対向電極容量ＣLCD に戻した後の対向電極Ｐの電位ＶLCは、
ＶLC（ｔ）＝０．７１Ｅ
となる。
【００５４】
そこで、電荷転送後、損失した電荷と同等の電荷を外部から補充し、対向電極Ｐの電位ＶLCの電位をＥとする。従って、消費電力を低減するためには、スイッチＳＷ３のオン抵抗を可能な限り小さくする必要がある。
【００５５】
スイッチＳＷ３のオン期間、即ち、制御信号φ３のＨＩＧＨレベル期間は、適当な時間より短ければ電荷転送が途中で終わり、長ければ一旦転送された電荷が再び逆に戻される。従って、制御信号φ３のＨＩＧＨレベル期間は、正確に設定する必要がある。
【００５６】
図５は、制御信号φ１、φ２、φ３を生成する回路の一例の回路構成図、図６は、図５の回路における極性切換パルスＨｐ、制御信号φ１、φ２、φ３のタイミングチャートである。
【００５７】
外部から極性切換パルス（例えば、水平同期パルス）Ｈｐがモノスティブル・マルチバイブレータ３１とフリップフロップ３２とのノードＴにそれぞれ入力される。モノスティブル・マルチバイブレータ３１は出力信号を制御する可変抵抗Ｒ１及びキャパシタＣ１を備えている。モノスティブル・マルチバイブレータ３１のノードＱ１からは制御信号φ３が出力され、フリップフロップ３２のノードＱ２、／Ｑ２からは極性切換パルスＨｐに同期した切換パルスが出力される。モノスティブル・マルチバイブレータ３１のノード／Ｑ１の出力とフリップフロップ３２のノードＱ２の出力とからＡＮＤ回路３３を介して制御信号φ１が生成され、さらに、モノスティブル・マルチバイブレータ３１のノード／Ｑ１の出力とフリップフロップ３２のノード／Ｑ２の出力とからＡＮＤ回路３４を介して制御信号φ２が生成される。モノスティブル・マルチバイブレータ３１及びフリップフロップ３２は、図６に示すような各パルス信号が生成されるように構成されたものであればよい。制御信号φ３のＨＩＧＨレベル期間は、モノスティブル・マルチバイブレータ３１の可変抵抗Ｒ１及びキャパシタＣ１によって設定する。
【００５８】
図７は、本発明の第２の実施の形態に係る表示装置における対向電極駆動回路の回路構成図である。
【００５９】
図１と同様に、点Ｐは対向電極を示し、ＶLCは対向電極の電位、ＣLCD は対向電極の容量である。対向電極Ｐはそれ自体の容量ＣLCD を介して接地された状態となっており、対向電極ＰにはスイッチＳＷ１及びインダクタＬの一端が接続されている。スイッチＳＷ１は、制御信号φ１によって電位点Ｖ１との接続が制御され、制御信号φ２によって電位点Ｖ２との接続が制御される。したがって、第１の実施の形態と同様に、対向電極Ｐの電位ＶLCはスイッチＳＷ１によって制御され、ここでは、周期Ｔで電位Ｖ１と電位Ｖ２（０Ｖ）とに切り換えるものとする。インダクタＬの他端（点Ｔ）には、スイッチＳＷ２及びＳＷ３が接続される。スイッチＳＷ２は、制御信号φ３によってダイオードＤ１のアノードとの接続が制御され、スイッチＳＷ３は、制御信号φ４によってダイオードＤ２のカソードとの接続が制御される。ダイオードＤ１のカソードとダイオードＤ２のアノードとは、接続点Ｓにおいて接続される。接続点Ｓには電荷保存用キャパシタＣD の一方側が接続され、電荷保存用キャパシタＣD の他方側は接地されている。接続点Ｓの電位はＶCDである。
【００６０】
第１の実施の形態においては、上述のように、制御信号φ３のＨＩＧＨレベル期間を正確に設定する必要があったが、第２の実施の形態においては、以下に説明するように正確な時間の設定は要求されない。
【００６１】
図８は、本発明の第２の実施の形態に係る表示装置における対向電極駆動回路のタイミングチャートである。
【００６２】
時刻ｔ０において、スイッチＳＷ１は制御信号φ１により電位点Ｖ１に接続され、対向電極Ｐの電位ＶLCはＶ１となり、対向電極容量ＣLCD に電荷Ｑ２（＝ＣLCD ×Ｖ１）が蓄積される。
【００６３】
ある期間経過後、時刻ｔ１において、制御信号φ１がＬＯＷレベルとなり、スイッチＳＷ１はオフとなると同時に（瞬時後）制御信号φ３がＨＩＧＨレベルとなり、スイッチＳＷ２がオンとなると、対向電極容量ＣLCD に蓄積されていた電荷Ｑ２は電荷転送用インダクタＬ、スイッチＳＷ２、ダイオードＤ１を介して電荷保存用キャパシタＣD に転送され、対向電極Ｐの電位ＶLCはＶ１から低下していく。電荷転送終了時には、インダクタＬを流れる電流ｉ（ｔ）＝０となり、以後、ダイオードＤ１の存在により、スイッチＳＷ２が接続されたままの状態であっても、電荷保存用キャパシタＣD から対向電極容量ＣLCD への電荷の逆流が起こることはなく、転送された電荷Ｑ２は電荷保存用キャパシタＣD に保存される。
【００６４】
電荷転送終了後の時刻ｔ２において、制御信号φ３がＬＯＷレベルとなり、スイッチＳＷ２がオフとなる。電荷転送終了後のこの時点で対向電極Ｐの電位ＶLCはＶ２’（Ｖ２’はほぼ０Ｖ、即ち、Ｖ２’の値はＶ２の値にほぼ等しい値）となる。同時に（瞬時後）、制御信号φ２がＨＩＧＨレベルとなり、スイッチＳＷ１が電位点Ｖ２に接続され、対向電極容量ＣLCD は対向電極Ｐの電位ＶLCがＶ２となるまで放電される。この後、一定期間が経過して時刻ｔ３となるまで、対向電極Ｐの電位ＶLCはＶ２に保持されるが、第１の実施の形態と同様に、時刻ｔ３直前のある程度の期間、対向電極Ｐの電位ＶLCがＶ２に保持されていることは、特に液晶表示装置における画素への書込み動作が正常に行われるために重要な点である。
【００６５】
一定期間経過後、時刻ｔ３において、制御信号φ２はＬＯＷレベルとなり、スイッチＳＷ１はオフとなる。同時に、制御信号φ４はＨＩＧＨレベルとなってスイッチＳＷ３がオンとなり、電荷保存用キャパシタＣD に保存されていた電荷Ｑ２がダイオードＤ２、スイッチＳＷ３、電荷転送用インダクタＬを介して対向電極容量ＣLCD に転送され、対向電極Ｐの電位ＶLCはＶ２から上昇していく。但し、電荷Ｑ２は、スイッチやリーク電流等によって損失を生じていることもあり得る。
【００６６】
電荷転送終了後の時刻ｔ４において、制御信号φ４はＬＯＷレベルとなり、スイッチＳＷ３は再びオフとなる。このときの対向電極Ｐの電位ＶLCは、電荷の損失等によりＶ１’となる（｜Ｖ１’｜≦｜Ｖ１｜）。同時に（瞬時後）、制御信号φ１がＨＩＧＨレベルとなり、スイッチＳＷ１が電位点Ｖ１側に接続され、対向電極Ｐの電位ＶLCはＶ１となる。この後、一定期間が経過して時刻ｔ５となるまで、対向電極Ｐの電位ＶLCはＶ１に保持されるが、時刻ｔ５直前のある程度の期間、対向電極Ｐの電位ＶLCがＶ１に保持されていることは、上記時刻ｔ３直前のある程度の期間と同様、特に液晶表示装置における画素への書込み動作が正常に行われるために重要な点である。
【００６７】
時刻ｔ５からは、時刻ｔ１からと同様の動作が繰り返される。以下、上記動作を繰り返すことにより、対向電極Ｐの電位ＶLCは周期ＴごとにＶ１とＶ２とに交互に切り換えられる。
【００６８】
第２の実施の形態では、対向電極Ｐ、接続点Ｓの変位は第１の実施の形態と同様であり、また、対向電極容量ＣLCD の電荷の充放電の大部分は電荷保存用キャパシタＣD によって行われ、新たに電位点Ｖ１又はＶ２から供給される電荷は、補正電圧（Ｖ１−Ｖ１’又はＶ２−Ｖ２’）を得るために必要な電荷のみであるため、対向電極Ｐの電圧切換に要する消費電力は非常に小さい点も同様である。しかしながら、制御信号φ３、φ４のＨＩＧＨ期間の終期は電荷転送終了後であれば、電荷転送終了と同時でなくても良く、厳密な設定が要求されない一方、電荷転送は確実に行うことができる。
【００６９】
例えば、
スイッチＳＷ２及びＳＷ３のオン抵抗＝０Ω
対向電極容量ＣLCD の容量＝電荷保存用キャパシタＣD の容量＝３００ｎＦ
インダクタＬのインダクタンス＝２．７μＨ
とすると、制御信号φ３、φ４のＨＩＧＨレベル期間は、
制御信号φ３、φ４のＨＩＧＨレベル期間≧２．００μｓｅｃ
を満たすように設定すれば良く、回路設計が容易である。
【００７０】
図９は、本発明の第３の実施の形態に係る表示装置における対向電極駆動回路の回路構成図である。
【００７１】
第３の実施の形態の構成は、図７の第２の実施の形態と比較すると、対向電極Ｐと接続点Ｓとの間の構成のみが異なっており、対向電極容量ＣLCD から電荷保存用キャパシタＣD への電荷転送経路と、電荷保存用キャパシタＣD から対向電極容量ＣLCD への電荷転送経路とを分けて、それぞれ設けた構成となっている。即ち、対向電極容量ＣLCD から電荷保存用キャパシタＣD への電荷転送は、インダクタＬ１、スイッチＳＷ２、ダイオードＤ１を介して行われ、電荷保存用キャパシタＣD から対向電極容量ＣLCD への電荷転送は、インダクタＬ２、スイッチＳＷ３、ダイオードＤ２を介して行われる。
【００７２】
各制御信号φ１、φ２、φ３、φ４による回路動作及び対向電極Ｐの電位ＶLCの変位並びにこの回路を用いることによる効果は、第２の実施の形態と同様である。
【００７３】
図１０は、本発明の第４の実施の形態に係る表示装置における対向電極駆動回路の回路構成図である。
【００７４】
第４の実施の形態の構成は、図１の第１の実施の形態における各スイッチをＭＯＳトランジスタで置き換えた構成である。第１の実施の形態におけるスイッチＳＷ１、ＳＷ３にはいずれもＭＯＳトランジスタスイッチを用いることができるが、第４の実施の形態においては、スイッチＳＷ１の電位点Ｖ１側にＰチャネルトランジスタ、電位点Ｖ２側にＮチャネルトランジスタを用い、スイッチＳＷ３にはＰチャネルトランジスタ及びＮチャネルトランジスタを用いている。スイッチＳＷ１の電位点Ｖ１側のＰチャネルトランジスタは制御信号／φ１、電位点Ｖ１側のＮチャネルトランジスタは制御信号φ２、スイッチＳＷ３のＰチャネルトランジスタ、Ｎチャネルトランジスタは制御信号／φ３、φ３をそれぞれ用いる。回路動作及びこの回路を用いることによる効果は、第１の実施の形態と同様である。
【００７５】
図１１は、本発明の第５の実施の形態に係る表示装置における対向電極駆動回路の回路構成図である。
【００７６】
第５の実施の形態の構成は、図７の第２の実施の形態における各スイッチをＭＯＳトランジスタで置き換えた構成である。第２の実施の形態におけるスイッチＳＷ１、ＳＷ２、ＳＷ３にもいずれもＭＯＳトランジスタスイッチを用いることができ、第５の実施の形態においては、スイッチＳＷ１の電位点Ｖ１側にＰチャネルトランジスタ、電位点Ｖ２側にＮチャネルトランジスタを用い、スイッチＳＷ２、スイッチＳＷ３にはＮチャネルトランジスタをそれぞれ用いている。スイッチＳＷ１の電位点Ｖ１側のＰチャネルトランジスタは制御信号／φ１、電位点Ｖ２側のＮチャネルトランジスタは制御信号φ２、スイッチＳＷ２、スイッチＳＷ３のＮチャネルトランジスタは制御信号φ３、φ４をそれぞれ用いる。回路動作及びこの回路を用いることによる効果は、第２の実施の形態と同様である。
【００７７】
図１２は、本発明の第６の実施の形態に係る表示装置における対向電極駆動回路の回路構成図である。
【００７８】
第６の実施の形態の構成は、図９の第３の実施の形態における各スイッチをＭＯＳトランジスタで置き換えた構成である。第２の実施の形態におけるスイッチＳＷ１、ＳＷ２、ＳＷ３にもいずれもＭＯＳトランジスタスイッチを用いることができ、第６の実施の形態においては、スイッチＳＷ１の電位点Ｖ１側、電位点Ｖ２側、スイッチＳＷ２、スイッチＳＷ３にＰチャネルトランジスタ及びＮチャネルトランジスタをそれぞれ用いている。スイッチＳＷ１の電位点Ｖ１側のＰチャネルトランジスタ及びＮチャネルトランジスタは制御信号／φ１及びφ１、電位点Ｖ２側のＰチャネルトランジスタ及びＮチャネルトランジスタは制御信号／φ２及びφ２、スイッチＳＷ２、スイッチＳＷ３のＰチャネルトランジスタ及びＮチャネルトランジスタは制御信号／φ３及びφ３、制御信号／φ４及びφ４をそれぞれ用いる。回路動作及びこの回路を用いることによる効果は、第３の実施の形態と同様である。
【００７９】
図１３は、本発明の第７の実施の形態に係る表示装置における対向電極駆動回路の回路構成図である。
【００８０】
第７の実施の形態の構成は、図１の第１の実施の形態と比較すると、電荷転送時における電荷損失の補償箇所を２箇所設けた構成となっている。即ち、対向電極Ｐのみならず、接続点Ｓにも電荷損失の補償箇所を設けている。接続点ＳにはスイッチＳＷ５が設けられ、スイッチＳＷ５は、制御信号φ１によって電位点Ｖ２との接続が制御され、制御信号φ２によって電位点Ｖ１との接続が制御される。その他は、第１の実施の形態と同様の構成である。
【００８１】
図１４は、本発明の第７の実施の形態に係る表示装置における対向電極駆動回路のタイミングチャートである。
【００８２】
第７の実施の形態の回路構成における回路動作については、第１の実施の形態と異なる点について説明する。対向電極容量ＣLCD から電荷保存用キャパシタＣD への電荷転送後、対向電極容量ＣLCD がスイッチＳＷ１により電位Ｖ２まで放電される点は同様であるが、この時同時に、電荷保存用キャパシタＣD がスイッチＳＷ５により電位Ｖ１まで充電される点で異なる。また、電荷保存用キャパシタＣD から対向電極容量ＣLCD への電荷転送後、対向電極容量ＣLCD がスイッチＳＷ１により電位Ｖ１まで充電される点は同様であるが、この時同時に、電荷保存用キャパシタＣD がスイッチＳＷ５により電位Ｖ２まで放電される点で異なる。
【００８３】
電荷転送時における電荷損失の補償箇所を２箇所設けたことにより、電荷損失の補償をより短時間で行うことができる。
【００８４】
図１５は、本発明の第８の実施の形態に係る表示装置における対向電極駆動回路の回路構成図である。
【００８５】
本発明の第８の実施の形態の構成は、図１の第１の実施の形態と比較すると、対向電極Ｐの電位ＶLCの安定化を図るため、対向電極Ｐに付加容量ＣH を併設した点のみ異なっている。ここでは、電荷保存用キャパシタＣD の容量が、対向電極容量ＣLCD の容量と付加容量ＣH の容量との和となるように各容量を設定するものとする。
【００８６】
以上の各実施の形態は、対向電極Ｐの電位ＶLCを切り換える構成について説明したが、通常、対向電極Ｐの電位ＶLCを切り換えるときは、画素の補助容量の共通電極の電位も切り換える必要があり、画素の補助容量の共通電極の電位の切換についても本発明の各構成を適用することができる。
【００８７】
図１６は、本発明の第９の実施の形態に係る表示装置における対向電極駆動回路の回路構成図である。
【００８８】
対向電極Ｐの電位ＶLCと、画素の補助容量の共通電極の電位とを異なる電圧又はタイミングでそれぞれ切り換える必要があるときは、図１６に示すようにそれぞれ電位切り換え用回路を配設すればよい。対向電極Ｐの電位ＶLCの切換には、電荷保存用キャパシタＣD 、インダクタＬ、スイッチＳＷ１及びＳＷ３から構成される電位切り換え用回路を用い、画素の補助容量の共通電極の電位の切換には、電荷保存用キャパシタＣD ’、インダクタＬ’、スイッチＳＷ１’及びＳＷ３’から構成される電位切り換え用回路を用いる。
【００８９】
図１７は、本発明の第１０の実施の形態に係る表示装置におけるデータ線基準電位供給回路の回路構成図である。
【００９０】
第１０の実施の形態の構成は、データ線駆動回路はディジタル回路で構成されている場合において、データ線に与える基準電位を切り換える必要のある場合に本発明の構成を適用した例である。
【００９１】
画像データＤＡＴＡ及びクロック信号ＣＬＯＣＫが入力されるシフトレジスタ及びデータ回路と、シフトレジスタ及びデータ回路にスイッチＳＷ１、ＳＷ２、ＳＷ３、ＳＷ４をそれぞれ介して接続されるデータ線駆動出力ノードＱ１と、データ線駆動出力ノードＱ１同様のデータ線駆動出力ノードＱ２、．．．、Ｑｎと、スイッチＳＷ１、ＳＷ２、ＳＷ３、ＳＷ４にそれぞれ接続され、電位Ｖ１とＶ１’、電位Ｖ２とＶ２’、電位Ｖ３とＶ３’、電位Ｖ４とＶ４’をそれぞれ切り換えるスイッチＳＷ１’、ＳＷ２’、ＳＷ３’、ＳＷ４’とから構成されている。スイッチＳＷ１とＳＷ１’との間、スイッチＳＷ２とＳＷ２’との間、スイッチＳＷ３とＳＷ３’との間、スイッチＳＷ４とＳＷ４’との間にそれぞれ示されている容量Ｃ1 、Ｃ2 、Ｃ3 、Ｃ4 は、それぞれ基準電位供給線の容量であり、その外部基準電位はそれぞれＶref1、Ｖref2、Ｖref3、Ｖref4である。
【００９２】
画像データＤＡＴＡの入力に応じクロック信号ＣＬＯＣＫに同期して、外部基準電位Ｖref1、Ｖref2、Ｖref3、Ｖref4が、スイッチＳＷ１〜４の切り換えによりデータ線駆動出力ノードＱ１、Ｑ２、．．．、Ｑｎに出力される。
【００９３】
図１８は、第１０の実施の形態におけるデータ線基準電位供給回路の回路構成図である。
【００９４】
外部基準電位Ｖref1を供給するデータ線基準電位供給回路は、電位Ｖ１とＶ１’とを制御信号φ１とφ２とで切り換えるスイッチＳＷ１と、一端がスイッチＳＷ１に接続され、他端が制御信号φ３で制御されるスイッチＳＷ２の一端に接続されたインダクタＬと、一方側がスイッチＳＷ２の他端に接続され、他方側が接地された外部キャパシタＣD と、一方側がスイッチＳＷ１及びインダクタＬの一端に接続され、他方側が接地された基準電位供給線の容量Ｃ1 とから構成されている。外部基準電位Ｖref2、Ｖref3、Ｖref4を供給するデータ線基準電位供給回路も同様の構成である。
【００９５】
基準電位を１走査線期間又は１フレーム期間ごとに切り換える場合、このデータ線基準電位供給回路は、例えば、ある期間は外部基準電位Ｖref1として電位Ｖ１を供給し、その次の期間は外部基準電位Ｖref1として電位Ｖ１’を供給する。具体的な回路動作は、図１の第１の実施の形態と同様であり、基準電位供給線の容量Ｃ1 に蓄えられた電荷を外部キャパシタＣD に転送して保存することにより、外部基準電位Ｖref1を切り換える。
【００９６】
この場合においても、非常に小さい消費電力で外部基準電位を切り換えることができる。
【００９９】
【発明の効果】
本発明の実施の一形態に係る表示装置によれば、複数の信号線と複数の走査線との交差部に、信号線及び走査線に接続されてそれぞれ配設されたスイッチング素子と、スイッチング素子のそれぞれに接続されて配設され、走査線への走査信号入力に応じてスイッチング素子を介して信号線からの信号が印加される画素電極と、画素電極と画素電極に対向する対向電極との間に挟持され、画素電極と対向電極との間の印加電圧により駆動される液晶分子を含む液晶層と、一方側は各画素電極に対してそれぞれ配設され接続された電極であり、他方側は各電極に共通して対応し配設された共通電極である補助キャパシタと、共通電極にインダクタを介して併設され、共通電極に蓄えられた電荷を共通電極との間でインダクタを介して相互に転送され又は転送することにより共通電極の電位を所定周期で変位させる電荷保存用キャパシタとを備えたので、チップサイズが小さく、耐電圧が低い安価なＬＳＩで駆動可能で、消費電力が小さく、かつ、高品質表示が可能な表示装置を提供することができる。
【０１００】
本発明の実施の一形態に係る表示装置の上記構成において、共通電極と電荷保存用キャパシタとの間の電荷転送によって損失した分の電荷を、電荷転送終了後に補充することとしたので、対向電極の電位を正確に制御することができる。
【０１０１】
本発明の他の実施の形態に係る表示装置によれば、２以上の基準電位のうち、制御信号に応じてそれぞれ選択された所定基準電位がそれぞれ基準電位供給線を介して与えられる複数の信号線と、複数の信号線と複数の走査線との交差部に、信号線及び走査線に接続されてそれぞれ配設されたスイッチング素子と、スイッチング素子のそれぞれに接続されて配設され、走査線への走査信号入力に応じてスイッチング素子を介して信号線からの信号が印加される画素電極と、画素電極と画素電極に対向する対向電極との間に挟持され、画素電極と対向電極との間の印加電圧により駆動される液晶分子を含む液晶層と、各基準電位供給線に付加された各基準電位供給線容量にインダクタを介してそれぞれ併設され、各基準電位供給線容量に蓄えられた電荷を各基準電位供給線容量との間で各インダクタを介して相互に転送され又は転送することにより所定基準電位を所定周期で変位させる電荷保存用キャパシタとを備えたので、チップサイズが小さく、耐電圧が低い安価なＬＳＩで駆動可能で、消費電力が小さく、かつ、高品質表示が可能な表示装置を提供することができる。
【０１０２】
本発明の他の実施の形態に係る表示装置の上記構成において、基準電位供給線容量と電荷保存用キャパシタとの間の電荷転送によって損失した分の電荷を、電荷転送終了後に補充することとしたので、対向電極の電位を正確に制御することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態に係る表示装置における対向電極駆動回路の回路構成図。
【図２】本発明の第１の実施の形態に係る表示装置における対向電極駆動回路のタイミングチャート。
【図３】対向電極容量ＣLCD から電荷保存用キャパシタＣD への電荷転送時における第１の実施の形態に係る対向電極駆動回路の等価回路の回路構成図。
【図４】第１の実施の形態に係る対向電極駆動回路のスイッチＳＷ３がオンの状態における対向電極Ｐの電位ＶLC（ｔ）、接続点Ｓの電位ＶCD（ｔ）、電流ｉ（ｔ）の変化を示すグラフ。
【図５】第１の実施の形態に係る対向電極駆動回路の制御信号φ１、φ２、φ３を生成する回路の一例の回路構成図。
【図６】図５の回路における極性切換パルスＨｐ、制御信号φ１、φ２、φ３のタイミングチャート。
【図７】本発明の第２の実施の形態に係る表示装置における対向電極駆動回路の回路構成図。
【図８】本発明の第２の実施の形態に係る表示装置における対向電極駆動回路のタイミングチャートである。
【図９】本発明の第３の実施の形態に係る表示装置における対向電極駆動回路の回路構成図。
【図１０】本発明の第４の実施の形態に係る表示装置における対向電極駆動回路の回路構成図。
【図１１】本発明の第５の実施の形態に係る表示装置における対向電極駆動回路の回路構成図。
【図１２】本発明の第６の実施の形態に係る表示装置における対向電極駆動回路の回路構成図。
【図１３】本発明の第７の実施の形態に係る表示装置における対向電極駆動回路の回路構成図。
【図１４】本発明の第７の実施の形態に係る表示装置における対向電極駆動回路のタイミングチャート。
【図１５】本発明の第８の実施の形態に係る表示装置における対向電極駆動回路の回路構成図。
【図１６】本発明の第９の実施の形態に係る表示装置における対向電極駆動回路の回路構成図。
【図１７】本発明の第１０の実施の形態に係る表示装置におけるデータ線基準電位供給回路の回路構成図。
【図１８】第１０の実施の形態におけるデータ線基準電位供給回路の回路構成図。
【図１９】アレイ基板の概略構成図。
【図２０】液晶表示装置の画素部の断面構造を模式的に表した説明図。
【符号の説明】
１９０１ ＴＦＴ
１９０２ 補助容量
１９０３ 液晶容量ＣL
１９０４ データ線駆動回路
１９０５ ゲート線駆動回路
１９０６ 対向電極
１９０７ データ線
１９０８ ゲート線
１９０９ 画素
２００１、２０１０ ガラス基板
２００２ カラーフィルタ
２００３ ブラックマトリクス
２００４、２０１５ 保護膜
２００５ 対向電極
２００６、２０１６ 配向膜
２００７ 液晶層
２０１１ ゲート電極
２０１２ ゲート絶縁膜
２０１３ アモルファスシリコン
２０１４ 画素電極
２０１７ ソース電極
２０１８ ドレイン電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device, and more particularly to a drive circuit for an active matrix liquid crystal display device.
[0002]
[Prior art]
As a thin, lightweight, low power consumption, high-quality display device, a liquid crystal display device (TFT-LCD) using a TFT (thin film transistor) is widely used in personal computers, TVs, game machines and the like. In TFT-LCD, a liquid crystal material is usually sealed in a liquid crystal cell composed of an array substrate on which pixels are arranged and a counter substrate on which a color filter is formed, and a polarizing plate is disposed on the outside of both substrates. The illumination is applied from the back side.
[0003]
FIG. 19 is a schematic configuration diagram of an array substrate. Each pixel 1909 is provided with a TFT 1901 for signal sampling, an auxiliary capacitor CS 1902 for holding voltage, and the like.
[0004]
FIG. 20 is an explanatory diagram schematically showing a cross-sectional structure of a pixel portion of a liquid crystal display device. The counter substrate includes a color filter 2002 and a black matrix 2003 formed on the glass substrate 2001, a protective film 2004, a counter electrode 2005, an alignment film 2006, and the like sequentially formed thereon. On the other hand, the array substrate is formed of TFTs and pixels formed on the glass substrate 2010, a protective film 2015, an alignment film 2016, and the like sequentially formed so as to cover them. The TFT includes a gate electrode 2011, a gate insulating film 2012, amorphous silicon 2013, a source electrode 2017, a drain electrode 2018, and the like. In addition, the pixel includes a pixel electrode 2014 formed on the gate insulating film 2012. The liquid crystal cell has a configuration in which two substrates are opposed so that the alignment film 2006 on the counter substrate and the alignment film 2016 on the array substrate are opposed to each other, and the liquid crystal layer 2007 is sandwiched between the substrates. .
[0005]
Referring back to FIG. 19, each TFT 1901 is controlled by a data line driver circuit 1904 and a gate line driver circuit 1905 via a data line 1907 and a gate line 1908. Reference numeral 1903 indicates a liquid crystal capacitance CL per pixel. Since the liquid crystal may be deteriorated in characteristics due to a decrease in polarization or the like when the application of a DC voltage is continued or repeated, normally, the liquid crystal display device needs to be AC driven and is driven as follows.
[0006]
When a signal voltage is supplied from the data line driver circuit 1904 and the gate of the TFT is opened by the gate line driver circuit 1905, writing to the pixel 1909 is performed by the signal voltage. This signal voltage is held by the auxiliary capacitor CS 1902 and the liquid crystal capacitor CL 1903 until the next writing is performed. On the other hand, a constant voltage is applied to the counter electrode 1906. Therefore, for example, when the potential of the counter electrode 1906 is 0 V, the potential of the pixel 1909 is +3 V for a certain period (for example, one frame time), and when the potential of the pixel 1909 is −3 V for the next certain period, the liquid crystal layer An AC voltage of ± 3V is applied.
[0007]
In the form in which the polarity of the entire screen is changed as an AC voltage application form, image quality deterioration due to flicker occurs. Therefore, there is a method of inverting the polarity for each scanning line and sequentially changing the polarity of each scanning line. is there. That is, when writing data in a certain frame, voltage is applied to each scanning line so that a positive voltage is applied to a certain scanning line and a negative voltage is applied to a scanning line adjacent to the scanning line, The voltage application at the time of data writing in the next frame is performed so that the polarity of the applied voltage to each scanning line is opposite to the polarity of the applied voltage in the immediately preceding frame. Even in this case, the potential of the counter electrode (common electrode) is kept constant. In this way, a driving method in which the potential of the counter electrode is held constant, and the voltage application is performed by switching the polarity of the signal voltage with respect to the potential of the counter electrode at regular intervals is referred to as a common constant driving method. . This common constant driving method has an advantage that the power consumption of the counter electrode is small because the counter electrode only needs to be held at a constant potential.
[0008]
However, in current liquid crystal display devices, voltage control of about ± 5 V is required to control transmission / non-transmission of the liquid crystal layer or display a bright / dark state. The control voltage requires an amplitude of 10V. Further, a higher voltage is required for the control voltage of the gate line driving circuit. Although the data line driving circuit is constituted by an LSI, the current power supply voltage of a normal LSI is 5 V or less, and a signal having a voltage of 10 V cannot be handled. Therefore, development of an LSI with a high withstand voltage is required. As a result, the chip size increases and the product unit price also increases. Furthermore, it is necessary to prepare a high-voltage power supply circuit, and the power consumption increases because the signal amplitude is large. Therefore, it is disadvantageous in responding to requests for downsizing and low power consumption of the drive circuit.
[0009]
In the common constant drive method, a drive method has been proposed in which the LSI power supply voltage is changed for each frame to obtain a data signal voltage having a substantially 10 V amplitude with a 5 V power supply voltage. Since it is necessary to change it, a circuit for that purpose is required, and since the amplitude of the data signal voltage is large, the power consumption reduction effect is small.
[0010]
In order to solve the above inconvenience, a driving method called a common inversion driving method has been proposed in which the potential of the counter electrode is inverted (or displaced) at regular intervals. According to the common inversion driving method, the amplitude of the control voltage of the data line driving circuit is reduced to ½ that of the common constant driving method by displacing the potential of the counter electrode every scanning line time or one frame time. Can be made. For example, when the potential of the counter electrode is 5 V in the scanning line period at the time of data writing of a certain frame, and the signal voltage of 2 V is supplied to the data line and the potential of the pixel electrode is 2 V, the liquid crystal layer has −3 V A voltage is applied. On the other hand, when the potential of the counter electrode is set to 0 V and a signal voltage of 3 V is supplied to the data line and the potential of the pixel electrode is set to 3 V in the same scanning line period at the time of data writing in the next frame, +3 V is applied to the liquid crystal layer. Is applied. Accordingly, an AC voltage of ± 3 V is applied to the liquid crystal layer. Thus, by displacing the potential of the counter electrode for each scanning line, the amplitude of the control voltage of the data line driving circuit can be halved compared to the common constant driving method. In addition, the data line driving LSI need only have a low withstand voltage, and the chip size can be reduced, so that the unit price of the product can be reduced.
[0011]
[Problems to be solved by the invention]
However, in the common inversion driving method, it is necessary to displace the potential of the counter electrode at regular intervals (every one scanning line or every frame). Since the counter electrode has a large capacity, power consumption for driving the counter electrode is large. There is a problem of increasing. Further, normally, the common electrode of the auxiliary capacitor CS needs to be driven in the same manner as the counter electrode, so that the power consumption is larger.
[0012]
On the other hand, in the above-described common constant driving method, the data line driving circuit must output a data signal voltage having a larger amplitude than the normal power supply voltage. Will increase. In addition, an LSI with a high withstand voltage is required and the chip size is increased, resulting in an increase in product unit price.
[0013]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a display that can be driven by an inexpensive LSI with a small chip size and low withstand voltage, low power consumption, and high-quality display. Is to provide a device.
[0018]
[Means for Solving the Problems]
According to the display device according to the embodiment of the present invention,
Switching elements respectively connected to the signal lines and the scanning lines at intersections of the plurality of signal lines and the plurality of scanning lines;
A pixel electrode connected to each of the switching elements, to which a signal from the signal line is applied via the switching element in response to a scanning signal input to the scanning line;
A liquid crystal layer including liquid crystal molecules sandwiched between a pixel electrode and a counter electrode facing the pixel electrode and driven by an applied voltage between the pixel electrode and the counter electrode;
One side is an electrode arranged and connected to each pixel electrode, and the other side is an auxiliary capacitor that is a common electrode arranged correspondingly to each electrode,
For storage of electric charge, which is installed in the common electrode through an inductor, and the electric charge stored in the common electrode is transferred to or from the common electrode through the inductor, thereby displacing the electric potential of the common electrode at a predetermined cycle. With a capacitor,
With this configuration, it is possible to provide a display device that can be driven by an inexpensive LSI having a small chip size and low withstand voltage, low power consumption, and high-quality display.
[0019]
In the above structure of the display device according to the embodiment of the present invention, the common electrode is held at the first predetermined potential for the first predetermined period, and the first writing operation is performed by applying a signal to each pixel electrode. The charge stored in the common electrode is transferred to the charge storage capacitor, the common electrode is held at the second predetermined potential for a second predetermined period, a second write operation is performed by applying a signal to each pixel electrode, and then The charge stored in the charge storage capacitor is transferred to the common electrode, the common electrode is held at the first predetermined potential for a third predetermined period, and a first write operation is performed by applying a signal to each pixel electrode. Since the second or first writing operation for each pixel electrode is sequentially performed for each scanning line while the potential of the common electrode is held at the second or first predetermined potential for each predetermined period of time, the chip size is reduced. Inexpensive with low withstand voltage Drivable in LSI, the power consumption is small and can provide a high quality display can display.
[0020]
Alternatively, in the above structure of the display device according to the embodiment of the present invention, the common electrode is held at the first predetermined potential for the first predetermined period and the switching element connected to the first scanning line A first writing operation is performed by applying a signal to the pixel electrode connected to the switching element, and then the charge stored in the common electrode is transferred to the charge storage capacitor, and the common electrode is set to the second predetermined period for a second predetermined period. The second writing operation is performed by applying a signal to the pixel electrode connected to the switching element via the switching element connected to the second scanning line, and then stored in the charge storage capacitor. The charge is transferred to the common electrode, the common electrode is held at the first predetermined potential for a third predetermined period, and is connected to the switching element via the switching element connected to the third scanning line. The first address operation is performed by applying a signal to the pixel electrode, and the second or first address operation is performed on the pixel electrode while holding the potential of the common electrode at the second or first predetermined potential for each predetermined period after the signal is applied. Since the scanning is performed sequentially for each scanning line, it is possible to provide a display device that can be driven by an inexpensive LSI with a small chip size and low withstand voltage, low power consumption, and high-quality display.
[0021]
In each of the above-described configurations of the display device according to the embodiment of the present invention, the charge lost by the charge transfer between the common electrode and the charge storage capacitor is supplemented after the charge transfer is completed. The potential of the electrode can be accurately controlled.
[0022]
According to the display device according to another embodiment of the present invention,
A plurality of signal lines each of which is supplied with a predetermined reference potential selected in accordance with a control signal among the two or more reference potentials via a reference potential supply line;
Switching elements respectively connected to the signal lines and the scanning lines at intersections of the plurality of signal lines and the plurality of scanning lines;
A pixel electrode connected to each of the switching elements, to which a signal from the signal line is applied via the switching element in response to a scanning signal input to the scanning line;
A liquid crystal layer including liquid crystal molecules sandwiched between a pixel electrode and a counter electrode facing the pixel electrode and driven by an applied voltage between the pixel electrode and the counter electrode;
Each reference potential supply line capacity added to each reference potential supply line is provided via an inductor, and the charge stored in each reference potential supply line capacity is connected to each reference potential supply line capacity via each inductor. And a charge storage capacitor that displaces a predetermined reference potential in a predetermined cycle by being transferred to each other or transferred,
With this configuration, it is possible to provide a display device that can be driven by an inexpensive LSI having a small chip size and low withstand voltage, low power consumption, and high-quality display.
[0023]
In the above-described configuration of the display device according to another embodiment of the present invention, the first writing operation is performed by holding the reference potential supply line for the first predetermined period at the first predetermined reference potential and applying a signal to each pixel electrode. Next, the charge stored in the reference potential supply line capacitance is transferred to the charge storage capacitor, the reference potential supply line is held at the second predetermined reference potential for a second predetermined period, and a signal is applied to each pixel electrode. And then, the charge stored in the charge storage capacitor is transferred to the reference potential supply line capacitance, and the reference potential supply line is held at the first predetermined reference potential for a third predetermined period. A first write operation is performed by applying a signal to the pixel electrode, and the second or first address for each pixel electrode is held while holding the potential of the reference potential supply line at each second predetermined period for a predetermined period thereafter. Write operation for each scan line Since it was decided to perform the following, small chip size, drivable in withstand voltage is low inexpensive LSI, it has developed the power consumption is small and can provide a high quality display can display.
[0024]
Alternatively, in the above configuration of the display device according to another embodiment of the present invention, the switching element connected to the first scanning line while holding the reference potential supply line for the first predetermined period at the first predetermined reference potential A first write operation is performed by applying a signal to the pixel electrode connected to the switching element via the first and second charges, and then the charge stored in the reference potential supply line capacitor is transferred to the charge storage capacitor for a second predetermined period. The reference potential supply line is held at the second predetermined reference potential, and a second writing operation is performed by applying a signal to the pixel electrode connected to the switching element via the switching element connected to the second scanning line. Then, the charge stored in the charge storage capacitor is transferred to the reference potential supply line capacitance, and the reference potential supply line is held at the first predetermined reference potential for the third predetermined period, and is connected to the third scanning line. The A first write operation is performed by applying a signal to the pixel electrode connected to the switching element via the switching element, and the potential of the reference potential supply line is held at the second or first predetermined reference potential for a predetermined period thereafter. However, since the second or first writing operation on the pixel electrode is sequentially performed for each scanning line, it can be driven by an inexpensive LSI with a small chip size, low withstand voltage, low power consumption, and A display device capable of high-quality display can be provided.
[0025]
In each of the above-described configurations of the display device according to another embodiment of the present invention, the amount of charge lost due to the charge transfer between the reference potential supply line capacitor and the charge storage capacitor is replenished after the charge transfer ends. As a result, the potential of the counter electrode can be accurately controlled.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a display device according to the present invention will be described with reference to the drawings.
[0027]
A feature of the display device according to the present invention is that charges are stored in a capacitor provided in the counter electrode constituting the display unit of the liquid crystal display device or the like, and the potential of the counter electrode is displaced at regular intervals using this charge. It is in. That is, the counter electrode potential is set to a high (HIGH) level for a certain period, and the charge stored at this time is transferred to and stored in the capacitor along with the inductor, and the counter electrode potential is set to a low (LOW) level. After a certain period of time, the charge stored in the capacitor is transferred to the capacitor of the counter electrode via the inductor, and the counter electrode potential is again shifted to the HIGH level. More simply, the electric potential once accumulated in the counter electrode is put into and out of a capacitor provided separately to displace the counter electrode potential. Similarly, when the potential of the common electrode of the auxiliary capacitor CS for voltage storage is displaced, the storage of charges in the capacitor is also used. In practice, it is difficult to completely store the charge, and loss occurs during charge transfer. Therefore, when the counter electrode potential is displaced, after the charge transfer, only the charge corresponding to the lost charge is supplied from the outside, and the counter electrode potential is set to a predetermined potential.
[0028]
FIG. 1 is a circuit configuration diagram of a counter electrode driving circuit in a display device according to a first embodiment of the present invention.
[0029]
Point P indicates the counter electrode, VLC is the potential of the counter electrode, and CLCD is the capacitance of the counter electrode. The counter electrode P is grounded via its own capacitance CLCD, and switches SW1 and SW3 are connected to the counter electrode P. The connection of the switch SW1 with the potential point V1 is controlled by the control signal φ1, and the connection with the potential point V2 is controlled by the control signal φ2. Therefore, the potential VLC of the counter electrode P is controlled by the switch SW1, and here, the potential VLC is switched between the potential V1 and the potential V2 (0 V) at the period T. On the other hand, the connection of the switch SW3 to one end of the charge transfer inductor L is controlled by the control signal φ3. The other end of the charge transfer inductor L is a connection point S with one side of the charge storage capacitor CD, and the other side of the charge storage capacitor CD is grounded. The potential at the connection point S is VCD.
[0030]
FIG. 2 is a timing chart of the counter electrode driving circuit in the display device according to the first embodiment of the present invention.
[0031]
At time t0, the switch SW1 is connected to the potential point V1 by the control signal φ1, the potential VLC of the counter electrode P becomes V1, and the charge Q1 (= CLCD × V1) is accumulated in the counter electrode capacitor CLCD.
[0032]
After a certain period (one scanning line time, several scanning line times or one frame time, etc.) has passed, at time t1, the control signal φ1 becomes LOW level and the switch SW1 is turned off. At the same time, when the control signal φ3 becomes HIGH level and the switch SW3 is turned on, the charge Q1 stored in the counter electrode capacitor CLCD is transferred to the charge storage capacitor CD via the charge transfer inductor L, and the potential of the counter electrode P VLC decreases from V1.
[0033]
At time t2, all of the charge Q1 is transferred to the charge storage capacitor CD, the control signal φ3 becomes LOW level, and the switch SW3 is turned off. At this time, the potential VLC of the counter electrode P becomes V2 ′ (V2 ′ is approximately 0V, that is, the value of V2 ′ is substantially equal to the value of V2). At the same time (after the moment), the control signal φ2 becomes HIGH level, the switch SW1 is connected to the potential point V2, and the counter electrode capacitor CLCD is discharged until the potential VLC of the counter electrode P becomes V2. Thereafter, the potential VLC of the counter electrode P is held at V2 until a time period elapses until a time t3. However, the potential VLC of the counter electrode P is held at V2 for a certain period immediately before the time t3. This is particularly important for the normal writing operation to the pixels in the liquid crystal display device.
[0034]
After a certain period of time, at time t3, the control signal φ2 becomes LOW level and the switch SW1 is turned off. At the same time, the control signal φ3 becomes HIGH level, the switch SW3 is turned on, and the charge Q1 stored in the charge storage capacitor CD is transferred to the counter electrode capacitor CLCD through the charge transfer inductor L, and the counter electrode P The potential VLC increases from V2. However, the charge Q1 may be lost due to a switch, a leakage current, or the like.
[0035]
After all the charges are transferred, at time t4, the control signal φ3 becomes the LOW level, and the switch SW3 is turned off again. At this time, the potential VLC of the counter electrode P becomes V1 ′ due to charge loss or the like (| V1 ′ | ≦ | V1 |). At the same time (after the moment), the control signal φ1 becomes HIGH level, the switch SW1 is connected to the potential point V1 side, and the potential VLC of the counter electrode P becomes V1. Thereafter, the potential VLC of the counter electrode P is held at V1 until a time period elapses until time t5, but the potential VLC of the counter electrode P is held at V1 for a certain period immediately before time t5. This is important for the normal operation of writing to the pixels in the liquid crystal display device, as in a certain period immediately before the time t3.
[0036]
From time t5, the same operation as from time t0 is repeated. Thereafter, by repeating the above operation, the potential VLC of the counter electrode P is alternately switched between V1 and V2 every period T.
[0037]
Most of the charge / discharge of the charge of the counter electrode capacitor CLCD is performed by the charge storage capacitor CD, and the charge newly supplied from the potential point V1 or V2 is applied with the correction voltage (V1-V1 'or V2-V2'). Since only the electric charge necessary for obtaining is obtained, the power consumption required for switching the potential of the counter electrode P is very small.
[0038]
FIG. 3 is a circuit configuration diagram of an equivalent circuit of the counter electrode driving circuit according to the first embodiment at the time of charge transfer from the counter electrode capacitor CLCD to the charge storage capacitor CD.
[0039]
Based on FIG. 3, the potential VLC of the counter electrode P and the displacement at the time of charge transfer of the potential VCD at the connection point S between the charge storage capacitor CD and the charge transfer inductor L are shown by equations. However, for simplicity of calculation,
Counter electrode capacitance CLCD capacitance = charge storage capacitor CD capacitance = 2C
Inductor L inductance = L
On-resistance of switch SW3 = R
V1 = E
V2 = 0
And Also,
[0040]
[Expression 1]

And
[0041]
It is assumed that the potential VLC of the counter electrode P is E at time t = 0. The potential VLC of the counter electrode P is
[0042]
[Expression 2]

The potential VCD at the connection point S is
[0043]
[Equation 3]

It is expressed. The current i (t) flowing through the switch SW3 and the inductor L during charge transfer is
[0044]
[Expression 4]

It is expressed. When i (t) = 0, the charge transfer from the counter electrode capacitance CLCD to the charge storage capacitor CD is completed. At this time,
[0045]
[Equation 5]

Because
[0046]
[Formula 6]

At this time, the charge transfer ends.
[0047]
FIG. 4 is a graph showing changes in the potential VLC (t) of the counter electrode P, the potential VCD (t) of the connection point S, and the current i (t) when the switch SW3 is on.
[0048]
When n = 1
[0049]
[Expression 7]

If the HIGH level period of the control signal φ3 is equal to this t, the charge is completely transferred during the ON period of the switch SW3.
[0050]
As an example,
On-resistance R of switch SW3 = 0Ω
Counter electrode capacity CLCD capacity = charge storage capacitor CD capacity = 300 nF
Inductance of inductor L = 2.7 μH
Then,
HIGH level period of control signal φ3 = 2.00 μsec
It becomes. At this time,
i (t) = 0
VLC (t) = 0
VCD (t) = E
Thus, all charges are transferred from the counter electrode capacitance CLCD to the charge storage capacitor CD. Similarly, there is no loss when charge is returned from the charge storage capacitor CD to the counter electrode capacitance CLCD, and the potential of the counter electrode P returns to E again.
[0051]
Even if one scanning line time is set to 30 μsec, the charge transfer time is very short, and therefore the displacement of the potential VLC (t) of the counter electrode P is expressed as a substantially square wave. Therefore, the counter electrode P has a substantially square wave potential. Will be given.
[0052]
When the on-resistance R = 0 of the switch SW3, there is no charge loss, so the potential VCD at the connection point S after charge transfer becomes E, and the potential VLC of the counter electrode P after returning the charge to the counter electrode capacitor CLCD again. E. Therefore, in this case, external charge supply for obtaining the correction voltage is not required, and the potential VLC (t) of the counter electrode P is a square wave that takes 0V and E.
[0053]
Usually, however, charge loss occurs. For example,
On-resistance R of switch SW3 = 1Ω
Then,
t = HIGH level period of control signal φ3 = 2.01 μsec
When the charge is transferred from the counter electrode capacitor CLCD to the charge storage capacitor CD, a part of the charge stored in the counter electrode capacitor CLCD is consumed by the resistor, and the potential VCD at the connection point S is
VCD (t) = 0.84E
It becomes. Therefore, the potential VLC of the counter electrode P after returning the charge of the charge storage capacitor CD to the counter electrode capacitance CLCD is
VLC (t) = 0.71E
It becomes.
[0054]
Therefore, after charge transfer, a charge equivalent to the lost charge is replenished from the outside, and the potential VLC of the counter electrode P is set to E. Therefore, in order to reduce power consumption, it is necessary to make the ON resistance of the switch SW3 as small as possible.
[0055]
During the ON period of the switch SW3, that is, the HIGH level period of the control signal φ3, the charge transfer ends in the middle if it is shorter than an appropriate time, and the transferred charge is returned to the reverse again if it is longer. Therefore, it is necessary to accurately set the HIGH level period of the control signal φ3.
[0056]
FIG. 5 is a circuit configuration diagram of an example of a circuit that generates the control signals φ1, φ2, and φ3, and FIG. 6 is a timing chart of the polarity switching pulse Hp and the control signals φ1, φ2, and φ3 in the circuit of FIG.
[0057]
A polarity switching pulse (for example, a horizontal synchronization pulse) Hp is input from the outside to nodes T of the monostable multivibrator 31 and the flip-flop 32, respectively. The monostable multivibrator 31 includes a variable resistor R1 and a capacitor C1 that control an output signal. The control signal φ3 is output from the node Q1 of the monostable multivibrator 31, and the switching pulse synchronized with the polarity switching pulse Hp is output from the nodes Q2 and / Q2 of the flip-flop 32. The control signal φ1 is generated from the output of the node / Q1 of the monostable multivibrator 31 and the output of the node Q2 of the flip-flop 32 via the AND circuit 33. Furthermore, the output of the node / Q1 of the monostable multivibrator 31 and the flip-flop Control signal φ2 is generated via AND circuit 34 from the output of node / Q2 of group 32. The monostable multivibrator 31 and the flip-flop 32 may be configured as long as each pulse signal as shown in FIG. 6 is generated. The HIGH level period of the control signal φ3 is set by the variable resistor R1 and the capacitor C1 of the monostable multivibrator 31.
[0058]
FIG. 7 is a circuit configuration diagram of the counter electrode driving circuit in the display device according to the second embodiment of the present invention.
[0059]
As in FIG. 1, the point P indicates the counter electrode, VLC is the potential of the counter electrode, and CLCD is the capacitance of the counter electrode. The counter electrode P is grounded via its own capacitance CLCD, and the switch SW1 and one end of the inductor L are connected to the counter electrode P. The connection of the switch SW1 with the potential point V1 is controlled by the control signal φ1, and the connection with the potential point V2 is controlled by the control signal φ2. Therefore, as in the first embodiment, the potential VLC of the counter electrode P is controlled by the switch SW1, and here, it is switched between the potential V1 and the potential V2 (0 V) in the cycle T. Switches SW2 and SW3 are connected to the other end (point T) of the inductor L. The switch SW2 is connected to the anode of the diode D1 by the control signal φ3, and the switch SW3 is connected to the cathode of the diode D2 by the control signal φ4. The cathode of the diode D1 and the anode of the diode D2 are connected at the connection point S. One side of the charge storage capacitor CD is connected to the connection point S, and the other side of the charge storage capacitor CD is grounded. The potential at the connection point S is VCD.
[0060]
In the first embodiment, as described above, it is necessary to accurately set the HIGH level period of the control signal φ3. However, in the second embodiment, an accurate time is described as described below. Setting of is not required.
[0061]
FIG. 8 is a timing chart of the counter electrode driving circuit in the display device according to the second embodiment of the present invention.
[0062]
At time t0, the switch SW1 is connected to the potential point V1 by the control signal φ1, the potential VLC of the counter electrode P becomes V1, and the charge Q2 (= CLCD × V1) is accumulated in the counter electrode capacitor CLCD.
[0063]
After a certain period of time, at time t1, the control signal φ1 becomes LOW level, the switch SW1 is turned off (at the moment), and at the same time the control signal φ3 becomes HIGH level, and the switch SW2 is turned on, it is stored in the counter electrode capacitor CLCD. The charged charge Q2 is transferred to the charge storage capacitor CD via the charge transfer inductor L, the switch SW2, and the diode D1, and the potential VLC of the counter electrode P decreases from V1. At the end of the charge transfer, the current i (t) flowing through the inductor L becomes 0, and thereafter, even if the switch SW2 remains connected due to the presence of the diode D1, the charge storage capacitor CD to the counter electrode capacitance CLCD Therefore, the charge Q2 is stored in the charge storage capacitor CD.
[0064]
At time t2 after the end of the charge transfer, the control signal φ3 becomes LOW level and the switch SW2 is turned off. At this time after the end of the charge transfer, the potential VLC of the counter electrode P becomes V2 ′ (V2 ′ is approximately 0V, that is, the value of V2 ′ is substantially equal to the value of V2). At the same time (after the moment), the control signal φ2 becomes HIGH level, the switch SW1 is connected to the potential point V2, and the counter electrode capacitor CLCD is discharged until the potential VLC of the counter electrode P becomes V2. Thereafter, the potential VLC of the counter electrode P is held at V2 until a certain period elapses until time t3. However, as in the first embodiment, the counter electrode P is maintained for a certain period immediately before time t3. That the potential VLC is held at V2 is particularly important for the normal operation of writing to the pixels in the liquid crystal display device.
[0065]
After a certain period of time, at time t3, the control signal φ2 becomes LOW level and the switch SW1 is turned off. At the same time, the control signal φ4 becomes HIGH level, the switch SW3 is turned on, and the charge Q2 stored in the charge storage capacitor CD is transferred to the counter electrode capacitor CLCD via the diode D2, the switch SW3 and the charge transfer inductor L. As a result, the potential VLC of the counter electrode P rises from V2. However, the charge Q2 may be lost due to a switch, a leakage current, or the like.
[0066]
At time t4 after the end of the charge transfer, the control signal φ4 becomes LOW level and the switch SW3 is turned off again. At this time, the potential VLC of the counter electrode P becomes V1 ′ due to charge loss or the like (| V1 ′ | ≦ | V1 |). At the same time (after the moment), the control signal φ1 becomes HIGH level, the switch SW1 is connected to the potential point V1 side, and the potential VLC of the counter electrode P becomes V1. Thereafter, the potential VLC of the counter electrode P is held at V1 until a time period elapses until time t5, but the potential VLC of the counter electrode P is held at V1 for a certain period immediately before time t5. This is important for the normal operation of writing to the pixels in the liquid crystal display device, as in a certain period immediately before the time t3.
[0067]
From time t5, the same operation as from time t1 is repeated. Thereafter, by repeating the above operation, the potential VLC of the counter electrode P is alternately switched between V1 and V2 every period T.
[0068]
In the second embodiment, the displacement of the counter electrode P and the connection point S is the same as in the first embodiment, and most of the charge / discharge of the charge of the counter electrode capacitor CLCD is performed by the charge storage capacitor CD. The charge newly performed and supplied from the potential point V1 or V2 is only the charge necessary for obtaining the correction voltage (V1-V1 ′ or V2-V2 ′), and is required for switching the voltage of the counter electrode P. The same applies to the point that the power consumption is very small. However, if the end of the HIGH period of the control signals φ3 and φ4 is after the end of the charge transfer, it does not have to be the same as the end of the charge transfer, and strict setting is not required, but the charge transfer can be performed reliably.
[0069]
For example,
ON resistance of switches SW2 and SW3 = 0Ω
Counter electrode capacity CLCD capacity = charge storage capacitor CD capacity = 300 nF
Inductance of inductor L = 2.7 μH
Then, the HIGH level period of the control signals φ3 and φ4 is
HIGH level period of control signals φ3 and φ4 ≧ 2.00 μsec
It is sufficient to set so as to satisfy the above, and the circuit design is easy.
[0070]
FIG. 9 is a circuit configuration diagram of the counter electrode driving circuit in the display device according to the third embodiment of the present invention.
[0071]
The configuration of the third embodiment differs from that of the second embodiment of FIG. 7 only in the configuration between the counter electrode P and the connection point S, and the charge storage capacitor is changed from the counter electrode capacitance CLCD. The charge transfer path to CD and the charge transfer path from charge storage capacitor CD to counter electrode capacitor CLCD are separately provided. That is, charge transfer from the counter electrode capacitance CLCD to the charge storage capacitor CD is performed via the inductor L1, the switch SW2, and the diode D1, and charge transfer from the charge storage capacitor CD to the counter electrode capacitance CLCD is performed by the inductor L2. , Via the switch SW3 and the diode D2.
[0072]
The circuit operation by each control signal φ1, φ2, φ3, and φ4, the displacement of the potential VLC of the counter electrode P, and the effect of using this circuit are the same as in the second embodiment.
[0073]
FIG. 10 is a circuit configuration diagram of the counter electrode driving circuit in the display device according to the fourth embodiment of the present invention.
[0074]
The configuration of the fourth embodiment is a configuration in which each switch in the first embodiment of FIG. 1 is replaced with a MOS transistor. Both of the switches SW1 and SW3 in the first embodiment can use MOS transistor switches. However, in the fourth embodiment, the P-channel transistor and the potential point V2 side are on the potential point V1 side of the switch SW1. An N channel transistor is used for the switch SW3, and a P channel transistor and an N channel transistor are used for the switch SW3. The P channel transistor on the potential point V1 side of the switch SW1 uses the control signal / φ1, the N channel transistor on the potential point V1 side uses the control signal φ2, and the P channel transistor of the switch SW3 uses the control signals / φ3 and φ3, respectively. . The circuit operation and effects obtained by using this circuit are the same as those in the first embodiment.
[0075]
FIG. 11 is a circuit diagram of a counter electrode driving circuit in the display device according to the fifth embodiment of the present invention.
[0076]
The configuration of the fifth embodiment is a configuration in which each switch in the second embodiment of FIG. 7 is replaced with a MOS transistor. All of the switches SW1, SW2, and SW3 in the second embodiment can use MOS transistor switches. In the fifth embodiment, a P-channel transistor and a potential point V2 are connected to the potential point V1 side of the switch SW1. N-channel transistors are used on the side, and N-channel transistors are used for the switches SW2 and SW3. The control signal / φ1 is used for the P-channel transistor on the potential point V1 side of the switch SW1, the control signal φ2 is used for the N-channel transistor on the potential point V2 side, and the control signals φ3 and φ4 are used for the N-channel transistors of the switches SW2 and SW3. The circuit operation and effects obtained by using this circuit are the same as those in the second embodiment.
[0077]
FIG. 12 is a circuit configuration diagram of the counter electrode driving circuit in the display device according to the sixth embodiment of the present invention.
[0078]
The configuration of the sixth embodiment is a configuration in which each switch in the third embodiment of FIG. 9 is replaced with a MOS transistor. All of the switches SW1, SW2, and SW3 in the second embodiment can use MOS transistor switches. In the sixth embodiment, the potential point V1 side, the potential point V2 side, and the switch SW2 of the switch SW1. A P-channel transistor and an N-channel transistor are used for the switch SW3. The P-channel transistor and the N-channel transistor on the potential point V1 side of the switch SW1 are the control signals / φ1 and φ1, the P-channel transistor and the N-channel transistor on the potential point V2 side are the control signals / φ2 and φ2, P of the switches SW2 and SW3. The channel transistors and N-channel transistors use control signals / φ3 and φ3 and control signals / φ4 and φ4, respectively. The circuit operation and the effect of using this circuit are the same as in the third embodiment.
[0079]
FIG. 13 is a circuit configuration diagram of the counter electrode drive circuit in the display device according to the seventh embodiment of the present invention.
[0080]
Compared with the first embodiment of FIG. 1, the configuration of the seventh embodiment is a configuration in which two compensation points for charge loss during charge transfer are provided. In other words, not only the counter electrode P but also the connection point S is provided with a charge loss compensation point. The connection point S is provided with a switch SW5. The switch SW5 is connected to the potential point V2 by the control signal φ1, and the connection to the potential point V1 is controlled by the control signal φ2. The other configuration is the same as that of the first embodiment.
[0081]
FIG. 14 is a timing chart of the counter electrode drive circuit in the display device according to the seventh exemplary embodiment of the present invention.
[0082]
Regarding circuit operation in the circuit configuration of the seventh embodiment, differences from the first embodiment will be described. After the charge transfer from the common electrode capacitance CLCD to the charge storage capacitor CD, the common electrode capacitance CLCD is discharged to the potential V2 by the switch SW1, but at this time, the charge storage capacitor CD is simultaneously turned on by the switch SW5. It differs in that it is charged to the potential V1. Further, after the charge transfer from the charge storage capacitor CD to the counter electrode capacitance CLCD, the counter electrode capacitance CLCD is charged to the potential V1 by the switch SW1, but at the same time, the charge storage capacitor CD is switched to the switch. It differs in that it is discharged to the potential V2 by SW5.
[0083]
By providing two charge loss compensation points during charge transfer, charge loss compensation can be performed in a shorter time.
[0084]
FIG. 15 is a circuit configuration diagram of the counter electrode driving circuit in the display device according to the eighth embodiment of the present invention.
[0085]
Compared with the first embodiment of FIG. 1, the configuration of the eighth embodiment of the present invention is that an additional capacitor CH is added to the counter electrode P in order to stabilize the potential VLC of the counter electrode P. Only different. Here, each capacity is set so that the capacity of the charge storage capacitor CD is the sum of the capacity of the counter electrode capacity CLCD and the capacity of the additional capacity CH.
[0086]
In each of the above embodiments, the configuration in which the potential VLC of the counter electrode P is switched has been described. Normally, when switching the potential VLC of the counter electrode P, it is also necessary to switch the potential of the common electrode of the auxiliary capacitor of the pixel. Each configuration of the present invention can also be applied to switching of the potential of the common electrode of the auxiliary capacitor of the pixel.
[0087]
FIG. 16 is a circuit configuration diagram of the counter electrode driving circuit in the display device according to the ninth embodiment of the present invention.
[0088]
When it is necessary to switch the potential VLC of the counter electrode P and the potential of the common electrode of the auxiliary capacitor of the pixel at different voltages or timings, a potential switching circuit may be provided as shown in FIG. The potential VLC of the counter electrode P is switched using a potential switching circuit composed of a charge storage capacitor CD, an inductor L, and switches SW1 and SW3, and the charge of the common electrode of the auxiliary capacitor of the pixel is switched. A potential switching circuit including a storage capacitor CD ′, an inductor L ′, and switches SW1 ′ and SW3 ′ is used.
[0089]
FIG. 17 is a circuit configuration diagram of the data line reference potential supply circuit in the display device according to the tenth embodiment of the present invention.
[0090]
The configuration of the tenth embodiment is an example in which the configuration of the present invention is applied when it is necessary to switch the reference potential applied to the data line when the data line driving circuit is configured by a digital circuit.
[0091]
A shift register and a data circuit to which image data DATA and a clock signal CLOCK are input, a data line drive output node Q1 connected to the shift register and the data circuit via switches SW1, SW2, SW3, and SW4, respectively, and a data line drive Data line drive output nodes Q2,. . . , Qn and switches SW1, SW2, SW3, SW4, respectively, and switches SW1 ′, SW2 ′, which switch between potentials V1 and V1 ′, potentials V2 and V2 ′, potentials V3 and V3 ′, and potentials V4 and V4 ′, respectively. It is composed of SW3 ′ and SW4 ′. Capacitors C1, C2, C3, and C4 shown between the switches SW1 and SW1 ′, between the switches SW2 and SW2 ′, between the switches SW3 and SW3 ′, and between the switches SW4 and SW4 ′, respectively. Are the capacitances of the reference potential supply lines, and the external reference potentials are Vref1, Vref2, Vref3, and Vref4, respectively.
[0092]
The external reference potentials Vref1, Vref2, Vref3, and Vref4 are synchronized with the clock signal CLOCK according to the input of the image data DATA, and the data line drive output nodes Q1, Q2,. . . , Qn.
[0093]
FIG. 18 is a circuit configuration diagram of the data line reference potential supply circuit according to the tenth embodiment.
[0094]
The data line reference potential supply circuit for supplying the external reference potential Vref1 has a switch SW1 for switching the potentials V1 and V1 ′ between the control signals φ1 and φ2, one end connected to the switch SW1, and the other end controlled by the control signal φ3. An inductor L connected to one end of the switch SW2, an external capacitor CD having one side connected to the other end of the switch SW2, and the other side grounded, one side connected to one end of the switch SW1 and the inductor L, and the other side The capacitor C1 is a grounded reference potential supply line. The data line reference potential supply circuit for supplying the external reference potentials Vref2, Vref3, and Vref4 has the same configuration.
[0095]
When the reference potential is switched every scanning line period or one frame period, the data line reference potential supply circuit supplies the potential V1 as the external reference potential Vref1 for a certain period, for example, and the external reference potential Vref1 for the next period. Is supplied with the potential V1 ′. The specific circuit operation is the same as that of the first embodiment of FIG. 1, and the external reference potential Vref1 is transferred by storing the charge stored in the capacitor C1 of the reference potential supply line to the external capacitor CD. Switch.
[0096]
Even in this case, the external reference potential can be switched with very low power consumption.
[0099]
【The invention's effect】
According to the display device according to the embodiment of the present invention, the switching elements respectively connected to the signal lines and the scanning lines at the intersections of the plurality of signal lines and the plurality of scanning lines, and the switching elements A pixel electrode to which a signal from a signal line is applied via a switching element in response to a scanning signal input to the scanning line, and a pixel electrode and a counter electrode facing the pixel electrode. A liquid crystal layer including liquid crystal molecules sandwiched between and driven by an applied voltage between the pixel electrode and the counter electrode, and one side is an electrode disposed and connected to each pixel electrode, and the other side Is an auxiliary capacitor, which is a common electrode arranged corresponding to each electrode, and the common electrode via an inductor, and the electric charge stored in the common electrode is mutually exchanged with the common electrode via the inductor. Forwarded to Alternatively, it is equipped with a charge storage capacitor that displaces the potential of the common electrode at a predetermined cycle by transferring, so that it can be driven by an inexpensive LSI with a small chip size and low withstand voltage, low power consumption, and high A display device capable of displaying quality can be provided.
[0100]
In the above configuration of the display device according to the embodiment of the present invention, the charge lost by the charge transfer between the common electrode and the charge storage capacitor is replenished after the charge transfer is completed. Can be accurately controlled.
[0101]
According to the display device according to another embodiment of the present invention, a plurality of signals to which predetermined reference potentials respectively selected according to the control signal among two or more reference potentials are applied via the reference potential supply line. A switching element that is connected to the signal line and the scanning line, and a switching element that is connected to each of the switching elements at the intersection of the line and the plurality of signal lines and the plurality of scanning lines. Is sandwiched between a pixel electrode to which a signal from a signal line is applied via a switching element in accordance with a scanning signal input to the pixel electrode and a counter electrode opposite to the pixel electrode, and the pixel electrode and the counter electrode A liquid crystal layer containing liquid crystal molecules driven by a voltage applied between them and each reference potential supply line capacitance added to each reference potential supply line are provided via an inductor, and stored in each reference potential supply line capacitance. Since the charge storage capacitor that displaces the predetermined reference potential in a predetermined cycle by transferring or transferring the charge to and from each reference potential supply line capacitance to each other through each inductor, the chip size is small, A display device that can be driven by an inexpensive LSI with low withstand voltage, has low power consumption, and can display high quality can be provided.
[0102]
In the above configuration of the display device according to another embodiment of the present invention, the charge lost by the charge transfer between the reference potential supply line capacitor and the charge storage capacitor is replenished after the charge transfer is completed. Therefore, the potential of the counter electrode can be accurately controlled.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a counter electrode driving circuit in a display device according to a first embodiment of the present invention.
FIG. 2 is a timing chart of a counter electrode driving circuit in the display device according to the first embodiment of the invention.
FIG. 3 is a circuit configuration diagram of an equivalent circuit of the counter electrode driving circuit according to the first embodiment at the time of charge transfer from the counter electrode capacitor CLCD to the charge storage capacitor CD;
FIG. 4 shows the potential VLC (t) of the counter electrode P, the potential VCD (t) of the connection point S, and the current i (t) when the switch SW3 of the counter electrode driving circuit according to the first embodiment is on. A graph showing changes.
FIG. 5 is a circuit configuration diagram of an example of a circuit that generates control signals φ1, φ2, and φ3 of the counter electrode driving circuit according to the first embodiment.
6 is a timing chart of the polarity switching pulse Hp and control signals φ1, φ2, and φ3 in the circuit of FIG. 5;
FIG. 7 is a circuit configuration diagram of a counter electrode driving circuit in a display device according to a second embodiment of the present invention.
FIG. 8 is a timing chart of the counter electrode drive circuit in the display device according to the second embodiment of the present invention.
FIG. 9 is a circuit configuration diagram of a counter electrode driving circuit in a display device according to a third embodiment of the present invention.
FIG. 10 is a circuit configuration diagram of a counter electrode driving circuit in a display device according to a fourth embodiment of the present invention.
FIG. 11 is a circuit configuration diagram of a counter electrode driving circuit in a display device according to a fifth embodiment of the present invention.
FIG. 12 is a circuit configuration diagram of a counter electrode driving circuit in a display device according to a sixth embodiment of the present invention.
FIG. 13 is a circuit configuration diagram of a counter electrode driving circuit in a display device according to a seventh embodiment of the present invention.
FIG. 14 is a timing chart of a counter electrode driving circuit in a display device according to a seventh embodiment of the present invention.
FIG. 15 is a circuit configuration diagram of a counter electrode driving circuit in a display device according to an eighth embodiment of the present invention.
FIG. 16 is a circuit configuration diagram of a counter electrode driving circuit in a display device according to a ninth embodiment of the present invention.
FIG. 17 is a circuit configuration diagram of a data line reference potential supply circuit in a display device according to a tenth embodiment of the present invention.
FIG. 18 is a circuit configuration diagram of a data line reference potential supply circuit according to the tenth embodiment.
FIG. 19 is a schematic configuration diagram of an array substrate.
FIG. 20 is an explanatory diagram schematically illustrating a cross-sectional structure of a pixel portion of a liquid crystal display device.
[Explanation of symbols]
1901 TFT
1902 Auxiliary capacity
1903 Liquid crystal capacitance CL
1904 Data line driving circuit
1905 Gate line drive circuit
1906 Counter electrode
1907 Data line
1908 Gate line
1909 pixels
2001, 2010 Glass substrate
2002 Color filter
2003 Black Matrix
2004, 2015 Protective film
2005 Counter electrode
2006, 2016 Alignment film
2007 Liquid crystal layer
2011 Gate electrode
2012 Gate insulation film
2013 Amorphous silicon
2014 Pixel electrode
2017 Source electrode
2018 Drain electrode

Claims (8)

Switching elements respectively connected to the signal lines and the scanning lines at intersections of the plurality of signal lines and the plurality of scanning lines;
A pixel electrode connected to each of the switching elements, to which a signal from the signal line is applied via the switching element in response to a scanning signal input to the scanning line;
A liquid crystal layer including liquid crystal molecules sandwiched between the pixel electrode and a counter electrode opposite to the pixel electrode and driven by an applied voltage between the pixel electrode and the counter electrode;
One side is an electrode disposed and connected to each pixel electrode, and the other side is an auxiliary capacitor that is a common electrode disposed correspondingly to each electrode;
The common electrode is disposed alongside the common electrode, and the electric charge stored in the common electrode is transferred or transferred to and from the common electrode via the inductor. A display device comprising a charge storage capacitor to be displaced.   2. The display device according to claim 1, wherein the common electrode is held at a first predetermined potential for a first predetermined period, a first writing operation is performed by applying the signal to each pixel electrode, and then the common electrode is applied. The charge stored in is transferred to the charge storage capacitor, the common electrode is held at a second predetermined potential for a second predetermined period, and a second write operation is performed by applying the signal to each pixel electrode. Then, the charge stored in the charge storage capacitor is transferred to the common electrode, the common electrode is held at the first predetermined potential for a third predetermined period, and the signal is applied to each pixel electrode. The first write operation is performed, and the second or first write operation with respect to each pixel electrode is performed for each scan while holding the potential of the common electrode at the second or first predetermined potential for each predetermined period after the first scan. Order by line Display device, which comprises carrying out.   The display device according to claim 1, wherein the common electrode is held at a first predetermined potential for a first predetermined period and is connected to the switching element via the switching element connected to a first scanning line. A first write operation is performed by applying the signal to the pixel electrode, and then the charge stored in the common electrode is transferred to the charge storage capacitor, and the common electrode is held at a second predetermined potential for a second predetermined period. To the pixel electrode connected to the switching element via the switching element connected to the second scanning line, and then applying a second write operation by applying the signal to the charge storage capacitor. The stored charge is transferred to the common electrode, the common electrode is held at the first predetermined potential for a third predetermined period, and the switching element connected to the third scanning line is connected. Then, the first write operation is performed by applying the signal to the pixel electrode connected to the switching element, and the potential of the common electrode is held at the second or first predetermined potential for each predetermined period thereafter. The display device, wherein the second or first writing operation with respect to the pixel electrode is sequentially performed for each scanning line.   4. A display device according to claim 1, wherein the charge lost by the charge transfer between the common electrode and the charge storage capacitor is replenished after the charge transfer is completed. apparatus. A plurality of signal lines each of which is supplied with a predetermined reference potential selected in accordance with a control signal among the two or more reference potentials via a reference potential supply line;
Switching elements respectively connected to the signal lines and the scanning lines at intersections of the plurality of signal lines and the plurality of scanning lines;
A pixel electrode connected to each of the switching elements, to which a signal from the signal line is applied via the switching element in response to a scanning signal input to the scanning line;
A liquid crystal layer including liquid crystal molecules sandwiched between the pixel electrode and a counter electrode opposite to the pixel electrode and driven by an applied voltage between the pixel electrode and the counter electrode;
Each reference potential supply line capacitance added to each reference potential supply line is provided with an inductor via an inductor, and the charge stored in each reference potential supply line capacitance is transferred between each reference potential supply line capacitance and each reference potential supply line capacitance. A display device comprising: a charge storage capacitor that is transferred to or transferred from each other via each inductor to displace the predetermined reference potential in a predetermined cycle. 6. The display device according to claim 5, wherein the reference potential supply line is held at a first predetermined reference potential for a first predetermined period, a first write operation is performed by applying the signal to each pixel electrode, and then The charge stored in the reference potential supply line capacitance is transferred to the charge storage capacitor, the reference potential supply line is held at a second predetermined reference potential for a second predetermined period, and the signal is supplied to each pixel electrode. A second write operation is performed by application, and then the charge stored in the charge storage capacitor is transferred to the reference potential supply line capacitance, and the reference potential supply line is set to the first predetermined reference potential for a third predetermined period. The first write operation is performed by applying the signal to each pixel electrode, and the potential of the reference potential supply line is held at the second or first predetermined reference potential for each predetermined period after Each pixel power Display device comprising sequentially performing the second or first write operation to each of said scanning lines for.   The display device according to claim 5, wherein the reference potential supply line is held at a first predetermined reference potential for a first predetermined period, and the switching element is connected to the switching element via the switching element connected to the first scanning line. A first write operation is performed by applying the signal to the connected pixel electrode, and then the charge stored in the reference potential supply line capacitance is transferred to the charge storage capacitor to perform the reference potential for a second predetermined period. A supply line is held at a second predetermined reference potential, and a second write operation is performed by applying the signal to the pixel electrode connected to the switching element via the switching element connected to the second scanning line. Then, the charge stored in the charge storage capacitor is transferred to the reference potential supply line capacitance, and the reference potential supply line is held at the first predetermined reference potential for a third predetermined period. The first writing operation is performed by applying the signal to the pixel electrode connected to the switching element via the switching element connected to a third scanning line, and the reference potential supply line for each predetermined period after The display device is characterized in that the second or first write operation for the pixel electrode is sequentially performed for each scanning line while maintaining the potential at the second or first predetermined reference potential.   8. The display device according to claim 5, wherein the charge lost by the charge transfer between the reference potential supply line capacitance and the charge storage capacitor is replenished after the charge transfer is completed. A display device.

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