JPH09243998A - Display device - Google Patents

Display device

Info

Publication number
JPH09243998A
JPH09243998A JP5627396A JP5627396A JPH09243998A JP H09243998 A JPH09243998 A JP H09243998A JP 5627396 A JP5627396 A JP 5627396A JP 5627396 A JP5627396 A JP 5627396A JP H09243998 A JPH09243998 A JP H09243998A
Authority
JP
Japan
Prior art keywords
signal
line
signal line
pixel electrode
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5627396A
Other languages
Japanese (ja)
Inventor
Minoru Sasaki
佐々木  実
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP5627396A priority Critical patent/JPH09243998A/en
Publication of JPH09243998A publication Critical patent/JPH09243998A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a display device, particularly, an active matrix liquid crystal display device with a high quality display and with less power consumption. SOLUTION: The write-in is performed to respective pixels successively while short-circuiting signal lines each other (S1 and S2), (S2 and S3), (S3 and S4),...) adjacent each other by inter-signal lines short circuit circuits 1-7-1, 1-7-2,... for intermittent write-in operation of the display device applying a signal of opposite polarity at every the number of prescribed pieces of signal lines and writing in the signal. Then, respective signal lines potential just before respective write-in operation become intermediate potential uniformizing positive/ negative signal potential. Since a signal line drive circuit doesn't displace each signal line potential from positive (negative) potential to negative (positive) potential, but only displaces from the intermediate potential to the negative (positive) potential, the power consumption in the signal line drive circuit is reduced by half.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は表示装置に係り、特
にアクティブマトリクス型の液晶表示装置の駆動回路に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a drive circuit for an active matrix type liquid crystal display device.

【0002】[0002]

【従来の技術】薄型、軽量、低消費電力で高画質な表示
装置として、TFT(薄膜トランジスタ)を用いた液晶
表示装置(TFT−LCD)が、パーソナル・コンピュ
ータ、TV、ゲーム機等に幅広く使用されている。TF
T−LCDは、通常、画素が配設されたアレイ基板とカ
ラーフィルタが形成された対向基板とから構成される液
晶セルに液晶材料を封入し、これら両基板の外部側に偏
光板を配置して背面側から照明を照射する構成となって
いる。
2. Description of the Related Art A liquid crystal display device (TFT-LCD) using a TFT (thin film transistor) is widely used in personal computers, TVs, game machines and the like as a display device having a thin, lightweight, low power consumption and high image quality. ing. TF
In a T-LCD, a liquid crystal material is usually enclosed in a liquid crystal cell composed of an array substrate on which pixels are arranged and a counter substrate on which a color filter is formed, and a polarizing plate is arranged on the outside of these substrates. The illumination is applied from the rear side.

【0003】図6は、アレイ基板の概略構成図である。
各画素509には、信号サンプリング用のTFT50
1、電圧保持用の補助容量CS 502等が配設されてい
る。
FIG. 6 is a schematic configuration diagram of an array substrate.
Each pixel 509 has a TFT 50 for signal sampling.
1. A storage capacitor CS 502 for holding voltage is provided.

【0004】図7は、液晶表示装置の画素部の断面構造
を模式的に表した説明図である。対向基板は、ガラス基
板601上に形成されたカラーフィルタ602及びブラ
ックマトリクス603と、これらの上に順次形成された
保護膜604、対向電極605、配向膜606等から構
成されている。一方、アレイ基板は、ガラス基板610
上に形成されたTFT及び画素、これらを覆うように順
次形成された保護膜615、配向膜616等から形成さ
れている。TFTは、ゲート電極611、ゲート絶縁膜
612、アモルファスシリコン613、ソース電極61
7、ドレイン電極618等から構成されている。また、
画素は、ゲート絶縁膜612上に形成された画素電極6
14により構成される。液晶セルは、対向基板上の配向
膜606とアレイ基板上の配向膜616とが相互に対向
するように2枚の基板を対向させ、基板間に液晶層60
7が挟持された構成となっている。
FIG. 7 is an explanatory view schematically showing a sectional structure of a pixel portion of a liquid crystal display device. The counter substrate is composed of a color filter 602 and a black matrix 603 formed on a glass substrate 601, a protective film 604, a counter electrode 605, an alignment film 606 and the like which are sequentially formed on these. On the other hand, the array substrate is a glass substrate 610.
The TFT and the pixel formed above, the protective film 615 and the alignment film 616 which are sequentially formed so as to cover these, and the like. The TFT includes a gate electrode 611, a gate insulating film 612, amorphous silicon 613, a source electrode 61.
7, a drain electrode 618 and the like. Also,
The pixel is the pixel electrode 6 formed on the gate insulating film 612.
It is composed of 14. In the liquid crystal cell, two substrates are opposed to each other such that the alignment film 606 on the counter substrate and the alignment film 616 on the array substrate face each other, and the liquid crystal layer 60 is interposed between the substrates.
7 is sandwiched.

【0005】図6に戻って説明すると、各TFT501
はデータ線507及びゲート線508を介してデータ線
駆動回路504及びゲート線駆動回路505によって制
御される。また、符号503は、1画素当たりの液晶容
量CL を示している。液晶は、直流電圧の印加を継続し
または繰り返すと分極等の減少により特性劣化のおそれ
があるため、通常、液晶表示装置は交流駆動を行う必要
があり、以下のように駆動される。
Returning to FIG. 6, each TFT 501 will be described.
Are controlled by the data line driving circuit 504 and the gate line driving circuit 505 via the data line 507 and the gate line 508. Reference numeral 503 indicates the liquid crystal capacitance CL per pixel. When liquid crystal is applied with a DC voltage continuously or repeatedly, its characteristics may be deteriorated due to a decrease in polarization. Therefore, normally, the liquid crystal display device needs to be driven by AC, and is driven as follows.

【0006】データ線駆動回路504から信号電圧が供
給され、ゲート線駆動回路505によりTFTのゲート
が開いた状態となると、信号電圧により画素509に書
込みが行われる。この信号電圧は、次の書込みが行われ
るまで補助容量CS 502及び液晶容量CL 503によ
り保持される。一方、対向電極506には、一定電圧が
印加される。従って、例えば、対向電極506の電位を
0Vとすると、ある一定期間(例えば1フレーム時間)
画素509の電位を+3Vとし、その次の一定期間は画
素509の電位を−3Vとすると、液晶層には±3Vの
交流電圧が印加されることになる。この駆動方法をここ
では「フレーム反転駆動」と称することとする。
When the signal voltage is supplied from the data line driving circuit 504 and the gate of the TFT is opened by the gate line driving circuit 505, writing is performed in the pixel 509 by the signal voltage. This signal voltage is held by the auxiliary capacitance CS 502 and the liquid crystal capacitance CL 503 until the next writing is performed. On the other hand, a constant voltage is applied to the counter electrode 506. Therefore, for example, assuming that the potential of the counter electrode 506 is 0 V, a certain fixed period (for example, one frame time)
When the electric potential of the pixel 509 is +3 V and the electric potential of the pixel 509 is −3 V for the next fixed period, an AC voltage of ± 3 V is applied to the liquid crystal layer. This driving method is referred to as "frame inversion driving" here.

【0007】交流電圧印加の形態として画面全体の極性
の正負を変化させる形態では、フリッカによる画質劣化
が生ずるため、1走査線ごとに極性を反転させ、各走査
線ごとに極性の正負を順次変化させる方法がある。即
ち、あるフレームにおけるデータ書込みの際、ある走査
線においては正極性の電圧が、当該走査線に隣接する走
査線においては負極性の電圧が印加されるように各走査
線に電圧印加を行い、その次のフレームにおけるデータ
書込みの際の電圧印加は、各走査線への印加電圧の極性
が直前のフレームにおける印加電圧の極性と逆極性とな
るように行う。この場合も、対向電極の電位は一定に保
持される。この駆動方法を「Hライン反転駆動」と称す
ることとする。
In the form of changing the polarity of the entire screen as the form of AC voltage application, the image quality is deteriorated due to flicker, so the polarity is inverted for each scanning line and the polarity is changed for each scanning line sequentially. There is a way to do it. That is, when writing data in a frame, voltage is applied to each scanning line so that a positive voltage is applied to a certain scanning line and a negative voltage is applied to a scanning line adjacent to the scanning line. The voltage application at the time of writing data in the next frame is performed so that the polarity of the applied voltage to each scanning line is opposite to the polarity of the applied voltage in the immediately preceding frame. Also in this case, the potential of the counter electrode is kept constant. This driving method will be referred to as "H line inversion driving".

【0008】また、1走査線ごとに極性を反転させるH
ライン反転駆動に対して、1信号線ごとに極性を反転さ
せ、各信号線ごとに極性の正負を順次変化させる方法も
あり、この駆動方法を「Vライン反転駆動」と称する。
Further, the polarity H is inverted every scanning line.
For line inversion drive, there is also a method of inverting the polarity for each signal line and sequentially changing the polarity of the polarity for each signal line, and this drive method is called “V line inversion drive”.

【0009】さらに、画質劣化を防止する駆動方法とし
て、1走査線上の1画素ごと、又は複数走査線上の複数
画素ごとに、極性を反転させ、1画素ごと又は複数画素
ごとに極性の正負を順次変化させる方法がある。即ち、
1画素ごとの反転の場合、あるフレームにおけるデータ
書込みの際、ある走査線上のある画素には正極性の電圧
が、当該画素に隣接する画素には負極性の電圧が印加さ
れ、当該走査線に隣接する走査線上の各画素には、隣接
する当該走査線上の各画素と逆極性の電圧が印加させる
ようにし、その次のフレームにおけるデータ書込みの際
の電圧印加は、各画素への印加電圧の極性が直前のフレ
ームにおける印加電圧の極性と逆極性となるように行
う。この場合も、対向電極の電位は一定に保持される。
この駆動方法をここでは「HV反転駆動」と称すること
とする。このHV反転駆動では、正極性、負極性の画素
が画面上において最小ピッチで配置され、フレームごと
に各画素の極性を順次切り換えることにより交流駆動す
ることができ、正極性・負極性のデータの差が平均化さ
れて見えるため、フリッカ、ラインクロール等の画質劣
化が最も少ない。
Further, as a driving method for preventing the deterioration of image quality, the polarity is inverted for each pixel on one scanning line or for each plurality of pixels on a plurality of scanning lines, and the positive and negative polarities are sequentially set for each pixel or each plural pixels. There is a way to change. That is,
In the case of inversion for each pixel, when writing data in a frame, a positive voltage is applied to a pixel on a scan line and a negative voltage is applied to a pixel adjacent to the pixel, and the scan line is applied to the pixel. Each pixel on the adjacent scanning line is applied with a voltage having a polarity opposite to that of each pixel on the adjacent scanning line, and the voltage applied at the time of writing data in the next frame is the voltage applied to each pixel. The polarity is set to be opposite to that of the applied voltage in the immediately preceding frame. Also in this case, the potential of the counter electrode is kept constant.
This driving method will be referred to as "HV inversion driving" here. In this HV inversion drive, positive and negative polarity pixels are arranged at a minimum pitch on the screen, and alternating drive can be performed by sequentially switching the polarities of the pixels for each frame. Since the differences appear to be averaged, image deterioration such as flicker and line crawl is minimized.

【0010】[0010]

【発明が解決しようとする課題】しかしながら、HV反
転駆動は、上記3つの駆動方法のうち画質劣化が最小で
ある反面、各信号線の電位の正負を1走査期間ごとに切
り換える必要があり、信号線を充放電するための消費電
力が最も大きいという問題点がある。また、Vライン反
転駆動も、Hライン反転駆動と並び、HV反転駆動に次
いで消費電力が大きい。
However, in the HV inversion drive, the image quality deterioration is minimum among the above three driving methods, but on the other hand, it is necessary to switch the positive / negative of the potential of each signal line every scanning period. There is a problem that the power consumption for charging and discharging the wire is the largest. In addition, the V line inversion drive has the same power consumption as the HV inversion drive, next to the HV inversion drive.

【0011】本発明は上記問題点に鑑みてなされたもの
で、その目的は、画質劣化が最小のHV反転駆動、又は
HV反転駆動に次いで画質劣化の小さいVライン反転駆
動を採用した高品質表示で、かつ、消費電力が小さい表
示装置、特にアクティブマトリクス型の液晶表示装置を
提供することである。
The present invention has been made in view of the above problems, and an object thereof is high-quality display employing HV inversion driving with minimal deterioration in image quality, or V line inversion driving with minimal deterioration in image quality following HV inversion driving. In addition, it is an object of the present invention to provide a display device which consumes less power and, in particular, an active matrix liquid crystal display device.

【0012】[0012]

【課題を解決するための手段】本発明に係る表示装置に
よれば、複数の信号線と複数の走査線との交差部に、信
号線及び走査線に接続されてそれぞれ配設されたスイッ
チング素子と、スイッチング素子のそれぞれに接続され
て配設され、走査線への走査信号入力に応じてスイッチ
ング素子を介して、信号線からの信号が印加される画素
電極と、一の画素電極に印加される信号の極性と、一の
画素電極に対して走査線方向に隣接する他の画素電極に
印加される信号の極性とが相互に逆極性の信号となるよ
うに、複数の信号線を駆動する信号線駆動回路及び複数
の走査線を駆動する走査線駆動回路と、画素電極への各
信号印加動作前に、一の信号線と一の信号線に対して隣
接する他の信号線とを相互に短絡し得るように各信号線
間に配設された信号線間短絡回路と、画素電極と画素電
極に対向する対向電極との間に挟持され、画素電極と対
向電極との間の印加電圧により駆動される液晶分子を含
む液晶層とを備えたことを特徴とし、断続する書込み動
作間において、すべての信号線間を短絡しながら順次各
画素に書込みを行うことにより各書込み動作直前の各信
号線電位を正極性・負極性信号電位の均一化された中間
電位としたので、信号線駆動回路の消費電力を半減した
高品質表示の表示装置を提供することができる。
According to the display device of the present invention, switching elements are provided at intersections of a plurality of signal lines and a plurality of scanning lines, each of which is connected to the signal line and the scanning line. A pixel electrode to which a signal from a signal line is applied via a switching element in response to a scanning signal input to a scanning line, and a pixel electrode which is applied to one pixel electrode. The plurality of signal lines are driven so that the polarity of the signal that is applied to one pixel electrode and the polarity of the signal that is applied to another pixel electrode that is adjacent to the one pixel electrode in the scanning line direction are opposite to each other. A signal line driver circuit and a scan line driver circuit that drives a plurality of scan lines are connected to one signal line and another signal line which is adjacent to the one signal line before the operation of applying each signal to the pixel electrode. The signal placed between each signal line so that And a liquid crystal layer sandwiched between the pixel electrode and a counter electrode facing the pixel electrode, the liquid crystal layer including liquid crystal molecules driven by an applied voltage between the pixel electrode and the counter electrode. Characteristically, during intermittent write operation, each signal line potential immediately before each write operation is made uniform between positive and negative polarity by writing sequentially to each pixel while short-circuiting all signal lines. Since the intermediate potential is used, it is possible to provide a display device with high quality display in which the power consumption of the signal line driving circuit is reduced by half.

【0013】複数の信号線と複数の走査線との交差部
に、信号線及び走査線に接続されてそれぞれ配設された
スイッチング素子と、スイッチング素子のそれぞれに接
続されて配設され、走査線への走査信号入力に応じてス
イッチング素子を介して、信号線からの信号が印加され
る画素電極と、一の画素電極に印加される信号の極性
と、一の画素電極に対して信号線方向及び走査線方向に
隣接する他の画素電極に印加される信号の極性とが相互
に逆極性の信号となるように、複数の信号線を駆動する
信号線駆動回路及び複数の走査線を駆動する走査線駆動
回路と、画素電極への各信号印加動作前に、一の信号線
と一の信号線に対して隣接する他の信号線とを相互に短
絡し得るように各信号線間に配設された信号線間短絡回
路と、画素電極と画素電極に対向する対向電極との間に
挟持され、画素電極と対向電極との間の印加電圧により
駆動される液晶分子を含む液晶層とを備えたことを特徴
とし、断続する書込み動作間において、すべての信号線
間を短絡しながら順次各画素に書込みを行うことにより
各書込み動作直前の各信号線電位を正極性・負極性信号
電位の均一化された中間電位としたので、信号線駆動回
路の消費電力を半減した高品質表示の表示装置を提供す
ることができる。
A switching element connected to each of the signal line and the scanning line is disposed at an intersection of the plurality of signal lines and the plurality of scanning lines, and a scanning line is disposed connected to each of the switching elements. A pixel electrode to which a signal from a signal line is applied via a switching element in response to a scan signal input to the pixel electrode, a polarity of a signal applied to one pixel electrode, and a signal line direction with respect to the one pixel electrode. And a signal line driver circuit for driving a plurality of signal lines and a plurality of scanning lines so that the polarities of signals applied to other pixel electrodes adjacent to each other in the scan line direction are opposite to each other. Before the operation of applying each signal to the pixel electrode, the scanning line driving circuit is arranged between the signal lines so that one signal line and another signal line adjacent to the one signal line can be short-circuited to each other. Short circuit between signal lines installed, pixel electrode and pixel A liquid crystal layer sandwiched between a counter electrode facing the pole and containing liquid crystal molecules driven by an applied voltage between the pixel electrode and the counter electrode, and between intermittent writing operations, By sequentially writing to each pixel while short-circuiting all the signal lines, the potential of each signal line immediately before each write operation is set to a uniform intermediate potential of the positive and negative signal potentials. It is possible to provide a display device with high quality display in which the power consumption is reduced by half.

【0014】複数の信号線と複数の走査線との交差部
に、信号線及び走査線に接続されてそれぞれ配設された
スイッチング素子と、スイッチング素子のそれぞれに接
続されて配設され、走査線への走査信号入力に応じてス
イッチング素子を介して、信号線からの信号が印加され
る画素電極と、走査線方向に連続して隣接する所定個数
の画素電極の群の一に印加される信号の極性と、一の群
に対して走査線方向に隣接する他の群に印加される信号
の極性とが相互に逆極性の信号となるように、複数の信
号線を駆動する信号線駆動回路及び複数の走査線を駆動
する走査線駆動回路と、画素電極への各信号印加動作前
に、一の信号線と一の信号線に対して隣接する他の信号
線とを相互に短絡し得るように各信号線間に配設された
信号線間短絡回路と、画素電極と画素電極に対向する対
向電極との間に挟持され、画素電極と対向電極との間の
印加電圧により駆動される液晶分子を含む液晶層とを備
えたことを特徴とし、断続する書込み動作間において、
すべての信号線間を短絡しながら順次各画素に書込みを
行うことにより各書込み動作直前の各信号線電位を正極
性・負極性信号電位の均一化された中間電位としたの
で、信号線駆動回路の消費電力を半減した高品質表示の
表示装置を提供することができる。
A switching element connected to each of the signal line and the scanning line is arranged at an intersection of the plurality of signal lines and the plurality of scanning lines, and a scanning line is connected to each of the switching elements. A signal applied to a pixel electrode to which a signal from a signal line is applied and a group of a predetermined number of pixel electrodes that are adjacent to each other in the scanning line direction via a switching element in response to the input of a scanning signal to And a signal line drive circuit that drives a plurality of signal lines such that the polarity of a signal applied to another group adjacent to one group in the scanning line direction is opposite to that of the other group. And a scanning line driving circuit that drives a plurality of scanning lines and one signal line and another signal line adjacent to the one signal line may be short-circuited to each other before each signal application operation to the pixel electrode. And a short circuit between signal lines arranged between each signal line Intermittent writing, comprising a liquid crystal layer sandwiched between a pixel electrode and a counter electrode facing the pixel electrode, the liquid crystal layer including liquid crystal molecules driven by an applied voltage between the pixel electrode and the counter electrode. Between movements,
By sequentially writing to each pixel while short-circuiting all the signal lines, the potential of each signal line immediately before each write operation is set to a uniform intermediate potential of the positive and negative signal potentials. It is possible to provide a display device with high quality display in which the power consumption is reduced by half.

【0015】複数の信号線と複数の走査線との交差部
に、信号線及び走査線に接続されてそれぞれ配設された
スイッチング素子と、スイッチング素子のそれぞれに接
続されて配設され、走査線への走査信号入力に応じてス
イッチング素子を介して、信号線からの信号が印加され
る画素電極と、信号線方向及び走査線方向に連続して隣
接する所定個数の画素電極の方形状の群の一に印加され
る信号の極性と、一の群に対して信号線方向及び走査線
方向に隣接する他の群に印加される信号の極性とが相互
に逆極性の信号となるように、複数の信号線を駆動する
信号線駆動回路及び複数の走査線を駆動する走査線駆動
回路と、画素電極への各信号印加動作前に、一の信号線
と一の信号線に対して隣接する他の信号線とを相互に短
絡し得るように各信号線間に配設された信号線間短絡回
路と、画素電極と画素電極に対向する対向電極との間に
挟持され、画素電極と対向電極との間の印加電圧により
駆動される液晶分子を含む液晶層とを備えたことを特徴
とし、断続する書込み動作間において、すべての信号線
間を短絡しながら順次各画素に書込みを行うことにより
各書込み動作直前の各信号線電位を正極性・負極性信号
電位の均一化された中間電位としたので、信号線駆動回
路の消費電力を半減した高品質表示の表示装置を提供す
ることができる。
A switching element connected to each of the signal line and the scanning line is arranged at an intersection of the plurality of signal lines and the plurality of scanning lines, and a scanning line is connected to each of the switching elements. A rectangular group of pixel electrodes to which a signal from a signal line is applied via a switching element in response to a scanning signal input to the pixel electrode and a predetermined number of pixel electrodes that are continuously adjacent in the signal line direction and the scanning line direction. So that the polarities of the signals applied to one of the groups and the polarities of the signals applied to the other groups adjacent to the one group in the signal line direction and the scanning line direction are mutually opposite polar signals, A signal line drive circuit that drives a plurality of signal lines and a scan line drive circuit that drives a plurality of scan lines, and one signal line and one signal line that are adjacent to each other before applying each signal to the pixel electrode. Each signal should be shorted to other signal lines. Includes liquid crystal molecules sandwiched between signal line short-circuit circuits arranged between lines and a pixel electrode and a counter electrode facing the pixel electrode, and driven by an applied voltage between the pixel electrode and the counter electrode A liquid crystal layer is provided, and the signal line potential immediately before each write operation is changed to positive or negative by sequentially writing to each pixel while short-circuiting all signal lines between intermittent write operations. Since the intermediate potential of the sex signal potential is made uniform, it is possible to provide a display device of high quality display in which the power consumption of the signal line drive circuit is halved.

【0016】各信号線間に配設された信号線間短絡回路
を、一信号線間おきに除去した場合においても、断続す
る書込み動作間において、相互に隣接する信号線同士を
短絡しながら順次各画素に書込みを行うことにより各書
込み動作直前の各信号線電位を正極性・負極性信号電位
の中間電位としたので、信号線駆動回路の消費電力を半
減した高品質表示の表示装置を提供することができる。
Even when the signal line short circuit provided between the signal lines is removed every other signal line, the signal lines adjacent to each other are sequentially short-circuited between the intermittent write operations. By writing to each pixel, the potential of each signal line immediately before each write operation was set to an intermediate potential between the positive and negative signal potentials, thus providing a display device of high quality display in which the power consumption of the signal line drive circuit is halved. can do.

【0017】各信号線間に配設された信号線間短絡回路
のうち、2つの群からなる一の組合せと他の組合せとの
間の信号線間短絡回路を除去した場合においても、断続
する書込み動作間において、相互に隣接する信号線同士
を短絡しながら順次各画素に書込みを行うことにより各
書込み動作直前の各信号線電位を正極性・負極性信号電
位の中間電位としたので、信号線駆動回路の消費電力を
半減した高品質表示の表示装置を提供することができ
る。
The signal line short circuit between the signal lines is intermittent even when the signal line short circuit between one of the two groups and the other combination is removed. During the write operation, the signal line potential immediately before each write operation is set to the intermediate potential between the positive and negative signal potentials by sequentially writing to each pixel while short-circuiting the adjacent signal lines. A display device with high quality display in which the power consumption of the line driver circuit is halved can be provided.

【0018】信号線間短絡回路は、MOSFETスイッ
チであるものとしたので、液晶表示装置の製造工程にお
いて容易に配設することができる。
Since the signal line short circuit is a MOSFET switch, it can be easily provided in the manufacturing process of the liquid crystal display device.

【0019】[0019]

【発明の実施の形態】以下、本発明に係る表示装置の実
施の形態について、図面を参照しながら説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a display device according to the present invention will be described below with reference to the drawings.

【0020】本発明に係る表示装置では、HV反転駆動
において、ある走査線期間、各信号線に対し1信号線お
きに交互に正極性・負極性の書込みデータ信号を印加し
て各画素に書込みを行い、その次の走査線に接続された
画素に書込みを行う前に、相互に隣接する信号線同士又
はすべての信号線を短絡し、その後、各信号線に対し1
信号線おきに交互に正極性・負極性の書込みデータ信号
を印加してその次の走査線に接続された画素に書込みを
行う。このように断続する書込み動作間において、相互
に隣接する信号線同士又はすべての信号線間を短絡しな
がら順次各画素に書込みを行うことに本発明に係る表示
装置の特徴がある。また、Vライン反転駆動においても
同様に、断続する書込み動作間において、相互に隣接す
る信号線同士又はすべての信号線間を短絡しながら順次
各画素に書込みを行う。
In the display device according to the present invention, in the HV inversion drive, a write data signal of positive polarity / negative polarity is alternately applied to each signal line for a certain scanning line period to write to each pixel. And short-circuit adjacent signal lines or all signal lines before writing to the pixel connected to the next scanning line, and then 1 for each signal line.
A positive polarity / negative polarity write data signal is alternately applied to every signal line to write to the pixel connected to the next scanning line. A feature of the display device according to the present invention is that writing is sequentially performed in each pixel while short-circuiting adjacent signal lines or all signal lines between the intermittent writing operations. Similarly, in the V line inversion driving, writing is sequentially performed in each pixel while short-circuiting adjacent signal lines or all signal lines between intermittent writing operations.

【0021】従って、各信号線の電位は、正(負)電
位、中間電位、負(正)電位、中間電位、...という
パターンを繰り返す。
Therefore, the potential of each signal line is positive (negative) potential, intermediate potential, negative (positive) potential, intermediate potential ,. . . Repeat the pattern.

【0022】通常の画像データにおいては、相互に隣接
する画素データ同士の相関性が高いため、相互に隣接す
る信号線同士を短絡することにより、双方の信号線電位
は中間電位となる。信号線同士を短絡するのみであるか
ら信号線駆動回路からの電力供給は不要であり、信号線
駆動回路は各信号線電位を正(負)電位から負(正)電
位へ変位させるのではなく、中間電位から負(正)電位
へ変位させるのみで足りるため、消費電力は半減される
こととなる。
In normal image data, pixel data adjacent to each other has a high correlation, and therefore, by short-circuiting signal lines adjacent to each other, both signal line potentials become intermediate potentials. Since only the signal lines are short-circuited, power supply from the signal line drive circuit is unnecessary, and the signal line drive circuit does not displace each signal line potential from a positive (negative) potential to a negative (positive) potential. Since it is sufficient to displace from the intermediate potential to the negative (positive) potential, the power consumption will be halved.

【0023】図1は、本発明の第1の実施の形態に係る
表示装置の回路構成図である。表示装置(ここでは、液
晶表示装置とする。)は、画素部1−1と、ゲート線駆
動回路1−2と、信号線駆動回路1−3とから構成され
ている。
FIG. 1 is a circuit configuration diagram of a display device according to the first embodiment of the present invention. The display device (here, a liquid crystal display device) includes a pixel portion 1-1, a gate line drive circuit 1-2, and a signal line drive circuit 1-3.

【0024】画素部1−1には、ゲート線駆動回路1−
2に接続されたゲート線G1,G2,...,Gnと、
信号線駆動回路1−3に接続された信号線S1,S2,
S3,...,Smと、これらのゲート線及び信号線に
それぞれ接続されたTFT1−11−1,1−11−
2,...と、各TFTにより駆動される画素1−10
−1,1−10−2,...とが配設されている。各画
素は、補助容量及び液晶容量1−12−1,1−12−
2,...を有している。また、信号線駆動回路1−3
には、画像データを順次転送するシフトレジスタ1−6
と、シフトレジスタ1−6にそれぞれ接続され、ディジ
タルデータをアナログ信号に変換するD/A変換器1−
4−1,1−4−2,...,1−4−mと、各D/A
変換器に接続され、信号線をS1,S2,S
3,...,Smを駆動するアンプ1−5−1,1−5
−2,...,1−5−mと、相互に隣接する信号線同
士S1とS2、S3とS4、...をそれぞれ短絡する
スイッチ1−7−1,1−7−2,...とが配設され
ている。各D/A変換器1−4−1,1−4−
2,...,1−4−mはSW1信号により、アンプ1
−5−1,1−5−2,...,1−5−mはINH信
号により、スイッチ1−7−1,1−7−2,...は
SW2信号により、それぞれ制御される。
The pixel section 1-1 includes a gate line driving circuit 1-
2. The gate lines G1, G2 ,. . . , Gn,
The signal lines S1, S2 connected to the signal line drive circuit 1-3
S3 ,. . . , Sm, and TFTs 1-11-1, 1-11- connected to these gate lines and signal lines, respectively.
2,. . . And a pixel 1-10 driven by each TFT
-1, 1-10-2 ,. . . And are arranged. Each pixel has an auxiliary capacitance and a liquid crystal capacitance 1-12-1, 1-12-.
2,. . . have. In addition, the signal line drive circuit 1-3
Is a shift register 1-6 for sequentially transferring image data.
And a D / A converter 1- which is connected to the shift register 1-6 and converts digital data into an analog signal.
4-1, 1-4-2 ,. . . , 1-4-m and each D / A
It is connected to the converter and the signal lines are S1, S2, S
3,. . . , Sm driving amplifiers 1-5-1, 1-5
-2 .. . . , 1-5-m, and signal lines S1 and S2, S3 and S4 ,. . . Switches 1-7-1, 1-7-2 ,. . . And are arranged. Each D / A converter 1-4-1, 1-4
2,. . . , 1-4-m are controlled by the SW1 signal and the amplifier 1
-5-1, 1-5-2 ,. . . , 1-5-m in response to the INH signal, switches 1-7-1, 1-7-2 ,. . . Are controlled by the SW2 signal.

【0025】図2は、本発明の第1の実施の形態に係る
表示装置の各制御信号のタイミングチャートである。図
2に基づき、第1の実施の形態に係る表示装置における
信号線駆動回路の回路動作について説明する。
FIG. 2 is a timing chart of each control signal of the display device according to the first embodiment of the present invention. The circuit operation of the signal line drive circuit in the display device according to the first embodiment will be described with reference to FIG.

【0026】ある走査線期間における第nの走査線Gn
の駆動時に、信号線S1には負極性の電位−V1が、信
号線S2には正極性の電位+V4が与えられていたとす
る。次の走査線期間に入ると、時刻t0において、SW
2信号、INH信号はともにHIGHレベルとなり、ス
イッチ1−7−1,1−7−2,...はすべて接続さ
れ、アンプ1−5−1,1−5−2,...はすべてハ
イインピーダンスとなる。各スイッチの接続により、信
号線S1とS2とが短絡され、信号線S1及びS2の電
位は(−V1+V4)となる。一方、第1の走査線G1
への各信号線S1,S2,...の画像データは、D/
A変換器1−4−1,1−4−2,...でアナログ信
号に変換され、アナログ信号はアンプ1−5−1,1−
5−2,...に供給される。
The nth scanning line Gn in a certain scanning line period
At the time of driving, it is assumed that the negative potential −V1 is applied to the signal line S1 and the positive potential + V4 is applied to the signal line S2. In the next scanning line period, at time t0, SW
The 2 signal and the INH signal both become HIGH level, and the switches 1-7-1, 1-7-2 ,. . . Are all connected, and amplifiers 1-5-1, 1-5-2 ,. . . Are all high impedance. Due to the connection of each switch, the signal lines S1 and S2 are short-circuited, and the potentials of the signal lines S1 and S2 become (−V1 + V4). On the other hand, the first scanning line G1
To each signal line S1, S2 ,. . . Image data of D /
A converter 1-4-1, 1-4-2 ,. . . Is converted into an analog signal by the amplifier, and the analog signal is converted into an amplifier 1-5-1, 1-
5-2. . . Is supplied to.

【0027】その後、時刻t1において、SW2信号、
INH信号は、ともにLOWレベルとなり、スイッチ1
−7−1,1−7−2,...はすべて開放され、アン
プ1−5−1,1−5−2,...のハイインピーダン
スはすべて解除され、各アンプに供給されたアナログ信
号は各信号線S1,S2,...に供給される。このと
き、第1の走査線G1の制御信号G1はHIGHレベル
となっているため、第1の走査線G1に接続されたTF
T1−11−1,1−11−2,...はオンとなって
おり、第1の走査線G1に接続された各画素1−10−
1,1−10−2,...の補助容量及び液晶容量1−
12−1,1−12−2,...にアナログ信号の書込
みが行われる。信号線S1,S2に供給されたアナログ
信号の電位がそれぞれ+V2,−V3であったとする
と、画素1−10−1,1−10−2にはそれぞれ電位
+V2,−V3のアナログ信号の書込みが行われる。
After that, at time t1, the SW2 signal,
Both INH signals are at LOW level, and switch 1
-7-1, 1-7-2 ,. . . Are all opened and the amplifiers 1-5-1, 1-5-2 ,. . . Of the analog signals supplied to the respective amplifiers are released from the high impedances of the signal lines S1, S2 ,. . . Is supplied to. At this time, since the control signal G1 of the first scanning line G1 is at the HIGH level, the TF connected to the first scanning line G1 is
T1-11-1, 1-11-2 ,. . . Is on, and each pixel 1-10- connected to the first scanning line G1
1, 1-10-2 ,. . . Auxiliary capacity and liquid crystal capacity 1-
12-1, 1-12-2 ,. . . An analog signal is written to. Assuming that the potentials of the analog signals supplied to the signal lines S1 and S2 are + V2 and −V3, respectively, the analog signals of the potentials + V2 and −V3 are written to the pixels 1-10-1 and 1-10-2, respectively. Done.

【0028】時刻t2から次の走査線期間となり、時刻
t2において、SW2信号、INH信号はともにHIG
Hレベルとなり、スイッチ1−7−1,1−7−
2,...はすべて接続され、アンプ1−5−1,1−
5−2,...はすべてハイインピーダンスとなる。各
スイッチの接続により、信号線S1とS2とが短絡さ
れ、信号線S1及びS2の電位は(+V2−V3)とな
る。一方、第2の走査線G2への各信号線S1,S
2,...の画像データは、D/A変換器1−4−1,
1−4−2,...でアナログ信号に変換され、アナロ
グ信号はアンプ1−5−1,1−5−2,...に供給
される。
The next scanning line period starts from time t2, and at time t2, the SW2 signal and the INH signal are both HIG.
It becomes H level, and switches 1-7-1, 1-7-
2,. . . Are all connected, and amplifiers 1-5-1, 1-
5-2. . . Are all high impedance. The signal lines S1 and S2 are short-circuited by the connection of the switches, and the potentials of the signal lines S1 and S2 become (+ V2-V3). On the other hand, the signal lines S1 and S to the second scanning line G2
2,. . . Image data of D / A converter 1-4-1,
1-4-2. . . Is converted into an analog signal by the amplifier 1-5-1, 1-5-2 ,. . . Is supplied to.

【0029】その後、時刻t3において、SW2信号、
INH信号は、ともにLOWレベルとなり、スイッチ1
−7−1,1−7−2,...はすべて開放され、アン
プ1−5−1,1−5−2,...のハイインピーダン
スはすべて解除され、各アンプに供給されたアナログ信
号は各信号線S1,S2,...に供給される。このと
き、第2の走査線G2の制御信号G2はHIGHレベル
となっているため、第2の走査線G2に接続されたTF
T1−13−1,1−13−2,...はオンとなって
おり、第2の走査線G2に接続された各画素1−14−
1,1−14−2,...の補助容量及び液晶容量にア
ナログ信号の書込みが行われる。信号線S1,S2に供
給されたアナログ信号の電位がそれぞれ−V5,+V6
であったとすると、画素1−14−1,1−14−2に
はそれぞれ電位−V5,+V6のアナログ信号の書込み
が行われる。
Thereafter, at time t3, the SW2 signal,
Both INH signals are at LOW level, and switch 1
-7-1, 1-7-2 ,. . . Are all opened and the amplifiers 1-5-1, 1-5-2 ,. . . Of the analog signals supplied to the respective amplifiers are released from the high impedances of the signal lines S1, S2 ,. . . Is supplied to. At this time, since the control signal G2 of the second scanning line G2 is at the HIGH level, the TF connected to the second scanning line G2 is
T1-13-1, 1-13-2 ,. . . Is on and each pixel 1-14-connected to the second scanning line G2
1, 1-14-2 ,. . . An analog signal is written to the auxiliary capacitor and the liquid crystal capacitor. The potentials of the analog signals supplied to the signal lines S1 and S2 are −V5 and + V6, respectively.
Then, the analog signals of potentials −V5 and + V6 are written to the pixels 1-14-1 and 1-14-2, respectively.

【0030】通常の画像データにおいては、相互に隣接
する画素値同士は相関性があり、
In normal image data, pixel values adjacent to each other have a correlation,

【数1】 であるため、時刻t0からt1までの期間、時刻t2か
らt3までの期間、...は、信号線S1,S
2,...の電位はそれぞれほぼ0Vとなる。
[Equation 1] Therefore, the period from time t0 to t1, the period from time t2 to t3 ,. . . Are signal lines S1 and S
2,. . . The respective potentials of the above are approximately 0V.

【0031】スイッチ1−7−1がないときは、アンプ
1−5−1は信号線S1の電位が−V1から+V2とな
るまで信号線S1を充電しなければならないが、スイッ
チ1−7−1の操作により、信号線S1の電位は一旦−
V1とV4との中間電位(ほぼ0V)まで戻されるた
め、アンプ1−5−1は信号線S1の電位が0Vから+
V2となるまで信号線S1を充電すればよい。従って、
アンプ1−5−1の消費電力は半減する。同様に、他の
各信号線の充電量、従って他の各アンプの消費電力も半
減する。
When the switch 1-7-1 is not provided, the amplifier 1-5-1 must charge the signal line S1 until the potential of the signal line S1 changes from -V1 to + V2, but the switch 1-7- By the operation of 1, the potential of the signal line S1 is once-
Since the potential is returned to an intermediate potential between V1 and V4 (approximately 0 V), the potential of the signal line S1 of the amplifier 1-5-1 changes from 0 V to +.
The signal line S1 may be charged until it becomes V2. Therefore,
The power consumption of the amplifier 1-5-1 is halved. Similarly, the charge amount of each of the other signal lines, and thus the power consumption of each of the other amplifiers, is also halved.

【0032】図3は、本発明の第1の実施の形態に係る
表示装置における信号線駆動回路中のアンプ及び信号線
間短絡回路の部分の一例の回路構成図である。
FIG. 3 is a circuit configuration diagram of an example of an amplifier and a short circuit between signal lines in the signal line drive circuit in the display device according to the first embodiment of the present invention.

【0033】信号線S1,S2,...にアナログ信号
を供給するアンプ3−1,3−2,...と、アンプ3
−1,3−2,...からのアナログ信号が入力され、
/INH信号でアナログ信号の出力を制御するMOSF
ET4−1,4−2,...と、信号線S1及びS2、
信号線S3及びS4にそれぞれ接続され、SW2信号で
信号線S1とS2、信号線S3とS4の短絡・開放を制
御するMOSFET5−1,5−2,...とから構成
されている。
The signal lines S1, S2 ,. . . Amplifiers 3-1, 3-2 ,. . . And amplifier 3
-1, 3-2. . . The analog signal from is input,
MOSF that controls analog signal output with / INH signal
ET4-1, 4-2 ,. . . And signal lines S1 and S2,
MOSFETs 5-1 5-2, which are respectively connected to the signal lines S3 and S4 and control the short circuit / opening of the signal lines S1 and S2 and the signal lines S3 and S4 by the SW2 signal. . . It is composed of

【0034】上記の例においては、時刻t0からt1ま
での期間、時刻t2からt3までの期間、...は、M
OSFET4−1,4−2,...はオフとなり、MO
SFET5−1,5−2,...はオンとなって、信号
線S1とS2、信号線S3とS4はそれぞれ短絡され、
各信号線の電位は中間電位(約0V)とされる。各信号
線の電位が中間電位とされた後、アンプ3−1,3−
2,...から信号線にアナログ信号が供給される。
In the above example, the period from time t0 to t1, the period from time t2 to t3 ,. . . Is M
OSFETs 4-1, 4-2 ,. . . Turns off and MO
SFET5-1, 5-2 ,. . . Is turned on, the signal lines S1 and S2 and the signal lines S3 and S4 are short-circuited,
The potential of each signal line is an intermediate potential (about 0 V). After the potential of each signal line is set to the intermediate potential, the amplifiers 3-1 and 3-
2,. . . Supplies an analog signal to the signal line.

【0035】図3においては、スイッチとしてMOSF
ETを用いた例を示したが、CMOSアナログスイッチ
等同様の機能を有する他の素子を用いても良い。
In FIG. 3, MOSF is used as a switch.
Although the example using the ET is shown, other elements having a similar function such as a CMOS analog switch may be used.

【0036】図4は、本発明の第2の実施の形態に係る
表示装置の回路構成図である。第1の実施の形態に係る
表示装置とほぼ同様の構成を有しているが、相互に隣接
するすべての信号線同士S1とS2、S2とS3、S3
とS4、...をそれぞれ短絡するスイッチ1−7’−
1,1−7’−2,...が配設されている点が異なっ
ている。
FIG. 4 is a circuit configuration diagram of a display device according to the second embodiment of the present invention. The display device according to the first embodiment has almost the same configuration as that of the display device according to the first embodiment, but all the signal lines S1 and S2, S2 and S3, and S3 that are adjacent to each other.
And S4 ,. . . Switches for short-circuiting each
1,1-7'-2 ,. . . Are different in that they are arranged.

【0037】第1の実施の形態においては、相互に隣接
する信号線同士S1とS2、S3とS4、...をそれ
ぞれ一組とし、それらをそれぞれ短絡することにより、
2本の信号線ごとに中間電位を得ていたのに対し、第2
の実施の形態においては、すべての信号線間を短絡して
中間電位を得るようにしているため、各信号線の中間電
位を均一化することができ、駆動時におけるバランスが
良好なものとなる。
In the first embodiment, mutually adjacent signal lines S1 and S2, S3 and S4 ,. . . By making them one set and shorting them respectively,
While the intermediate potential was obtained for every two signal lines, the second
In the embodiment of the present invention, all the signal lines are short-circuited to obtain the intermediate potential, so that the intermediate potentials of the respective signal lines can be made uniform and good balance can be achieved during driving. .

【0038】尚、以上の各実施の形態における信号線駆
動回路は、表示部と別々に製造する構成としても良く、
また、表示部と一体として同一の素子形成工程で製造す
る構成としても良い。また、上述したように、本発明の
構成は、HV反転駆動の表示装置のみならずVライン反
転駆動の表示装置においても適用することができる。さ
らに、HV反転駆動又はVライン反転駆動において、複
数信号線ごと又は複数走査線ごとに、印加する信号の極
性を反転させる場合においても、本発明の構成を適用す
ることができる。
The signal line drive circuit in each of the above embodiments may be manufactured separately from the display section,
Further, it may be configured to be manufactured integrally with the display unit in the same element forming process. Further, as described above, the configuration of the present invention can be applied not only to the HV inversion driving display device but also to the V line inversion driving display device. Further, in the HV inversion drive or the V line inversion drive, the configuration of the present invention can be applied even when the polarity of the signal to be applied is inverted for each of the plurality of signal lines or each of the plurality of scanning lines.

【0039】本発明の第3の実施の形態に係る表示装置
は、図4の第2の実施の形態に係る表示装置と同様の構
成を有しているが、信号線同士を短絡するスイッチ1−
7−1,1−7−2,1−7−3,1−7−4,…の開
閉のタイミングが異なる。
The display device according to the third embodiment of the present invention has the same structure as the display device according to the second embodiment of FIG. 4, but the switch 1 for short-circuiting the signal lines is used. −
The opening and closing timings of 7-1, 1-7-2, 1-7-3, 1-7-4, ... Are different.

【0040】第2の実施の形態においては、すべての信
号線を短絡したが、第3の実施の形態では短絡する信号
線の組み合わせを変え、中間電位を得る。即ち、ある走
査線期間はスイッチ1−7−1,1−7−3,…を短絡
し、次の走査線期間は1−7−2,1−7−4,…を短
絡する。このように短絡する信号線の組み合わせを変え
ることにより、すべての信号線を短絡する場合と同様に
中間電位を均一化することができる。
In the second embodiment, all signal lines are short-circuited, but in the third embodiment, the combination of short-circuited signal lines is changed to obtain an intermediate potential. That is, the switches 1-7-1, 1-7-3, ... Are short-circuited during a certain scanning line period, and the switches 1-7-2, 1-7-4, ... Are short-circuited during the next scanning line period. By changing the combination of the signal lines to be short-circuited in this way, the intermediate potential can be made uniform as in the case where all the signal lines are short-circuited.

【0041】図5は、本発明の第4の実施の形態に係る
表示装置の回路構成図である。第1の実施の形態に係る
表示装置とほぼ同様の構成を有しているが、短絡する信
号線の組み合わせを変えている。カラー型液晶表示装置
の場合、信号線は例えば、R,G,B,R,G,B…の
順番で配置されており、対応する各画素にカラー信号が
書き込まれる。そこで、第4の実施の形態においては、
次のように信号線の短絡を行う。即ち、R,G,Bの3
本の信号線を、信号線の一構成単位とすると、スイッチ
1−7−1は第1の構成単位のR信号線と第1の構成単
位に対して隣接する第2の構成単位のR信号線とを短絡
し、スイッチ1−7−2は第1の構成単位のG信号線と
第2の構成単位のG信号線とを短絡し、スイッチ1−7
−3は第1の構成単位のB信号線と第2の構成単位のB
信号線とを短絡し、以下同様に、各スイッチは、相互に
隣接する2つの構成単位に属する同一色の信号線をそれ
ぞれ短絡する。
FIG. 5 is a circuit configuration diagram of a display device according to the fourth embodiment of the present invention. Although it has almost the same configuration as the display device according to the first embodiment, the combination of short-circuited signal lines is changed. In the case of a color type liquid crystal display device, the signal lines are arranged in the order of R, G, B, R, G, B, ... And a color signal is written in each corresponding pixel. Therefore, in the fourth embodiment,
Short the signal lines as follows. That is, R, G, B 3
Assuming that the present signal line is one structural unit of the signal line, the switch 1-7-1 includes the R signal line of the first structural unit and the R signal of the second structural unit adjacent to the first structural unit. The switch 1-7-2 short-circuits the G signal line of the first constituent unit and the G signal line of the second constituent unit by short-circuiting the switch 1-7-2.
-3 is the B signal line of the first constituent unit and the B signal line of the second constituent unit
Similarly, each switch short-circuits a signal line of the same color belonging to two constituent units adjacent to each other.

【0042】カラー信号の場合、各色信号は当該色信号
に対して隣接する色信号との相関性が高く、従って、各
色信号に対応する信号線を同一色ごとに相互に短絡する
ことにより、0Vに近い中間電圧を得ることができる。
In the case of a color signal, each color signal has a high correlation with an adjacent color signal with respect to the color signal. Therefore, by connecting the signal lines corresponding to each color signal to each other for each same color, 0V is obtained. It is possible to obtain an intermediate voltage close to.

【0043】[0043]

【発明の効果】本発明に係る表示装置によれば、断続す
る書込み動作間において、すべての信号線間を短絡しな
がら順次各画素に書込みを行うことにより各書込み動作
直前の各信号線電位を正極性・負極性信号電位の均一化
された中間電位としたので、信号線駆動回路の消費電力
を半減した高品質表示の表示装置を提供することができ
る。
According to the display device of the present invention, during intermittent write operations, each signal line potential immediately before each write operation is written by sequentially writing to each pixel while short-circuiting all signal lines. Since the positive and negative polarity signal potentials are equalized to the intermediate potential, it is possible to provide a display device of high quality display in which the power consumption of the signal line driving circuit is halved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態に係る表示装置の回
路構成図。
FIG. 1 is a circuit configuration diagram of a display device according to a first embodiment of the present invention.

【図2】本発明の第1の実施の形態に係る表示装置の各
制御信号のタイミングチャート。
FIG. 2 is a timing chart of each control signal of the display device according to the first embodiment of the present invention.

【図3】本発明の第1の実施の形態に係る表示装置にお
ける信号線駆動回路中のアンプ及び信号線短絡回路の部
分の一例の回路構成図。
FIG. 3 is a circuit configuration diagram of an example of a portion of an amplifier and a signal line short circuit in a signal line drive circuit in the display device according to the first embodiment of the present invention.

【図4】本発明の第2の実施の形態に係る表示装置の回
路構成図。
FIG. 4 is a circuit configuration diagram of a display device according to a second embodiment of the present invention.

【図5】本発明の第4の実施の形態に係る表示装置の回
路構成図。
FIG. 5 is a circuit configuration diagram of a display device according to a fourth embodiment of the present invention.

【図6】アレイ基板の概略構成図。FIG. 6 is a schematic configuration diagram of an array substrate.

【図7】液晶表示装置の画素部の断面構造を模式的に表
した説明図。
FIG. 7 is an explanatory diagram schematically showing a cross-sectional structure of a pixel portion of a liquid crystal display device.

【符号の説明】[Explanation of symbols]

501 TFT 502 補助容量CS 503 液晶容量CL 504 データ線駆動回路 505 ゲート線駆動回路 506 対向電極 507 データ線 508 ゲート線 509 画素 601、610 ガラス基板 602 カラーフィルタ 603 ブラックマトリクス 604、615 保護膜 605 対向電極 606、616 配向膜 607 液晶層 611 ゲート電極 612 ゲート絶縁膜 613 アモルファスシリコン 614 画素電極 617 ソース電極 618 ドレイン電極 501 TFT 502 Auxiliary capacitance CS 503 Liquid crystal capacitance CL 504 Data line drive circuit 505 Gate line drive circuit 506 Counter electrode 507 Data line 508 Gate line 509 Pixels 601, 610 Glass substrate 602 Color filter 603 Black matrix 604, 615 Protective film 605 Counter electrode 606, 616 Alignment film 607 Liquid crystal layer 611 Gate electrode 612 Gate insulating film 613 Amorphous silicon 614 Pixel electrode 617 Source electrode 618 Drain electrode

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】複数の信号線と複数の走査線との交差部
に、前記信号線及び前記走査線に接続されてそれぞれ配
設されたスイッチング素子と、 前記スイッチング素子のそれぞれに接続されて配設さ
れ、前記走査線への走査信号入力に応じて前記スイッチ
ング素子を介して、前記信号線からの信号が印加される
画素電極と、 一の前記画素電極に印加される前記信号の極性と、前記
一の前記画素電極に対して前記走査線方向に隣接する他
の画素電極に印加される前記信号の極性とが相互に逆極
性の信号となるように、前記複数の信号線を駆動する信
号線駆動回路及び前記複数の走査線を駆動する走査線駆
動回路と、 前記画素電極への各信号印加動作前に、一の前記信号線
と前記一の前記信号線に対して隣接する他の信号線とを
相互に短絡し得るように各信号線間に配設された信号線
間短絡回路と、 前記画素電極と前記画素電極に対向する対向電極との間
に挟持され、前記画素電極と前記対向電極との間の印加
電圧により駆動される液晶分子を含む液晶層とを備えた
ことを特徴とする表示装置。
1. A switching element connected to each of the signal line and the scanning line at an intersection of a plurality of signal lines and a plurality of scanning lines, and a switching element connected to each of the switching elements. A pixel electrode to which a signal from the signal line is applied via the switching element in response to a scan signal input to the scan line, and a polarity of the signal applied to the one pixel electrode, A signal for driving the plurality of signal lines so that the polarities of the signals applied to the other pixel electrodes adjacent to the one pixel electrode in the scanning line direction are mutually opposite polarities. A line driving circuit and a scanning line driving circuit that drives the plurality of scanning lines; and, before each signal application operation to the pixel electrode, one signal line and another signal adjacent to the one signal line. You can short the wires to each other A signal line short circuit provided between the signal lines, and sandwiched between the pixel electrode and a counter electrode facing the pixel electrode, by an applied voltage between the pixel electrode and the counter electrode. A display device comprising a liquid crystal layer containing driven liquid crystal molecules.
【請求項2】複数の信号線と複数の走査線との交差部
に、前記信号線及び前記走査線に接続されてそれぞれ配
設されたスイッチング素子と、 前記スイッチング素子のそれぞれに接続されて配設さ
れ、前記走査線への走査信号入力に応じて前記スイッチ
ング素子を介して、前記信号線からの信号が印加される
画素電極と、 一の前記画素電極に印加される前記信号の極性と、前記
一の前記画素電極に対して前記信号線方向及び前記走査
線方向に隣接する他の画素電極に印加される前記信号の
極性とが相互に逆極性の信号となるように、前記複数の
信号線を駆動する信号線駆動回路及び前記複数の走査線
を駆動する走査線駆動回路と、 前記画素電極への各信号印加動作前に、一の前記信号線
と前記一の前記信号線に対して隣接する他の信号線とを
相互に短絡し得るように各信号線間に配設された信号線
間短絡回路と、 前記画素電極と前記画素電極に対向する対向電極との間
に挟持され、前記画素電極と前記対向電極との間の印加
電圧により駆動される液晶分子を含む液晶層とを備えた
ことを特徴とする表示装置。
2. A switching element connected to each of the signal line and the scanning line at an intersection of a plurality of signal lines and a plurality of scanning lines, and a switching element connected to each of the switching elements. A pixel electrode to which a signal from the signal line is applied via the switching element in response to a scan signal input to the scan line, and a polarity of the signal applied to the one pixel electrode, The plurality of signals so that the polarities of the signals applied to the other pixel electrodes adjacent to the one pixel electrode in the signal line direction and the scanning line direction are opposite to each other. A signal line driving circuit for driving a line and a scanning line driving circuit for driving the plurality of scanning lines; and, before each signal application operation to the pixel electrode, with respect to the one signal line and the one signal line. With other adjacent signal lines A signal line short circuit provided between the signal lines so as to be short-circuited to each other, and sandwiched between the pixel electrode and a counter electrode facing the pixel electrode, and the pixel electrode and the counter electrode. And a liquid crystal layer containing liquid crystal molecules driven by an applied voltage between the display devices.
【請求項3】複数の信号線と複数の走査線との交差部
に、前記信号線及び前記走査線に接続されてそれぞれ配
設されたスイッチング素子と、 前記スイッチング素子のそれぞれに接続されて配設さ
れ、前記走査線への走査信号入力に応じて前記スイッチ
ング素子を介して、前記信号線からの信号が印加される
画素電極と、 前記走査線方向に連続して隣接する所定個数の前記画素
電極の群の一に印加される前記信号の極性と、前記一の
群に対して前記走査線方向に隣接する他の群に印加され
る前記信号の極性とが相互に逆極性の信号となるよう
に、前記複数の信号線を駆動する信号線駆動回路及び前
記複数の走査線を駆動する走査線駆動回路と、 前記画素電極への各信号印加動作前に、一の前記信号線
と前記一の前記信号線に対して隣接する他の信号線とを
相互に短絡し得るように各信号線間に配設された信号線
間短絡回路と、 前記画素電極と前記画素電極に対向する対向電極との間
に挟持され、前記画素電極と前記対向電極との間の印加
電圧により駆動される液晶分子を含む液晶層とを備えた
ことを特徴とする表示装置。
3. A switching element connected to each of the signal line and the scanning line at an intersection of the plurality of signal lines and the plurality of scanning lines, and a switching element connected to each of the switching elements. A predetermined number of pixels that are provided adjacent to a pixel electrode to which a signal from the signal line is applied via the switching element in response to a scan signal input to the scan line The polarities of the signals applied to one of the electrode groups and the polarities of the signals applied to another group adjacent to the one group in the scanning line direction are signals having mutually opposite polarities. As described above, a signal line driving circuit that drives the plurality of signal lines and a scanning line driving circuit that drives the plurality of scanning lines, and one signal line and one of the signal lines before applying each signal to the pixel electrode. Other adjacent to the signal line of A signal line short circuit provided between the signal lines so as to short-circuit the signal lines with each other, and sandwiched between the pixel electrode and a counter electrode facing the pixel electrode, and the pixel electrode A display device comprising: a liquid crystal layer containing liquid crystal molecules driven by an applied voltage between the counter electrode.
【請求項4】複数の信号線と複数の走査線との交差部
に、前記信号線及び前記走査線に接続されてそれぞれ配
設されたスイッチング素子と、 前記スイッチング素子のそれぞれに接続されて配設さ
れ、前記走査線への走査信号入力に応じて前記スイッチ
ング素子を介して、前記信号線からの信号が印加される
画素電極と、 前記信号線方向及び前記走査線方向に連続して隣接する
所定個数の前記画素電極の方形状の群の一に印加される
前記信号の極性と、前記一の群に対して前記信号線方向
及び前記走査線方向に隣接する他の群に印加される前記
信号の極性とが相互に逆極性の信号となるように、前記
複数の信号線を駆動する信号線駆動回路及び前記複数の
走査線を駆動する走査線駆動回路と、 前記画素電極への各信号印加動作前に、一の前記信号線
と前記一の前記信号線に対して隣接する他の信号線とを
相互に短絡し得るように各信号線間に配設された信号線
間短絡回路と、 前記画素電極と前記画素電極に対向する対向電極との間
に挟持され、前記画素電極と前記対向電極との間の印加
電圧により駆動される液晶分子を含む液晶層とを備えた
ことを特徴とする表示装置。
4. A switching element connected to each of the signal line and the scanning line at an intersection of the plurality of signal lines and the plurality of scanning lines, and a switching element connected to each of the switching elements. And a pixel electrode to which a signal from the signal line is applied via the switching element according to a scanning signal input to the scanning line, and is continuously adjacent to the pixel electrode in the signal line direction and the scanning line direction. The polarity of the signal applied to one of a predetermined number of the rectangular groups of the pixel electrodes, and the polarity applied to another group adjacent to the one group in the signal line direction and the scanning line direction. A signal line driving circuit that drives the plurality of signal lines and a scanning line driving circuit that drives the plurality of scanning lines so that the polarities of the signals are mutually opposite polarities, and each signal to the pixel electrode. Before applying operation, A signal line and a signal line short-circuiting circuit arranged between the signal lines so that the other signal line adjacent to the one signal line can be short-circuited to each other; A display device, comprising: a liquid crystal layer sandwiched between opposed counter electrodes, the liquid crystal layer including liquid crystal molecules driven by an applied voltage between the pixel electrode and the counter electrode.
【請求項5】請求項1又は2のいずれかに記載の表示装
置において、前記各信号線間に配設された前記信号線間
短絡回路を、一信号線間おきに除去したことを特徴とす
る表示装置。
5. The display device according to claim 1, wherein the signal line short-circuiting circuit arranged between the signal lines is removed every other signal line. Display device.
【請求項6】請求項3又は4のいずれかに記載の表示装
置において、前記各信号線間に配設された前記信号線間
短絡回路のうち、2つの前記群からなる一の組合せと他
の組合せとの間の前記信号線間短絡回路を除去したこと
を特徴とする表示装置。
6. The display device according to claim 3, wherein the signal line short-circuiting circuit arranged between the signal lines includes one of the two groups and another combination. The display device characterized in that the short circuit between the signal lines between the above-mentioned combination is removed.
【請求項7】請求項1乃至6のいずれかに記載の表示装
置において、前記信号線間短絡回路は、MOSFETス
イッチであることを特徴とする表示装置。
7. The display device according to claim 1, wherein the signal line short-circuit circuit is a MOSFET switch.
JP5627396A 1996-03-13 1996-03-13 Display device Pending JPH09243998A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5627396A JPH09243998A (en) 1996-03-13 1996-03-13 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5627396A JPH09243998A (en) 1996-03-13 1996-03-13 Display device

Publications (1)

Publication Number Publication Date
JPH09243998A true JPH09243998A (en) 1997-09-19

Family

ID=13022487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5627396A Pending JPH09243998A (en) 1996-03-13 1996-03-13 Display device

Country Status (1)

Country Link
JP (1) JPH09243998A (en)

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* Cited by examiner, † Cited by third party
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JPH10326090A (en) * 1997-05-23 1998-12-08 Sony Corp Active matrix display device
JPH1185115A (en) * 1997-07-16 1999-03-30 Seiko Epson Corp Liquid crystal and its driving method, projection type display device using it and electronic equipment
JP2001134245A (en) * 1999-11-10 2001-05-18 Sony Corp Liquid crystal display device
KR20010060834A (en) * 1999-12-28 2001-07-07 박종섭 Method of sharing two-level voltage in tft-lcd and circuit thereof
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