JPH05313605A - Multi-gradation active matrix liquid crystal driving cirucit - Google Patents

Abstract

PURPOSE:To prevent the increase in a circuit size caused by the increase in the number of gradation. CONSTITUTION:The contents of resisters 231 and 232 are successively selected by a selector 261, a D/A converter, which consists of a reference voltage source 50, a decoder 241 and a selector 251 converts these to analog voltages and these voltages are successively supplied to two stage sample and hold circuits 271 and 272, respectively in synchronization with the selection. Thus, the total number of analog switches, which constitute selectors 251 and 253 and are the major cause of a circuit size increase as the gradation number is increased, is reduced to less than 1/2 of the conventional number. Moreover, data lines X1 to X4 which have relatively large distributed capacitances are not directly driven through these switches and analog switches, which have larger on resistances than conventional ones, are used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-gradation active matrix liquid crystal drive circuit.

[0002]

2. Description of the Related Art An active matrix driving type liquid crystal display device using thin film transistors (TFTs) has a relatively high display speed and excellent display quality.
It is expected as a display device that replaces the T display device.

FIG. 11 shows a conventional multi-gradation active matrix liquid crystal drive circuit. For simplification of description, the liquid crystal display panel 10 is shown as a monochrome display of 4 × 4 pixels in FIG.

The data lines X1 to X1 of the liquid crystal display panel 10
To the X4, gradation display data for one row is simultaneously supplied from the output end of the data driver 20A, and the liquid crystal display panel 10
Row selection signals are line-sequentially supplied to the scanning lines Y1 to Y4 from the output end of the scanning driver 30. The data driver 20A and the scan driver 30 are controlled by the control circuit 40A. The control circuit 40A generates various control signals based on a horizontal synchronizing signal HS, a vertical synchronizing signal VS, and a clock CK from the outside.

The liquid crystal display panel 10 has a liquid crystal pixel C as shown in FIG.
One end electrode of ij (i = 1 to 4, j = 1 to 4) is made common, and the other end electrode is connected to the data line Xj via the thin film transistor Qij. Thin film transistor Qij
Is connected to the scanning line Yi.

In FIG. 11, the data driver 20A
Is a shift register 21 that generates latch pulses SP1 to SP4 and two-stage buffer registers 221 to 224.
And 231 to 234, decoders 241 to 244 and selectors 251 to 254 for converting the contents of the registers 231 to 234 into analog data.

The shift register 21 has a horizontal synchronizing signal HS.
An initial pulse T1 having the same cycle as the above is received at the serial data input terminal, this is shifted by the clock CK1 through which the clock CK is passed through the buffer gate, and the latch pulses SP1 to SP4 are sequentially output from each bit.

An N-bit (2 ^N gradation) digital video signal D is written and held in the registers 221 to 224 at the timing of the latch pulses SP1 to SP4. After the digital video signal D is written in the register 224, the contents of the registers 221 to 224 are simultaneously written and held in the registers 231 to 234 at the timing of the latch pulse T2. The contents of the registers 231 to 234 are decoded by the decoders 241 to 244, respectively. This decoder 2
4i (i = 1 to 4) outputs, the number of M selectors 25i shown in FIG. 12 (M = 2 ^N , N = 3, M = in FIG. 12).
Any one of 8) analog switches is selectively turned on. The reference voltages V1 to VM from the external reference voltage source 50 are different from each other at one end of each analog switch.
Is supplied. The other ends of all the analog switches of the selector 25i are commonly connected to the data line Xi of the liquid crystal display panel 10. Therefore, the data line X
A multi-gradation display voltage according to the contents of the registers 231 to 234 is applied to 1 to X4.

On the other hand, the scan driver 30 includes buffer gates 31 to 34 and a shift register 35, and the output ends of the bits of the shift register 35 are connected to the input ends of the buffer gates 31 to 34. The output ends of the buffer gates 31 to 34 are connected to the scan lines Y1 to Y4 of the liquid crystal display panel 10, respectively. The shift register 35 has an initial pulse T of the same cycle as the vertical synchronizing signal VS.
3 is supplied to the serial data input terminal and is shifted by the clock CK2 having the same cycle as the horizontal synchronizing signal HS.

First, the thin film transistors Q11 to Q14 are turned on and the thin film transistors Q21 to Q44 are turned off.
Registers 231-2 are provided in the liquid crystal pixels C11-C14 of the first row.
The gradation display voltage for one row is written according to the contents of 34. In the same manner, the gradation display voltage is written in the liquid crystal display panel 10 line-sequentially.

[0011]

Liquid crystal display panel 10
11 is 4 × 4 pixels for simplification in FIG. 11, but is actually 640 × 480 pixels. Furthermore, in order to display in full color, it is necessary to set the number of gradations of each of R (red), G (green) and B (blue) to 64, and the analog switches constituting the selectors 251 to 254 are actually the analog switches. 64 × 3 × 640 = 1222880 pieces are required.

On the other hand, the distributed capacitance between the data line Xi (i = 1 to 4) and the common electrode, the distributed capacitance at the intersection of the data line Xi and the scanning lines Y1 to Y4, and the distributed resistance of the data line Xi. Also, the data line Xi is charged with a time constant determined by the resistance of one analog switch which is turned on by the selector 25i. In order to display high quality, it is necessary to reduce the on-resistance of all analog switches constituting the selectors 251 to 254, that is, to increase the on-chip area of the analog switches so that the startup at the time of charging is rapid. is there.

For this reason, the data driver 20B is replaced by an LSI.
As the number of chips increases, the chip area or the number of chips increases, the frame area around the liquid crystal display panel 10 increases, and the cost increases.

In view of the above problems, an object of the present invention is to provide a multi-gradation active matrix liquid crystal drive circuit capable of suppressing an increase in circuit scale accompanying an increase in the number of gradations.

[0015]

A multi-gradation active matrix liquid crystal drive circuit according to the present invention will be described with reference to the reference numerals of corresponding constituent elements in the drawings.

In this multi-gradation active matrix liquid crystal drive circuit, one end electrodes of the liquid crystal pixels C11 to C44 are made common, and the other end electrodes are connected to the data lines X1 to X4 via the switch elements Q11 to Q44, and the data line X1. ~
The liquid crystal display panel 10 in which the control input terminals of the switch elements Q11 to Q44 are connected to the scanning lines Y1 to Y4 crossing X4 is driven to perform multi-gradation display.

In the first invention, for example, as shown in FIGS. 1 to 5, the first storage means 2 in which the digital video signal D represented by the grayscale display data of one color is written and temporarily stored.
21 to 224 and the selected j-th group when the gradation display data for one line stored in the first storage means 221 to 224 is divided into 1st to qth groups for every p pixels, Selector 2 for reading the i-th gradation display data
31-234, 261, 263 and selecting means 231-2
Digital / analog conversion means 50, 241, 243, 251, 253 for converting the gradation display data of each pixel read out from 34, 261, 263 into an analog voltage, and sample hold for each data line X1 to X4. Circuits 271 to 274 are provided, the input ends of the p sample and hold circuits are commonly connected to the output ends of one digital / analog converting means 50, 24j, 25j (j = 1, 3), and each sample and hold circuit is connected. The circuits 271 to 274 are provided with first and second capacitors CA and CB capable of writing two continuous input voltages, and the output ends thereof are data lines X.
1 to X4 connected to the sample hold circuits 271-2
74 and the first storage means 221 to 224 to perform the writing, and the selection means 231 to 234, 261 and 263 to read the i-th gradation display data of the 1st to qth groups for q pixels. , The reading is performed during one horizontal scanning time by i =
1 to p are repeated p times, and the i-th sample and hold circuit 27i is added to the p sample and hold circuits.
Of the first or second capacitors CA, CB of the analog voltage is written, and this is performed for i = 1 to p, and the analog voltage is written to the other of the first or second capacitors CA, CB. The control means 40B and 21 for applying the applied voltage to the data lines X1 to X4 as the output voltage of the sample hold circuits 271 to 274 are provided.

According to the first aspect of the present invention, the number of analog switches constituting the digital / analog converting means, which is a main cause of the increase in the circuit scale with the increase in the number of gradations, is reduced to half that of the conventional one.
It can be reduced to: In addition, the data line X1 having a relatively large distributed capacitance is provided through the analog switch.
Since ~ X4 is not directly driven, the analog switch having a larger on-resistance than the conventional one can be used. Therefore, it is possible to reduce the required chip area of the analog switch, and it is possible to suppress an increase in circuit scale due to an increase in the number of gradations.

In the first aspect of the first aspect of the invention, as shown in FIGS. 1 and 4, for example, the selection means is the first storage means 221-2.
Second storage means 231, which are provided for each of the 24 groups and in which the gradation display data of the group is written
234 and selectors 261, 263 which are provided for each group of the second storage means 231-234 and read out one selected gradation display data from the group, and the control means 40B, 21 is the first storage means 221 to
After the gradation display data for one line is written in 224, the gradation display data of the group is stored in the second storage unit 2.
31 to 234, and the second storage means 231 to 23
The i-th gradation display data is read from each of the four groups, and the reading is repeated p times for i = 1 to p during one horizontal scanning time.

In the second aspect of the first invention, for example, as shown in FIG. 6, the selecting means is provided for each group of the first storing means 221-224, and the gradation display data of the group is written. Shift registers 281 to 284 for reading out the gradation display data for one pixel on one end side, and the control units 40C and 21 are the first storage units 221 to 221.
After the gradation display data for one line is written in 224, the gradation display data of the group is written in the shift registers 281-284, and the shift register 281
To 284 to supply shift pulses to the shift register 28
By shifting the gradation display data stored in Nos. 1 to 284 by one pixel to the one end side, the gradation display data of the next pixel is read from the one end side, and the one pixel shift is performed by one. Repeat p times during the horizontal scan time.

In the multi-gradation active matrix liquid crystal drive circuit of the second invention, for example, as shown in FIGS. 7, 8, 3, and 5, a digital video signal in which one color is represented by gradation display data of N bits is used. First storage means 51 to 54 in which D is written and temporarily stored, and the gradation display data for one line stored in the first storage means 51 to 54 are assigned to p-pixel groups 1 to q Selecting means 60 for reading the i-th gradation display data from the selected j-th group when divided into
And the second storage means 22 in which the gradation display data for q pixels read from the selection means 60 is written and temporarily stored.
1, 223, 231, 233 and the second storage means 231,
Digital / analog conversion means 50, 2 for converting the gradation display data of each pixel stored in 233 into an analog voltage.
41, 243, 251, 253 and each data line X1
To X4 are provided with sample and hold circuits 271 to 274, and the input terminals of the p sample and hold circuits are commonly used as one digital / analog conversion means 50, 24.
The sample and hold circuits 271 to 274 are connected to the output terminals of j and 25j (j = 1 and 3), and each of the sample and hold circuits 271 to 274 can write two consecutive input voltages.
Sample-and-hold circuits 271 to 274 having CBs and having output terminals connected to the data lines X1 to X4, first storage means 51 to 54, and second storage means 221, 223, and 23.
1, 233 are caused to perform the writing, and the selecting means 60 is caused to sequentially read the i-th gradation display data of the 1st to qth groups by q pixels, and the reading is performed during one horizontal scanning time. = 1 to p times, the analog voltage is written to one of the first and second capacitors CA and CB of the i-th sample and hold circuit for the p sample and hold circuits. For i = 1 to p,
Control means 40D, 21 for applying the voltage written in the other of the first or second capacitors CA, CB to the data lines X1 to X4 as the output voltage of the sample hold circuits 271 to 274.

According to the second aspect of the present invention, the number of analog switches constituting the digital / analog converting means, which is a main cause of the increase in the circuit scale with the increase in the number of gradations, is reduced to half that of the conventional one.
It can be reduced to: In addition, the data line X1 having a relatively large distributed capacitance is provided through the analog switch.
Since ~ X4 is not directly driven, the analog switch having a larger on-resistance than the conventional one can be used. Therefore, it is possible to reduce the required chip area of the analog switch, and it is possible to suppress an increase in circuit scale due to an increase in the number of gradations.

By arranging the first storage means 51 to 54 and the selection means 60 outside the data driver,
Since the first storage means 51 to 54 and the selection means 60 can be shared by a plurality of LSIs constituting the data driver, the circuit scale of the entire multi-gradation active matrix liquid crystal drive circuit can be made smaller than that of the first invention. Is possible.

In the first aspect of the second aspect of the invention, as shown in FIGS. 7 and 8, for example, the second storage means has the second A storage having a storage capacity for storing the gradation display data for the q pixels. Means 221, 223 and second B storage means 231, 23
3, the control means 40D, 21 causes the gradation display data for the q pixels read by the selection means 60 to be written in the second A storage means 221, 223, and then the second A storage means 221, 2B storage means 231 and 2B
33, next, the gradation display data for the q pixels is read out from the second B storage means 231, 233, and the readout is 1
It is repeated p times for i = 1 to p during the horizontal scanning time, and at the same time as the reading, the gradation display data for the next q pixels is written in the second A storage means 221 and 223.

In the case of this configuration, the second B storage means 231,
It is possible to make more data lines correspond to one digital / analog conversion means 50, 24j, 25j (j = 1, 3) than in the case without 233.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 shows a multi-gradation active matrix liquid crystal drive circuit of the first embodiment. 11
The same components as those of the above are given the same reference numerals and the description thereof will be omitted.

This data driver 20B omits the decoders 242 and 244 and the selectors 252 and 254 of FIG. 11, and instead includes selectors 261, 263 and sample hold circuits 271 to 274.

The register 23 is provided at the input end of the selector 261.
The contents of 1 and 232 are supplied, and the selector 261 selects and outputs the contents of the register 231 when the selection control signal T4 is at the high level, and selects the contents of the register 232 when the selection control signal T4 is at the low level. Output. Similarly, the contents of the registers 233 and 234 are supplied to the input end of the selector 263, and the selector 263 receives the selection control signal T4.
Is high level, the contents of the register 233 are selected and output, and when the selection control signal T4 is low level, the register 234 is selected.
Select and output the contents of. This selection control signal T4 is
As shown in FIG. 4, the cycle is the same as the horizontal synchronizing signal HS, the duty ratio is 50%, and it rises in synchronization with the rising edge of the latch pulse T2.

The outputs of the selectors 261 and 263 are supplied to the decoders 241 and 243, respectively.
The outputs of 1 and 243 are used to select the selectors 251 and 253.
One of the analog switches shown in FIG. 2 is selectively turned on for each of the
~ VM (M = 8 in FIG. 2) is supplied to the sample hold circuits 271 and 272 as the voltage VA, and the other
One as the voltage VB and the sample and hold circuits 273 and 2
74.

The sample and hold circuits 271 to 274 have the same structure, and an example of the structure of the sample and hold circuit 271 is shown in FIG.

In this sample hold circuit 27A, two stages of sample hold circuits having the same structure are connected in cascade. In the sample-hold circuit in the previous stage, one end of the capacitor CA and one end of the analog switch SA are connected to the input end of the voltage follower OP1, the other end of the capacitor CA is connected to the ground line, and the other end of the analog switch SA is sample-held. It is the input end of the circuit 27A. In the sample-hold circuit 271 in the latter stage, one end of the capacitor CB and one end of the analog switch SB are connected to the input end of the voltage follower OP2, the other end of the capacitor CB is connected to the ground line, and the other end of the analog switch SB is voltage. The output terminal of the voltage follower OP2 is connected to the output terminal of the follower OP1 and serves as the output terminal of the sample hold circuit 27A.

The analog switch SA of the sample hold circuits 271 and 273 is turned on by the sample pulse T6.
OFF-controlled, sample and hold circuits 272 and 274
The analog switch SA of is controlled to be turned on / off by the sample pulse T7. As shown in FIG. 4, the sample pulse T
6 is the same as the selection control signal T4, and the sample pulse T7 is the inverted level of the sample pulse T6. The analog switches SB of the sample hold circuits 271 to 274 are both on / off controlled by a sample pulse T5 as shown in FIG. These sample pulses T5, T6 and T7 all have the same cycle as the horizontal synchronizing signal HS and are supplied from the control circuit 40B.

Next, the operation of the multi-gradation active matrix liquid crystal drive circuit configured as described above will be described with reference to FIG. The gradation display data for the pixels C11 to C14 on the first line are represented by 11, 12, 13 and 14, respectively, and the gradation display data for the pixels C21 to C24 on the second line are represented by 21, 22, 23 and 24, respectively. Represent In addition, the voltages of the data lines X1 to X4 are set to the voltages VX1 to VX4, respectively.
And

First, the gradation display data 11 to 14 are registered in the register 22 at the timing of the latch pulses SP1 to SP4, respectively.
1 to 224 are written and held. Register 224
After the gradation display data 14 is written in, the contents of the registers 221 to 224 are simultaneously written and held in the registers 231 to 234 at the timing of the latch pulse T2.
At this time, the selection control signal T4 and the sample pulse T6 are at a high level, and the sample pulse T7 is at a low level, and the contents of the registers 231 and 233 are respectively in the selector 261.
And the reference voltages VA and VB selected by the selector 263 and corresponding to the gradation display data 11 and 13 from the reference voltage source 50 are written in the capacitor CA of the sample hold circuit 271 and the capacitor CA of the sample hold circuit 273, respectively. Next, the selection control signal T4 and the sample pulse T6 become low level, the sample pulse T7 becomes high level, the contents of the registers 232 and 234 are selected by the selector 261 and the selector 263, respectively, and the gradation display from the reference voltage source 50 is performed. The reference voltages corresponding to the data 12 and 14 are written in the capacitor CA of the sample hold circuit 272 and the capacitor CA of the sample hold circuit 274, respectively.

Next, by the sample pulse T5, the analog switch SB of the sample hold circuits 271 to 274.
Are turned on for a certain period of time, the terminal voltage of the capacitor CA is written in the capacitor CB, and the gradation display data 11
Analog voltage corresponding to ~ 14 is the data line X
1 to X4. In addition, the sample hold circuit 2
When the voltage is written to 71 to 274, the gray scale display data 21 to 24 of the second line are written and held in the registers 221 to 224 at the timing of the latch pulses SP1 to SP4, respectively.

Thereafter, the above operation is repeated.

According to the first embodiment, the selectors 251, 25, which are the main cause of the increase in the circuit scale with the increase in the number of gradations, are provided.
3 can be halved from the case of FIG. Further, since the data lines X1 to X4 having a relatively large distributed capacitance are not directly driven through the analog switches of the selectors 251 and 253, the selectors 251 and 253 can be configured with analog switches having a larger ON resistance than that of FIG. Therefore, the required chip area of the selector can be reduced, and the increase in the circuit scale of the data driver 20B due to the increase in the number of gradations can be suppressed.

In FIG. 1, one selector 251 is made to correspond to two data lines for convenience of explanation, but how many data lines can be made to correspond to one selector 251 depends on the selector 251. It depends on the time constant determined by the combined ON resistance of one analog switch and the ON resistance of the analog switch SA in FIG. 3 and the capacitance of the capacitor CA. As a typical value, for example, when the capacitor CA is 10 pF and the combined ON resistance of the analog switch is 50 KΩ, the time constant is about 0.5 μs. The time required for the voltage across the terminals of the capacitor CA to reach 99% or more of the final value during charging is 2.3, which is 4.6 times the time constant.
μs. If the analog switch ON time per one data line is set to 3 μs with a margin, when the liquid crystal display panel 10 has 640 × 480 pixels, one horizontal scanning time 1H is about 30 μs, so 30 μs / 3 μs> 8. 8 data lines X for each decoder 241
1 can be associated.

Therefore, according to the first embodiment, the circuit scale of the data driver 20B can be greatly reduced, and when the data driver 20B is an LSI, it contributes to cost reduction and miniaturization of mounting. large.

[Second Embodiment] FIG. 5 shows a sample hold circuit 27B of the second embodiment. This sample hold circuit 27B is used in place of the sample hold circuit 27A of FIG.
7A is a cascade connection type, while the sample hold circuit 27B is a parallel connection type.

In the sample hold circuit 27B, one end of the analog switch SC and one end of the analog switch SD are commonly connected to the input end of the voltage follower OP. The other end of the analog switch SC is connected to one end of the capacitor CA and one end of the analog switch SA, and the other end of the capacitor CA is connected to the ground line. The other end of the analog switch SD is connected to one end of the capacitor CB and one end of the analog switch SB, and the capacitor C
The other end of B is connected to the ground line. The other ends of the analog switches SA and SB are commonly connected and serve as an input end of the sample hold circuit 27B. The output end of the sample hold circuit 27B is the output end of the voltage follower OP.

This sample hold circuit 27B is shown in FIG.
Of the analog switch SA, the capacitor CA, the analog switch SB, and the capacitor CB of
A first set consisting of A, analog switch SB and capacitor CB is used, and for even pixel data, analog switch SB, capacitor CB, analog switch S
A second set of C and capacitors CA is used.

The analog switches SA and SB are on / off controlled by sample pulses T61 and T62, respectively. The sample pulses T61 and T62 are sample pulses T6 of FIG. Obtained by switching alternately. The analog switches SC and SD are on / off controlled by sample pulses T51 and T52, respectively.
The sample pulses T51 and T52 are the sample pulse T5 and the sample pulse T5 shown in FIG.
It is obtained by alternately switching every one period.

[Third Embodiment] FIG. 6 shows a multi-gradation active matrix liquid crystal drive circuit of the third embodiment. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In this data driver 20C, the selectors 261 and 263 of FIG. 1 are omitted, and N-bit shift registers 281 to 284 are used instead of the N-bit registers 231 to 234 of FIG.

The operation of switching from the register 231 to the register 232 by the selector 261 of FIG. 1 is performed by the control circuit 40C.
With the clock CK3 from, the shift registers 281 and 282 connected in series are shifted at high speed by N bits. The same applies to the shift registers 283 and 284.

The other points are the same as in FIG.

[Fourth Embodiment] FIG. 7 shows a multi-gradation active matrix liquid crystal drive circuit of the fourth embodiment. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In this circuit, for the data driver 20D, the registers 222, 224, 232 and 234 of FIG.
And the selectors 261, 263 are omitted, and the register 23
The output terminals of 1 and 233 are connected to the decoders 241 and 2 respectively.
43 is connected to the input end of the line memory 43, and instead, line memories 51 to 54 and a selector 6 are provided outside the data driver 20D.
It has 0.

When the data driver 20D is composed of a plurality of LSIs, the line memories 51 to 54 and the selector 60 are included.
Need only be equipped with one set. For this reason, the line memory 5
1 to 54 and the selector 60 are provided outside the data driver 20D.

The shift register 21A has 2 bits,
The frequency of the initial pulse T1A supplied to the shift register 21A is twice the frequency of the initial pulse T1 of FIG. 1, as shown in FIG. The frequency of the clock CK1A supplied to the shift register 21A is the clock CK of FIG.
It is the same as the frequency of 1.

The digital video signal D is commonly supplied to the line memories 51 to 54, and the digital video signal D is written and held in the line memories 51 to 54 at the timing of the latch pulses T8 to T11 from the control circuit 40D. It When one of the first set of line memories 51 and 52 and the second set of line memories 53 and 54 is in the write state,
The other pair is in the read state, and the pair of writing and reading is switched every one cycle of the horizontal synchronizing signal HS. The contents of the line memories 51 to 54 are supplied to the selector 60,
The selector 60 reads out the data from the line memory in the read state and supplies it to the registers 221 and 223 as the gradation display data DS.

The scale of the multi-gradation active matrix liquid crystal drive circuit of the fourth embodiment can be made smaller than that of the first embodiment as a whole.

Next, the operation of the multi-gradation active matrix liquid crystal drive circuit configured as described above will be described with reference to FIG.

In the first cycle of the horizontal synchronizing signal HS, the gray scale display data 11 to 14 are alternately written in the line memories 51 and 52, and the gray scale display data 11 and the line memory 51 are written in the line memories 51 and 52.
12, the gradation display data 13 and 14 are held in the line memory 52. At this time, the line memories 53 and 54
Is in a read state.

In the second period of the horizontal synchronizing signal HS, the gray scale display data 21 to 24 are written alternately in the line memories 53 and 54, and the gray scale display data 21 and the gray scale display data 21 are written in the line memory 53.
23 is held, and the gradation display data 22 and 24 are held in the line memory 54. At the time of this writing, the line memory 51
The gray scale display data 11 and 13 are read from the shift register 21A, and the gray scale display data 11 and 13 are read at the timing of the latch pulses SP1 and SP3 from the shift register 21A, respectively.
21 and 223 are written and held. Next, at the timing of the latch pulse T2, the registers 221 and 223 are
Contents are written and held in the registers 231 and 233 at the same time, and then the gradation display data is written from the line memory 52.
12 and 14 are read out, and the gradation display data 12 and 14 are written and held in the registers 221 and 223, respectively, at the timing of the latch pulses SP1 and SP3 from the shift register 21A.

In the third period of the horizontal synchronizing signal HS, the gray scale display data 31 to 34 are written alternately in the line memories 51 and 52, and the gray scale display data 31 and the line memory 51 are written.
33 is held, and the gradation display data 32 and 34 are held in the line memory 52. At the time of this writing, the line memory 53
The gradation display data 21 and 23 are read from the register 2, and the gradation display data 21 and 23 are respectively read at the timing of the latch pulses SP1 and SP3 from the shift register 21A.
21 and 223 are written and held. Next, at the timing of the latch pulse T2, the registers 221 and 223 are
Contents are simultaneously written and held in the registers 231 and 233, and then the gradation display data is written from the line memory 54.
22 and 24 are read out, and the gradation display data 22 and 24 are written and held in the registers 221 and 223 at the timing of the latch pulses SP1 and SP3 from the shift register 21A, respectively.

[Fifth Embodiment] FIG. 9 shows a multi-gradation active matrix liquid crystal drive circuit of the fifth embodiment. The same components as those in FIG. 7 are designated by the same reference numerals and the description thereof will be omitted.

This data driver 20E omits the registers 231 and 233 of FIG.
The outputs of 23 are directly supplied to the decoders 241 and 243, respectively. This omission is possible because the line memories 51 to 54 are arranged outside the data driver 20E. However, since the registers 231 and 233 are omitted, the line memories 51 to 5 by the selector 60 are omitted.
Speed and register 22 for continuous read from one of the four
As shown in FIG. 10, the speed at the time of continuous writing to 1 and 223 is set higher than that in the case of FIG. 8 to secure the time required for writing to the capacitor CB by the sample pulse T5.

When the number of data lines for one selector 251 is the same as in the fourth embodiment, it is obviously the fourth
Although the configuration is simpler than that of the embodiment, the fourth embodiment is
More data lines can be associated with one selector 251.

The other points are the same as those in the fourth embodiment.

[0063]

As described above, according to the multi-gradation active matrix liquid crystal drive circuit of the first and second inventions, the digital / analog which is the main cause of the increase in the circuit scale as the number of gradations increases. It is possible to reduce the number of analog switches constituting the conversion means to half or less of the conventional one,
Further, since the data line having a relatively large distributed capacitance is not directly driven through this analog switch, the analog switch having a larger on-resistance than the conventional one can be used, and therefore, the required chip area of the analog switch can be narrowed. The excellent effect that the increase in the circuit scale due to the increase in the number of gradations can be suppressed,
It greatly contributes to reduction of production cost and miniaturization of mounting.

According to the second invention, the first storage means and the selection means are arranged outside the data driver so that the first storage means and the selection means are shared by a plurality of LSIs forming the data driver. Therefore, the multi-gradation active matrix liquid crystal drive circuit as a whole is the first
The circuit size can be made smaller than that of the invention.

[Brief description of drawings]

FIG. 1 is a multi-gradation active matrix liquid crystal drive circuit diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of main parts of the circuit of FIG.

FIG. 3 is a configuration diagram of a sample hold circuit of FIG.

FIG. 4 is a time chart showing the operation of the circuit of FIG.

FIG. 5 is a configuration diagram of a sample hold circuit according to a second embodiment of the present invention.

FIG. 6 is a multi-gradation active matrix liquid crystal drive circuit diagram of a third embodiment of the present invention.

FIG. 7 is a multi-gradation active matrix liquid crystal drive circuit diagram of a fourth embodiment of the present invention.

FIG. 8 is a time chart showing the operation of the circuit of FIG.

FIG. 9 is a multi-gradation active matrix liquid crystal drive circuit diagram of the fifth embodiment of the present invention.

FIG. 10 is a time chart showing the operation of the circuit of FIG.

FIG. 11 is a conventional multi-gradation active matrix liquid crystal drive circuit diagram.

12 is a circuit configuration diagram of the liquid crystal display panel and selector of FIG.

[Explanation of symbols]

10 liquid crystal display panel 20A-20E data driver 21, 21A, 281-284 shift register 221-234, 231-234 register 241-244 decoder 251-254, 261, 263, 60 selector 271-274, 27A, 27B sample hold circuit 40A-40E Control circuit 50 Reference voltage source 51-54 Line memory X1-X4 Data line Y1-Y4 Scan line SA-SD Analog switch OP, OP1, OP2 Voltage follower CA, CB Capacitor

Claims (5)

[Claims] 1. One end electrode of liquid crystal pixels (C11 to C44) is made common and the other end electrode is a switch element (Q11 to Q4).
4) is connected to the data lines (X1 to X4) via
Scan lines (Y1 to Y4) that cross the data lines
In a multi-gradation active matrix liquid crystal drive circuit for driving a liquid crystal display panel (10) to which the control input terminal of the switch element is connected, and displaying multi-gradation, one color is represented by N-bit gradation display data. A first storage means (221 to 224) in which a digital video signal (D) for writing is temporarily stored, and the gradation display data for one line stored in the first storage means for every p pixels. Selecting means (231 to 234, 261, 26) for reading the i-th gradation display data from the selected j-th group when divided into the 1st to qth groups.
3), digital / analog conversion means (50, 241, 243, 251, 253) for converting the gradation display data of each pixel read out from the selection means into an analog voltage, and for each data line Sample and hold circuit (27
1-274), the input terminals of the p sample-hold circuits are commonly connected to the output terminals of the one digital / analog conversion means, and each sample-hold circuit outputs two consecutive input voltages. The sample and hold circuit (271) having writable first and second capacitors (CA, CB) and having an output end connected to a data line
˜274), and causes the first storage means to perform the writing, and causes the selection means to output the i-th gradation display data of the 1st to qth groups.
Pixels are read out, and the reading is performed during one horizontal scanning time by i
= 1 to p, the analog voltage is written to one of the first or second capacitors of the i-th sample-hold circuit, and the analog voltage is written to the p sample-hold circuits. i = 1 to p, and control means (40B, 21) for applying the voltage written in the other one of the first and second capacitors to the data line as the output voltage of the sample hold circuit. A multi-gradation active matrix liquid crystal drive circuit characterized by the above. 2. The selection means is the first storage means (2).
21 to 224), and second storage means (231 to 234) to which the gradation display data of the group is written, and to each group of the second storage means. , And a selector (261, 263) for reading the selected one of the gradation display data from the group, and the control means (40B, 21) stores 1 in the first storage means.
After writing the gradation display data of the line, the gradation display data of the group is written in the second storage means, and the i-th gradation display data is written from each group of the second storage means. 2. The multi-gradation active matrix liquid crystal drive circuit according to claim 1, wherein the reading is repeated and the reading is repeated p times for i = 1 to p during one horizontal scanning time. 3. The selection means is the first storage means (2).
21 to 224), the gradation display data of the group is written, and
It is a shift register (281 to 284) from which the gradation display data for pixels is read out, and the control means (40C, 21) causes the first storage means to write the gradation display data for one line. Later, the gradation display data of the group is written in the shift register, and a shift pulse is supplied to the shift register to shift the gradation display data stored in the shift register by one pixel to the one end side. The gradation display data of the next pixel is read out from the one end side, and the shift for one pixel is repeated p times during one horizontal scanning time. Tone active matrix liquid crystal drive circuit. 4. One end electrode of the liquid crystal pixels (C11 to C44) is commonly used, and the other end electrode is a switch element (Q11 to Q4).
4) is connected to the data lines (X1 to X4) via
Scan lines (Y1 to Y4) that cross the data lines
In a multi-gradation active matrix liquid crystal drive circuit for driving a liquid crystal display panel (10) to which the control input terminal of the switch element is connected, and displaying multi-gradation, one color is represented by N-bit gradation display data. A first storage means (51 to 54) in which a digital video signal (D) is written and temporarily stored, and the gradation display data for one line stored in the first storage means for every p pixels. Selecting means (60) for reading the i-th gradation display data from the selected j-th group when divided into the first to q groups, and the floor for q pixels read from the selecting means. Second storage means (221, 2) in which key display data is written and temporarily stored
23, 231, 233) and digital / analog conversion means (50, 241, 243, 251, 253) for converting the gradation display data of each pixel stored in the second storage means into an analog voltage, A sample hold circuit (27
1-274), the input terminals of the p sample-hold circuits are commonly connected to the output terminals of the one digital / analog conversion means, and each sample-hold circuit outputs two consecutive input voltages. The sample and hold circuit (271) having writable first and second capacitors (CA, CB) and having an output end connected to a data line
˜274), the first storage means and the second storage means are caused to perform the writing, and the selection means is read out the i-th gradation display data of the 1st to qth groups for q pixels in order. Then, the reading is repeated p times for i = 1 to p during one horizontal scanning time, and the first or second capacitor of the i-th sample / hold circuit is connected to the p sample / hold circuits. The analog voltage is written in one of the two, and i = 1 to p
The control means (40D, 2D) for applying the voltage written in the other of the first or second capacitor to the data line as the output voltage of the sample hold circuit.
1) and a multi-gradation active matrix liquid crystal drive circuit characterized by the following. 5. The second storage means has a storage capacity of a second A having a storage capacity for storing the gradation display data for the q pixels.
Storage means (221, 223) and second B storage means (23
1, 233), and the control means (40D, 21) includes the selection means (6
0), the gradation display data for the q pixels is written in the second A storage means, then the stored contents of the second A storage means are transferred to the second B storage means, and then the second storage means is stored. The gradation display data for the q pixels is read from the 2B storage means, the reading is repeated p times for i = 1 to p during one horizontal scanning time, and at the same time as the reading, the second display memory means is read. 5. The multi-gradation active matrix liquid crystal drive circuit according to claim 4, wherein the gradation display data for the q pixels is written.