JP2011170376A - Liquid crystal display driving device, liquid crystal display system, and semiconductor integrated circuit device for driving liquid crystal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact liquid crystal driver (semiconductor integrated circuit for driving liquid crystal) having built-in DA converter circuits to convert digital image data into an analog gradation voltage and outputting a voltage applied to the signal line (source line) of a color liquid crystal panel. <P>SOLUTION: Output amplifiers (160: AMP1-AMP480) of the final stage to output an image signal converted into a gradation voltage are divided into a plurality of groups. The D/A converter circuits (160: DAC1-DAC40) converting the image data into a gradation voltage are arranged as circuits common to the groups, and time sharing operation of the D/A converter circuits is carried out while changing the groups. The output amplifiers of the final stage are selected to group the output amplifies relating to image signals of the same color. A selector function is arranged between the D/A converting circuits and the output amplifiers, and the image signals converted into the gradation voltages by the D/A converting circuits are distributed to desired hold circuits. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display driving device that drives a color display panel, a liquid crystal display driving device that drives a color liquid crystal panel, and a technique that is effective when applied to a liquid crystal display driving device that is formed into a semiconductor integrated circuit. The present invention relates to a technique effective when used in a liquid crystal display driving device for driving the color liquid crystal display panel in a color television system having a liquid crystal display panel.

  A liquid crystal display device as one of display devices includes a liquid crystal display panel (hereinafter also referred to as a liquid crystal panel) as a display panel, a liquid crystal display control device (liquid crystal controller) as a display control device, and a liquid crystal under the control of the control device. A liquid crystal display driving device (liquid crystal display driver) is used as a display driving device for driving the display panel. A source driver for driving a source line as a signal line to which a pixel signal of a liquid crystal panel is applied generally has digital image data for each image signal output terminal Y1, Y2,... Yn as shown in FIG. Digital-analog (DA) conversion circuits DAC1, DAC2,... DACn for converting signals into analog voltages are provided.

  In the driver of FIG. 16, DA converter circuits DAC1, DAC2,... DACn are alternately arranged for positive voltage output and negative voltage output, and pixel data of a certain source line is converted to positive voltage by multiplexer MPX1. The electrodes of each pixel are AC driven by being alternately input to the output DA conversion circuit DACi and the negative voltage output DA conversion circuit DACi + 1, converted into an analog voltage, and applied to the source line via the multiplexer MPX2. The liquid crystal is prevented from deteriorating.

JP 2001-27750 A

  In recent years, image data in a liquid crystal display device is composed of a plurality of pixel data. One pixel data is composed of 8-bit red data (R), 8-bit green data (G), and 8-bit blue data (B) per pixel. Are often 256 levels for each color (R / G / B). However, as the liquid crystal display device is improved in image quality, a liquid crystal display device capable of performing higher gradation display has been demanded. Therefore, the present inventors can, for example, set each color (R / G / B) data constituting pixel data of one pixel to 10 bits and perform gradation display such as 1024 steps for each color (R / G / B). The source driver was examined.

  As a result, in the method in which the DA conversion circuits DAC1, DAC2,... DACn are provided for each of the image signal output terminals Y1, Y2,... Yn, the number of wirings for supplying the gradation voltage to the DA conversion circuit is 2048 in total. I need it. Therefore, the width of the wiring area of the wiring that supplies the gradation voltage is widened, and even if the DA converter circuit is arranged under the wiring that supplies the gradation voltage (also referred to as a power supply line), a wasteful space is generated. become. Accordingly, the inventors have found that there is a problem that the size of the liquid crystal driver, that is, the semiconductor chip on which the source driver is formed increases, leading to a significant cost increase of the source driver. In order to solve this, the number of DA conversion circuits mounted on the source driver may be reduced and the DA conversion circuit may be operated in a time-sharing manner. In this case, the image data is input and then output as an analog voltage. It takes a long time.

  In addition, liquid crystal panels with a large number of source lines are provided along with the increase in size and definition of the display screen, and therefore liquid crystal panels with different numbers of source lines coexist. In order to make it possible to use a common source driver for these liquid crystal panels, it is one solution to provide an image signal output terminal in accordance with the liquid crystal panel having the largest source line. However, the inventors have also found that such a source driver is not an effective method because its chip size becomes extremely large.

  Therefore, it is conceivable to limit the number of image signal output terminals of one source driver and to configure a liquid crystal display system using a plurality of source drivers. Such a technique is effective in reducing the chip size of the source driver. However, in this case, it is necessary to pay attention to the timing when switching the source driver to which image data is to be sent. If the timing is inaccurate, there is a possibility that the image data cannot be correctly captured by the source driver, or that the transmission time for transmitting the image data to the source driver becomes long.

  An object of the present invention is to reduce the size of a display driving device (liquid crystal driver, liquid crystal driving semiconductor integrated circuit).

  Another object of the present invention is to provide a display drive device (liquid crystal driver) capable of constituting a display device (liquid crystal display device) by combining a plurality of display drive devices (liquid crystal driver).

  Still another object of the present invention is to provide a plurality of display driving devices (liquid crystal drivers) capable of dynamically performing gamma correction according to the characteristics of each color of a color display panel (color liquid crystal panel).

  Still another object of the present invention is to provide a plurality of display driving devices (liquid crystal drivers) capable of performing high gradation display while suppressing an increase in chip size.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Outlines of representative ones of the inventions disclosed in the present application will be described as follows.

  That is, the final stage output amplifier that outputs the image signal converted into the analog gradation voltage is divided into a plurality of groups, and the digital-analog (DA) conversion circuit that converts the image data into the analog gradation voltage is common to the above groups. The DA converter circuit is operated in a time-sharing manner while switching groups. The final stage output amplifiers select and group together those related to the same color image signal, and a selector function is provided between the DA conversion circuit and the output amplifier to convert the analog gradation voltage to the DA conversion circuit. The converted image signal is distributed to a desired output amplifier.

  According to the above-described means, since the DA conversion circuit is operated in a time-sharing manner, the number of DA conversion circuits is less than the number of image signal output terminals, and the display drive device (liquid crystal driver) can be downsized.

  In an image display system using a combination of a plurality of display driving devices (liquid crystal drivers) according to the present invention, DA conversion is performed by another display driving device (liquid crystal driver) while DA conversion is performed by a certain display driving device (liquid crystal driver). The converted image signal can be transmitted to the output amplifier. For this reason, it is possible to output the grayscale voltage within a predetermined time after inputting the image data, and the image data cannot be correctly taken into the display drive device (liquid crystal driver), or the time required for data transmission becomes long. Can be prevented.

  Further, since the output amplifiers in the final stage select and group those related to the same color image signal, the display control device (liquid crystal controller) is the same color image for one line of the display panel (liquid crystal panel). Data can be transferred continuously. Since color data can be switched three times for each R / G / B data per line, gamma correction can be performed by dynamically changing the gradation voltage of each color when switching color data. It becomes. Since the accompanying delay is extremely small, gamma correction can be performed without greatly changing the data transmission timing and system configuration.

  Further, according to another invention of the present application, a plurality of DA conversion circuits for converting image data into analog gradation voltages are arranged in the center of the semiconductor chip in a direction perpendicular to the longitudinal direction of the semiconductor chip. A plurality of wirings for supplying a gradation voltage are arranged along a direction orthogonal to the longitudinal direction of the semiconductor chip.

  According to the above-described means, the display driving device (liquid crystal driver) outputs a multi-stage image signal such as 1024 gradations, and even when the width of the wiring region for supplying the gradation voltage becomes wide, When the DA converter circuit is disposed under the wiring (feeding line) for supplying these gradation voltages, no wasteful space is generated, and the size of the semiconductor chip can be reduced.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the invention of the present application, it is possible to reduce the size of the display driving device (liquid crystal driver, liquid crystal driving semiconductor integrated circuit).

  Further, according to the invention of the present application, a display drive device (liquid crystal driver) capable of configuring a display device (liquid crystal display system) by combining a plurality of display drive devices (liquid crystal driver) is realized.

  Furthermore, according to the invention of the present application, it is possible to realize a display driving device (liquid crystal driver) that can dynamically perform gamma correction according to the characteristics of each color of the color display panel (color liquid crystal panel).

  In addition, it is possible to realize a display driving device (a liquid crystal driver, a liquid crystal driving semiconductor integrated circuit) capable of performing high gradation display while suppressing an increase in chip size.

It is a block diagram which shows schematic structure of the liquid crystal driver circuit to which this invention is applied. FIG. 2 is a block diagram showing a more detailed configuration by taking out a decoder unit, a sample and hold unit, and an output amplifier unit from the liquid crystal driver circuit of FIG. 1. It is a block diagram which shows the structural example of the liquid crystal display system which uses multiple liquid crystal driver circuits of a present Example. 4 is a timing chart showing the transmission timing of a red image signal supplied from a decoder unit of four liquid crystal driver circuits forming a set to the sample and hold unit in the liquid crystal display system of FIG. 4 is a timing chart showing the transmission timing of a green image signal supplied from a decoder unit of four liquid crystal driver circuits that form a set to the sample and hold unit in the liquid crystal display system of FIG. 4 is a timing chart showing the transmission timing of a blue image signal supplied from a decoder unit to a sample and hold unit of four liquid crystal driver circuits each forming a pair in the liquid crystal display system of FIG. 4 is a timing chart showing timings of control signals and clocks supplied from the liquid crystal display controller to the liquid crystal driver circuit in the liquid crystal display system of FIG. 3. It is a block diagram which shows the structural example of a timing control part. It is a timing chart which shows the timing of the latch clock automatically generated by the timing control unit. 4 is a timing chart showing timings of various signals in the liquid crystal display system of FIG. 3. It is a block diagram which shows the structural example of the unit sample hold circuit of a sample hold part. It is a timing chart which shows the operation timing of the unit sample hold circuit of a sample hold part. It is a top view which shows an example of the layout on the semiconductor chip of each circuit block which comprises the liquid crystal driver circuit of a present Example. It is a top view which shows arrangement | positioning of the DA converter circuit in the decoder part of the Example of FIG. It is a top view which shows the layout of the liquid crystal driver circuit examined prior to this invention. It is a block diagram which shows schematic structure of the liquid-crystal driver circuit examined prior to this invention.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a schematic configuration of a liquid crystal driver circuit to which the present invention is applied. Although not particularly limited, each circuit block shown in FIG. 1 is configured as a semiconductor integrated circuit on one semiconductor chip such as single crystal silicon. The liquid crystal driver circuit of this embodiment is an image applied to the signal lines of a dot matrix type color liquid crystal panel in which a plurality of scanning lines and a plurality of signal lines are arranged in a grid pattern and pixels are provided at each intersection. It is a circuit that outputs signals Y1 to Yn.

  In the present invention, although not particularly limited, pixel data of one pixel is assumed to be composed of 30 bits in which each color data of red (R) / green (G) / blue (B) is 10 bits. Examples will be described.

  The liquid crystal driver circuit of this embodiment has 10-bit input image data (indicating 10 bits of one color data among three color data of red (R) / green (G) / blue (B)) D9 to The first latch unit 110 that sequentially captures D0, the second latch unit 120 that collectively transfers the image data captured by the first latch unit 110, and the input image data D9 to D0 are all “1”. A data inversion circuit 130 that inverts data depending on whether the pixel is set to “black” or the pixel is set to “black” when all the pixels are “0”, and the input image data D9 to D0 in the first latch unit 110 A latch position designating circuit 140 for designating whether or not to take in and a gradation voltage V0 to V8 and V9 to V17 supplied from the outside are divided by a ladder resistor to generate 1024 grayscale voltages each having a positive polarity and a negative polarity. Voltage regulator A circuit 150, and a decoder (selector) unit 160 that converts a digital signal into an analog gradation voltage by selecting a voltage corresponding to the image data held in the second latch unit 120 from the generated voltages A sample-and-hold unit 170 that holds the converted analog voltage, an output amplifier unit 180 that generates and outputs image signals Y1 to Yn corresponding to the held voltage, and a clock signal and a control signal input from the outside And a timing control unit 190 for generating an internal control signal for operating the circuits in the semiconductor chip in a predetermined order.

  In the timing controller 190, when a plurality of liquid crystal driver circuits of this embodiment are connected in series to configure a system for driving a liquid crystal panel having more signal lines than the number of outputs (n) of the circuit, A signal indicating that the first liquid crystal driver circuit (the IC to which the first image data is supplied) is output according to the state of the predetermined terminal EIO1 and that the circuit has output all the image signals Y1 to Yn. Is provided from a predetermined terminal EIO2. Specifically, the terminal EIO1 of the leading liquid crystal driver circuit is fixed to the power supply voltage Vcc, and the terminal EIO2 of the previous stage liquid crystal driver circuit is connected to the terminal EIO1 of the next stage, whereby a plurality of liquid crystal driver circuits are sequentially imaged. Data can be taken in.

  FIG. 2 shows the configuration of the liquid crystal driver circuit shown in FIG. 1 in more detail by taking out the decoder unit 160, the sample-and-hold unit 170, and the output amplifier unit 180.

  In this embodiment, the sample and hold unit 170 and the output amplifier unit 180 are provided with 480 unit sample and hold circuits S / H1 to S / H480 and output amplifiers AMP1 to AMP480 that operate as voltage followers, respectively. On the other hand, 1/12 (40) DA converter circuits DAC1 to DAC40 and amplifiers operating as voltage followers are provided. Here, the 40 circuits constituting the decoder unit 160 are referred to as a DA converter for convenience, but a voltage corresponding to the input code from among the plurality of gradation voltages supplied from the gradation voltage generation circuit 150. The decoder unit 160 can be configured by a selector composed of only switch elements that select and output.

  The 40 outputs of the decoder unit 160 are taken into any 40 of the 480 unit sample / hold circuits S / H1 to S / H480 via a bus BUS composed of 40 signal lines. It is configured. Specifically, 40 pieces of image data of the same color are collectively input to the decoder unit 160, and among the 480 output terminals Y1 to Y480, Y1, Y4, Y7. The red image signal corresponds to the signal line connected to the red (R) pixel, and Y2, Y5, Y8... Y479 are green image signals corresponding to the signal line connected to the green (G) pixel of the liquid crystal panel. However, Y3, Y6, Y9,..., Y480 are the 40 converted by the decoder unit 160 so that blue image signals are output corresponding to the signal lines connected to the blue (B) pixels of the liquid crystal panel. Image signals are taken into a total of 40 sample and hold circuits every other two of the sample and hold circuits S / H1 to S / H480.

  The DA conversion circuits DAC1... DAC40 are alternately arranged for positive voltage output and negative voltage output. That is, when the odd-numbered DA converter circuits DAC1, DAC3... DAC47 output a positive voltage, the even-numbered DA converter circuits DAC2, DAC4... DAC48 output a negative voltage. Then, the pixel data of a certain bit is alternately input to the positive voltage output DA conversion circuit DACi and the negative voltage output DA conversion circuit DACi + 1 by the multiplexer MPX1, converted into an analog voltage, and transmitted to the sample and hold circuit. It is output via the multiplexer MPX2.

  At this time, the multiplexers MPX1 and MPX2 operate in the same manner. That is, when the multiplexer MPX1 passes through the image data, the multiplexer MPX2 also passes through the image signal, and when the multiplexer MPX1 crosses the image data, the signal path is switched so that the multiplexer MPX2 also crosses the image signal. As a result, a positive voltage and a negative voltage are alternately applied to the electrodes of each pixel of the liquid crystal panel to be driven by alternating current, thereby preventing deterioration of the liquid crystal.

  FIG. 3 shows a block diagram when a system for driving a color liquid crystal panel 200 of 1280 × 768 dots using a plurality of liquid crystal driver circuits 100 of the present embodiment is configured. Eight liquid crystal driver circuits DRV1 to DRV8 are arranged in the line direction of the color liquid crystal panel 200, and these four liquid crystal driver circuits DRV1 to DRV8 are divided into two groups each including four liquid crystal driver circuits DRV1. , DRV5 terminal EIO1 is fixed at power supply voltage Vcc, and terminal EIO1 of the previous liquid crystal driver circuit is electrically coupled to terminals EIO1 of the remaining liquid crystal driver circuits DRV2 to DRV4 and DRV6 to 8. Four are connected in series.

  Reference numeral 300 denotes a scanning line driving circuit (common driver) for sequentially setting common lines (called gate lines in the TFT panel) of the color liquid crystal panel 200 to a selection level, and 400 denotes a timing control signal for the scanning line driving circuit 300, The liquid crystal display controller generates image data D9 to D0 supplied to the liquid crystal driver circuit, a control signal DSS for controlling the liquid crystal driver circuit, and operation clocks CL1 and CL2.

  The liquid crystal display controller 400 is configured to simultaneously output image data D9 to D0 for the two scanning line driving circuits. In this embodiment, the control signal DSS for informing the start of transmission of image data and the clock CL2 for informing the capture timing are separately generated and given to the two liquid crystal driver circuits DRV1 to DRV4 and DRV5 to DRV8. Although configured, these signals may be given as a common signal.

  FIGS. 4 to 6 show transmission of image signals sent from the decoder unit 160 of the four liquid crystal driver circuits DRV1 to DRV4 or DRV5 to DRV8, respectively, to the sample and hold unit 160 in the liquid crystal display system as shown in FIG. Timing is shown. The flow of time in FIGS. 4 to 6 is from FIG. 4 to FIG. 5 to FIG. 6, and in each figure, the flow first goes from left to right and reaches the right end when it reaches the right end. .

  As can be seen from FIG. 4 to FIG. 6, in the liquid crystal display system of the present embodiment, first, red image data is transmitted 16 times each 16 times, DA-converted and held, and then green image data 40 Each image is transmitted 16 times, DA-converted and held, and then blue image data is transmitted 40 times 16 times, DA-converted and held.

  Thus, 1920 image data are transmitted and held for 640 dots, which is half of one line of the liquid crystal panel. In the liquid crystal display system of this embodiment, a slight delay time is provided when moving from the transmission of red image data to the transmission of green image data and further to the transmission of blue image data. Gamma correction for changing the output voltage according to the gamma characteristic of the image is dynamically performed. As described above, in the liquid crystal display system of this embodiment, the gamma correction can be dynamically performed relatively easily because the image data of each color of red, green and blue are transmitted together. .

  In a display system that sequentially transmits image data for one end signal line to image data for the other end signal line in accordance with the configuration of the color liquid crystal panel, transmission of red image data and green image Since data transmission and blue image data transmission are repeated or mixed, gamma correction must be performed for each color image data transmission. Therefore, it is necessary to provide a delay time for gamma correction as many as the number of image data. In such a case, transmission of all image data cannot be completed in one horizontal period.

  On the other hand, in the liquid crystal display system of the present embodiment, the image data of each color of red, green, and blue are transmitted together, so that a delay time for gamma correction is provided only three times during one horizontal period. Therefore, transmission of all image data can be completed during one horizontal period.

  Note that the gamma correction in the liquid crystal driver circuit of this embodiment is performed by applying the voltages V0 to V8 and V9 to V17 supplied from the outside to the gradation voltage generation circuit 150 of FIG. 1 according to the gamma characteristics of each color of red, green, and blue. It can be realized by switching.

  7 shows the data sampling start control signal DSS supplied to the liquid crystal driver circuits DRV1 to DRV4 (the same applies to DRV5 to DRV8) from the liquid crystal display controller 400 in the liquid crystal display system of FIG. The timings of the notification clocks CL1 and CL2, the image data D9 to D0, and the data transmission end signal EIO2 output from each of the liquid crystal driver circuits DRV1 to DRV4 are shown.

  Among them, the clock CL1 is a signal indicating one horizontal period, and the control signal DSS is a signal for informing the data sampling start timing of each of the liquid crystal driver circuits DRV1 to DRV4, four times during one horizontal period, that is, one period of the clock CL1. The control signal DSS rises.

  On the other hand, CL2 is a clock for informing the timing for taking in the image data D9 to D0. In this embodiment, the liquid crystal driver circuit is configured to take in the image data at the falling edge and the rising edge of the clock CL2. The number of pulses of the clock CL2 in the period during which the driver circuit captures 40 pieces of image data, that is, the period of one cycle of the data sampling start control signal DSS is 20.

  Note that the first liquid crystal driver circuit DRV1 starts to capture the image data from the time point two pulses after the clock CL2 after the data sampling start control signal DSS changes. Further, the signal EIO2 notifying that each liquid crystal driver circuit has captured 40 pieces of image data rises two pulses before the clock CL2 before the actual last data capturing timing. Thereby, the liquid crystal driver circuits DRV2 to DRV4 can continuously capture the image data without a time delay from the end of the data capturing of the driver in the previous stage.

  Next, the operation inside the chip of the liquid crystal driver circuit DRV of the embodiment will be described. Each circuit block inside the liquid crystal driver circuit DRV is operated at a predetermined timing by a control signal from the timing control unit 190, and the timing control unit 190 configures an internal circuit based on a clock signal or control signal input from the outside. An internal control signal is generated to operate according to a predetermined order.

  FIG. 8 shows a configuration example of the timing control unit 190. The timing control unit 190 of this embodiment uses control signals STB, CEN and the like indicating whether to operate the initial stage latch circuit 110 that captures image data based on the input signal EIO1 or a counter that will be described later that counts the clock, or to enter a standby state. A DSS counter 192 that counts the number of data sampling start control signals DSS in one horizontal period and generates an enable signal SHEN for the sample and hold unit 170 based on the generated operation start determination circuit 191 and a clock CL1 indicating one horizontal period. And a clock control circuit that generates a latch timing signal DLT that divides the clock CL2 that gives the data latch timing and gives the timing at which the image data fetched into the first latch unit 110 is transferred to the second latch unit 120 at once. 193 and the output amplifier unit 180 Comprising an LCD output control circuit 194 for generating an output enable signal OEN to enable the output of the LCD image signals against.

  Although not shown in FIG. 1, in the liquid crystal driver circuit of the embodiment, the second latch unit 120 has a two-stage configuration including a first-stage latch circuit 121 and a second-stage latch circuit 122. The control unit 190 generates and supplies a clock that sequentially latches the first-stage latch circuit 121 and the second-stage latch circuit 122. As a result, the first-stage latch circuit 121 operates as a master latch, the second-stage latch circuit 122 operates as a slave latch, and the image data captured by the second latch unit 120 is immediately transferred to the next-stage decoder unit 160. Can be prevented.

  Further, the timing control unit 190 includes a CL2 counter 195 that counts the number of clocks CL2 between the data sampling start control signals DSS, and a CL2 number register 196, 1 that holds the number of clocks CL2 between the first DSS signals in one line. Comparator 197 for comparing the number of clocks CL2 between the first DSS signals in the line and the number of clocks CL2 between the second and subsequent DSS signals, and based on the comparison result of the comparator 197, the external DSS signal is When the clock signal DLC is not input for a period longer than the number of clocks CL2 between the DSS signals, the clock signal DLC for instructing the latch circuit 122 at the subsequent stage of the second latch unit 120 to latch data is automatically generated within the semiconductor chip. A latch clock generation circuit 198 is provided.

  The latch clock generation circuit 198 is provided in a display system that performs gamma correction using the liquid crystal driver circuit of this embodiment, as shown in FIG. 9, for gamma correction during the transfer period of image data of each color. Since the DSS signal may be input with a slight delay in order to provide a margin period (Ta), if the latch clock signal DLC for the latch circuit 122 is generated based only on the DSS signal, the latch timing is delayed. It is.

  In the timing control circuit of this embodiment, the EIO2 signal for the next stage liquid crystal driver circuit can be raised when the CL2 counter 195 counts a predetermined number (16 clocks). Thus, by connecting the next stage liquid crystal driver circuit to receive this signal at the EIO1 terminal, in a display system using a plurality of liquid crystal driver circuits, the liquid crystal display controller is unique to each driver. Continuous image data can be transmitted without sending a start signal. Therefore, the burden on the designer of the display system can be reduced.

  FIG. 10 shows a liquid crystal display in a liquid crystal display system as shown in FIG. 3 in which eight liquid crystal driver circuits of the embodiment are used and four image data are sequentially transferred in pairs to perform color display on the liquid crystal panel. The timing of the data sampling start control signal DSS and the clock CL1 supplied to the driver circuits DRV1 to DRV4 (same for DRV5 to DRV8), the clock enable signal CEN generated in each of the liquid crystal driver circuits DRV1 to DRV4, The timing of the sample hold enable signal SHEN and the EIO2 signal for the next stage liquid crystal driver circuit is shown.

  FIG. 11 shows a configuration example of a unit sample / hold circuit of the sample / hold unit 170, and FIG. 12 shows an operation timing thereof.

  The unit sample and hold circuit of this embodiment includes a set of hold capacitors CH1 and CH2 for holding the voltage AD-converted by the decoder unit 160, an output terminal of the amplifier AMPi on the input side, and the hold capacitors CH1 and CH2. A pair of switches SW11 and SW12 connected between the nodes N1 and N2 to which one terminal is connected, respectively, and a pair of switches connected between the nodes N1 and N2 and the input terminal of the amplifier AMPo on the output side. It is composed of switches SW21 and SW22. The amplifiers AMP1 to AMP480 in FIG. 2 correspond to the amplifier AMPo in FIG.

  The pair of switches SW11, SW12 are turned on / off by control signals EN11, EN12, and the switches SW21, SW22 are turned on / off by control signals EN21, EN22. The control signals EN11, EN12, EN21, and EN22 are controlled so that SW22 is turned on when the switch SW11 is turned on, and SW21 is turned on when the switch SW12 is turned on. Further, the control signals EN11 are controlled based on the sample hold enable signal SHEN so that the switches SW11 and SW21 are not turned on at the same time and the switches SW12 and SW22 are not turned on at the same time. , EN12, EN21, EN22 are generated.

  In the unit sample / hold circuit of this embodiment, when the switch SW11 is turned on, the switch SW21 is turned off, and the voltage (image signal) AD-converted by the decoder unit 160 is sampled in the hold capacitor CH1. . At this time, the hold capacitor CH2 on the opposite side is in a state of outputting the voltage sampled immediately before, when the switch SW22 is turned on and the switch SW12 is turned off.

  When the input voltage is sampled in the hold capacitor CH1, the switch SW11 is turned off and the switch SW12 is turned on, so that the sampled voltage is output. At this time, the switch SW12 is turned on and the switch SW22 is turned off, and the hold capacitor CH2 on the opposite side is charged with the voltage AD-converted by the decoder unit 160 for sampling.

  By repeating the above operation, one set of hold capacitors CH1 and CH2 alternately repeats the sampling state and the hold state, and the voltage (image signal) output from the decoder unit 160 is continuously sampled. Are output one after another.

  FIG. 13 shows an example of the layout on the semiconductor chip of each circuit block constituting the liquid crystal driver circuit of this embodiment. In FIG. 13, the same circuits as those shown in FIG. 2 are denoted by the same reference numerals.

  As can be seen from FIG. 13, in the liquid crystal driver IC of the present embodiment, a DA converter circuit POS-DAC that outputs a positive voltage and a DA converter circuit NEG-DAC that outputs a negative voltage are provided at the center of the semiconductor chip. Are arranged side by side in the longitudinal direction, a multiplexer MPX is disposed above, and a timing control circuit (190) composed of random logic and a gradation voltage generation circuit (150) TG & RL composed of a resistor ladder are disposed below. The multiplexer MPX2, the output amplifier AMP, and the sample / hold circuit S / H are arranged symmetrically from the top to the left and right of these circuits, and the same circuit as these is symmetrically arranged in the vertical direction. The hold circuit S / H, the output amplifier AMP, and the multiplexer MPX2 are arranged in this order.

  Further, as shown in FIG. 14, the DA converter circuit POS-DAC that outputs a positive voltage and the DA converter circuit NEG-DAC that outputs a negative voltage each include 20 unit DA converter circuits DAC1 to DAC20 in the longitudinal direction of the semiconductor chip. 1024 power supply lines that are arranged side by side in a direction orthogonal to the direction and supply the gradation voltage output from the gradation voltage generation circuit TG & RL are disposed thereon.

  As shown in FIG. 15, a liquid crystal driver IC having image data of 8 bits and 256 gradations includes a multiplexer MPX2, an output amplifier AMP, a decoder unit DAC, a level shifter, a multiplexer MPX1, a timing control circuit, and a gradation voltage generation circuit TG & RL. In general, the unit DA conversion circuit of the decoder unit has a chip layout in which the same number of output terminals as the number of output terminals are arranged along the longitudinal direction of the semiconductor chip. When this layout is applied to a liquid crystal driver IC having 10 bits of image data and 1024 gradations as in the liquid crystal driver IC of the present embodiment, four times as many feeder lines as the conventional one are provided on the DA converter circuit array. It must be arranged along the longitudinal direction, and the length of the power supply line becomes very long and the width of the power supply line is greatly increased, resulting in a waste space below the power supply line.

  On the other hand, according to the layout shown in FIGS. 13 and 14, it is only necessary to arrange the grayscale voltage power supply line along a direction orthogonal to the longitudinal direction of the semiconductor chip. In addition, even if the layout width of the plurality of power supply lines is significantly increased, the DA conversion circuit can be arranged without creating a waste space below the power supply lines. As a result, there is an advantage that an increase in chip size accompanying the increase in gradation can be significantly suppressed.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above-described embodiment, the case where the image data has 10 bits and the gradation voltage has 1024 levels has been described. However, the present invention is not limited thereto, and the image data has 9 bits and the gradation voltage has 512 levels. The present invention can also be applied to a case where the image data is 11 bits and the gradation voltage is 2048 levels. In the above-described embodiment, 40 DA converter circuits, that is, 1/12 DA converter circuits, are provided for 480 output amplifiers. However, 1/8 ICs or 1/16 ICs may be used.

  Further, in the above embodiment, a terminal is provided for outputting a signal EIO2 indicating the end of capturing of image data when the count value of the counter that counts the clock signal input in synchronization with the image data reaches a predetermined value, Although the terminal signal is input to the driver IC at the next stage as the data capture permission signal EIO1, the terminal for outputting the signal EIO2 may be omitted and the data capture permission signal EIO1 may be supplied from the liquid crystal display controller 400. Is possible.

  In the above description, the invention made mainly by the present inventor has been described as applied to a liquid crystal driver circuit for driving a liquid crystal panel, which is a field of use behind that. However, the present invention is not limited thereto. The present invention can be generally applied to a color display device driving circuit that converts color image data given by a digital code into an analog voltage and outputs the analog voltage.

100 Liquid crystal display drive device (Liquid crystal driver IC)
DESCRIPTION OF SYMBOLS 110 1st latch part 120 2nd latch part 130 Data inversion circuit 140 Latch position designation circuit 150 Gradation voltage generation circuit 160 Decoder (selector) part 170 Sample hold part 180 Output amplifier part 190 Timing control part 200 Liquid crystal panel 300 Scan line Drive circuit (common driver)
400 LCD controller DRV1 to DRV8 LCD driver IC
MPX1, MPX2 Multiplexer DAC DA conversion circuit AMP Output amplifier S / H Sample / hold circuit

Claims (10)

A liquid crystal display driving device capable of driving a color display device by being used in combination is
A first terminal;
A second terminal;
A third terminal;
A first data latch circuit;
A second data latch circuit;
A conversion circuit;
A sample-and-hold circuit;
An output amplifier circuit,
The first terminal receives an image data transmission start notification control signal,
An input permission signal for the image data is input to the second terminal,
The image data is input to the third terminal,
The first data latch circuit sequentially captures the image data input from the third terminal,
A second data latch circuit fetches the image data fetched by the first data latch circuit and sends the image data to the conversion circuit in a batch;
The conversion circuit converts the analog data into the analog drive voltage corresponding to the image data sent from the second data latch circuit, and outputs the converted voltage.
The sample-and-hold circuit is provided in a number corresponding to the number of output terminals used for driving the color display device, and holds the analog driving voltage output from the conversion circuit,
The output amplifier circuit is provided in a number corresponding to the number of output terminals, and outputs the analog drive voltage held in the sample hold circuit from the output terminal,
A first terminal to which an image data transmission start notification control signal is input;
When the transmission start notification control signal is input to the first terminal and the input permission signal is input to the second terminal, image data input from the third terminal is input to the first data latch circuit. Can be imported,
The conversion circuit is operated in a time-sharing manner by being provided as a circuit common to a plurality of groups of the sample hold circuit and the output amplifier,
The image data converted at a time by the conversion circuit is image data of the same color of red, green and blue for color display by the color display device,
As the image data, a plurality of image data of the same color are continuously input and converted into the analog drive voltage by the conversion circuit, and the drive voltage is held in the sample hold circuit and input to the output amplifier. A liquid crystal display driving device. A fourth terminal to which a clock signal indicating a data latch timing for taking in the image data into the first data latch circuit is input;
All of the image data captured by the first data latch circuit is sent from the second data latch circuit to the conversion circuit, and is converted into the analog drive voltage by the conversion circuit, and the sample hold circuit and the A fifth terminal for outputting an image output completion signal indicating output to the color display device via an output amplifier;
A counter that counts a clock signal input from the fourth terminal;
The counter starts counting the clock signal after inputting the input permission signal of the image data, and outputs the image output completion signal to the fifth terminal when the count value of the counter reaches a predetermined value. 2. The liquid crystal display according to claim 1, wherein the image output completion signal is used as an input permission signal for image data of one color display device among other color display devices used in combination. Drive device. The image data is the red image data, the green image data, and the blue image data of the color display,
The output terminal and the output amplifier are repeatedly arranged in a predetermined order, those related to the red image signal, those related to the green image signal, and those related to the blue image signal,
The liquid crystal display driving device according to claim 2, wherein every two output amplifiers are arranged in the same color group. The number of clock signals input to the fourth terminal between the transmission start notification control signal of the first image data input to the first terminal and the transmission start notification control signal of the second image data. A register that holds
Comparing means for comparing the number held in the register with the number of clock signals counted by the counter,
The transmission start notification control signal input to the first terminal is longer than the time corresponding to the number of clock signals between the first transmission start notification control signal and the second transmission start notification control signal. The count value of the counter becomes larger than the number held in the register, and the second data latch circuit is provided with a signal for instructing data fetching. The liquid crystal display driving device according to claim 2.   A plurality of image data of a first color selected from the red, the green, and the blue are continuously input to the third terminal, and then a second selected from the red, the green, and the blue. The grayscale voltage value supplied to the conversion circuit is adjusted in accordance with the gamma characteristic of the pixel corresponding to the second color before a plurality of image data of the same color are continuously input to the third terminal 5. The liquid crystal display driving device according to claim 2, wherein the gamma correction is performed. A gradation voltage generation circuit that divides a voltage applied from the outside to generate a plurality of gradation voltages and supplies the plurality of gradation voltages to the conversion circuit,
6. The liquid crystal display driving device according to claim 5, wherein the gamma correction is performed by changing the voltage applied to the gradation voltage generation circuit from the outside. A plurality of liquid crystal display driving devices having the configuration according to claim 5;
A color liquid crystal display panel serving as the color display device for receiving and displaying a drive voltage output from the output terminal of the plurality of liquid crystal display drive devices at a signal input terminal;
A scanning line driving device for sequentially driving a plurality of scanning lines of the color liquid crystal display panel;
A control device that generates the transmission start notification control signal of the image data input to the first terminal and controls the liquid crystal display driving device,
The transmission start notification control signal output by the control device is input to each terminal of the first terminal of the plurality of liquid crystal display driving devices,
The second terminal of the first liquid crystal display driving device among the plurality of liquid crystal display driving devices is connected to a constant potential point,
Of the plurality of liquid crystal display driving devices, the second terminal of each of the second and subsequent liquid crystal display driving devices is connected to the fifth terminal of the preceding liquid crystal display driving device. LCD display system. Each liquid crystal display driving device of the plurality of liquid crystal display driving devices includes a gradation voltage generating circuit that divides a voltage applied from the outside to generate a plurality of gradation voltages and supplies the plurality of gradation voltages to the conversion circuit,
The controller is
The image data of the first color selected from the red color, the green color, and the blue color is supplied to the plurality of color display devices to the liquid crystal display driving device, and then selected from the red color, the green color, and the blue color. The second color image data is supplied to all of the plurality of color display devices, and then the third color image data selected from the red color, the green color, and the blue color is supplied to all of the plurality of color display devices. The transmission start notification control signal is generated in the same cycle until the image data of the same color is supplied to all of the plurality of color display devices by repeating the supply operation, and the cycle is used when switching the image data of each color. A pre-transmission start notification control signal is generated at a longer cycle, and after the supply of the third color image data is finished, the voltage applied to the grayscale voltage generation circuit is switched to adjust the grayscale voltage and The liquid crystal display system according to claim 7, characterized in that to perform the correction. A first latch circuit for sequentially capturing image data input from the outside;
A second latch circuit for collectively fetching image data sequentially fetched into the first latch circuit;
A conversion circuit for outputting, as an image signal, a voltage corresponding to the image data sequentially taken into the second latch circuit;
A hold circuit for holding the image signal output by the conversion circuit;
An output amplifier that outputs a drive voltage corresponding to the image signal held in the hold circuit,
A plurality of the conversion circuits are arranged side by side along a direction orthogonal to the longitudinal direction of the semiconductor chip,
A plurality of wirings for supplying gradation voltages to the conversion circuits are disposed above the formation areas of the plurality of conversion circuits, and a semiconductor integrated circuit for driving a liquid crystal formed on one semiconductor chip Circuit device. The conversion circuit comprises a positive voltage and a negative voltage.
The formation regions of the plurality of conversion circuits that generate the positive voltage and the formation regions of the plurality of conversion circuits that generate the negative voltage are provided side by side in the longitudinal direction of the semiconductor chip,
In each formation region, a plurality of conversion circuits are arranged side by side along a direction orthogonal to the longitudinal direction of the semiconductor chip,
A plurality of wirings for supplying the gradation voltage to the conversion circuit above the formation region of the plurality of conversion circuits for generating the positive voltage and the formation region of the plurality of conversion circuits for generating the negative voltage 10. The semiconductor integrated circuit device for driving liquid crystal according to claim 9, wherein each of the semiconductor integrated circuit devices is disposed.

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