JP2007163913A - Liquid crystal display drive device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal driving semiconductor integrated circuit (liquid crystal driver) capable of suppressing the increase in size of a chip regardless of the increase of the number of outputs of a driving signal for source lines of a liquid crystal panel, and a liquid crystal display device using the same. <P>SOLUTION: In the liquid crystal driver which receives display image data to generate image signals to be applied to signal lines of the liquid crystal panel and outputs the image signals in accordance with a prescribed timing signal, signal lines of the liquid crystal panel are successively divided into groups by an integral multiple of 3, and a pair of positive and negative decoders for gradation voltage selection and a pair of positive and negative output amplifiers are provided for two adjacent groups. Furthermore, a switch which transmits or intercepts an image signal is provided corresponding to each signal line of the liquid crystal panel, and switching circuits which make transmission signals pass therethrough or cross are provided between the switch and the output amplifiers and in preceding stages of the decoders. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique effective when applied to a liquid crystal display driving device for driving a liquid crystal display panel. It is related to effective technology.

  A liquid crystal display device as one of the display devices includes a liquid crystal display panel (hereinafter referred to as a liquid crystal panel), a liquid crystal display control device (liquid crystal controller), and a display driving device that drives the liquid crystal panel under the control of the control device. A liquid crystal display driving device (liquid crystal driver) is used. Conventionally, various types of liquid crystal panels such as a passive type and an active matrix type have been proposed.

  Among these, a TFT liquid crystal panel, which is one of the active matrix type, is arranged so that a plurality of gate lines (scanning lines) and a plurality of source lines (signal lines) intersect, and an electrode serving as a pixel at each intersection A transistor for applying a voltage on the signal line to the electrode is disposed, and a liquid crystal is sandwiched between the common counter electrode. The liquid crystal driver sequentially applies pixel signals one line at a time to the source line of the liquid crystal panel having such a structure in synchronization with the selection operation of the gate line.

  The TFT liquid crystal panel is driven by an alternating current to prevent deterioration of the liquid crystal. As the AC driving method, there are a dot inversion method in which the polarity is inverted for each dot, a line inversion method in which the polarity is inverted for each gate line, and a column inversion method in which the polarity is inverted for each source line. .

  On the other hand, the liquid crystal panel tends to be enlarged with the times, and the liquid crystal driver needs to increase the number of outputs of the signal for driving the source line accordingly. However, if the number of output terminals is simply increased in response to the increase in the number of outputs, a drive amplifier is required for each terminal. Therefore, the size of the semiconductor chip on which the liquid crystal driver is formed increases, leading to an increase in cost.

Therefore, as shown in FIG. 6, a switch SW is provided corresponding to each signal line (source line) SL on the liquid crystal panel, and a source line drive signal is sent in time division from the liquid crystal driver side to the liquid crystal panel side. In synchronism with this, the switch SW on the source line is selectively turned on sequentially with the clocks φ1 to φ3, and the desired drive signal is applied to the desired source line SL, so that the gradation selection with the driver amplifier AMP on the driver side There is a technique in which the number of decoders DEC is reduced. Such time-division driving of the source line is described in Patent Document 1, for example.
JP-A-11-327518

  However, in the above-mentioned prior application, a positive polarity voltage and a negative polarity are provided as a drive amplifier provided for each output terminal that outputs a drive signal of the source line and a decoder that converts display pixel data of the preceding stage into an analog gradation voltage. The circuit which can output the voltage of is required.

  Such a circuit that can output both positive and negative voltages has a larger circuit scale than a circuit that outputs either positive or negative voltage, Power consumption also increases. Since liquid crystal panels will become larger and higher in density in the future, the size of the liquid crystal driver chip may increase as the panel capacity increases if the conventional circuit system is used.

  An object of the present invention is to provide a liquid crystal display driving device (liquid crystal driver) that can suppress an increase in chip size even when the number of output signals of a source line of a liquid crystal panel increases.

  The present invention also provides a liquid crystal display driving device (liquid crystal driver) capable of reducing the chip size as long as the number of driving signals output from the source lines of the liquid crystal panel is the same.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Outlines of representative ones of the inventions disclosed in the present application will be described as follows.

  That is, in a liquid crystal driver that receives display data, generates an image signal to be applied to a signal line of a liquid crystal panel, and outputs it according to a predetermined timing signal, the signal lines of the liquid crystal panel are sequentially grouped every integer multiple of 3 and adjacent For each of the two groups, a positive / negative set of gradation voltage selection decoders and a positive / negative set of output amplifiers are provided. Further, a switch for passing or blocking the image signal corresponding to each signal line of the liquid crystal panel is provided, and signals transmitted between the switch and the output amplifier and to the previous stage of the decoder are passed or crossed. A switching circuit is provided. Then, the output timing of the image signal is slightly shifted for each signal in each group and output in a time division manner, and half of the signals of the two adjacent groups are selected from the output from the positive output amplifier, and the remaining The other half controls the switch and the switching circuit so that the output from the negative output amplifier is selected.

  According to the above-described means, since the image signal to be applied to the signal line of the liquid crystal panel is output in a time-sharing manner, the number of output amplifiers can be reduced, and the outputs of a pair of positive and negative decoders are adjacent. Since it is used by switching between groups, the number of decoders can be reduced.

  Desirably, the switching circuit and the switch on the signal line are controlled such that signals having different polarities are output to adjacent signal lines among the signal lines in each group within one horizontal period. Accordingly, dot inversion or column inversion driving is possible, and the driving order of the signal lines is dispersed, so that screen flickering can be suppressed and display image quality deterioration can be avoided.

  Further, preferably, the signal lines in each group are divided into even-numbered signal lines and odd-numbered signal lines, and images from the output amplifier are sequentially successively connected to even-numbered signal lines (or odd-numbered signal lines). The switching circuit and the switch on the signal line are controlled so that the signal is applied, and then the image signal from the output amplifier is sequentially applied to the odd-numbered signal line (or even-numbered signal line) sequentially. As a result, the number of switching of the switching circuit can be reduced to suppress an increase in power consumption.

  When the liquid crystal panel to be driven is a liquid crystal panel using amorphous silicon when the present invention is applied, the switch on the signal line is provided on the liquid crystal driver side so that the liquid crystal panel to be driven is LTPS (low temperature In the case of a (polysilicon) liquid crystal panel, it is desirable to provide a switch on the signal line on the liquid crystal panel side. This is because amorphous silicon has a high switching speed and it is difficult to form a switch with a small on-resistance. Further, when the liquid crystal panel to be driven is an LTPS liquid crystal panel, by providing a switch on the liquid crystal panel side, it is possible to reduce the number of elements of the liquid crystal driver and reduce the chip size.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the invention of the present application, it is possible to realize a liquid crystal display driving device (liquid crystal driver) that can suppress an increase in chip size even if the number of driving signals output from the source lines of the liquid crystal panel increases.

  Further, according to the invention of the present application, a liquid crystal display driving device (liquid crystal driver) capable of reducing the chip size can be realized if the number of output signals of the source line driving signal of the liquid crystal panel is the same.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows an embodiment of a source line driving circuit unit and a liquid crystal panel of a liquid crystal driver to which the present invention is applied. The liquid crystal driver of the present embodiment is for a case where the liquid crystal panel to be driven is an LTPS liquid crystal panel.

  The LTPS liquid crystal panel 200 includes a plurality of scanning lines (gate lines) GL1, GL2,... And a plurality of signal lines (source lines) SL1, SL2, SL3. The dot matrix type color liquid crystal panel is provided. Each pixel includes a selection MOSFET having a gate terminal connected to the scanning line GL and a source terminal connected to the signal line SL, and a pixel capacitance formed between the drain terminal of the MOSFET and a counter electrode as a common electrode. Consists of

  In the liquid crystal panel 100 of the present embodiment, one external terminal P1, P2, P3... Is provided for every three signal lines (source lines), and each external terminal and the signal lines (source lines) SL1, SL2,. Between the switches SL3..., Switches SW1, SW2, SW3... For transmitting or blocking signals applied from the liquid crystal driver 100 to the external terminals P1, P2, P3. It has been.

  The liquid crystal driver 100 is not particularly limited, but is configured as a semiconductor integrated circuit on a single semiconductor chip such as single crystal silicon by a known semiconductor manufacturing technique. FIG. 1 shows only the source line driver circuit portion of the liquid crystal driver IC. As will be described later, the liquid crystal driver IC of this embodiment is provided with circuits other than the source line driving circuit, but the source line driving circuit shown in FIG. 1 is configured as one semiconductor integrated circuit, Other circuits can be configured on separate semiconductor chips.

  In this embodiment, the display pixel data will be described below on the assumption that each color data of red (R) / green (G) / blue (B) is composed of, for example, 8 bits.

  The source line driving circuit of the liquid crystal driver according to the present embodiment includes a data latch unit 110 including latch circuits LAT1 to LAT400 that sequentially capture 8-bit input display pixel data. In addition, the source line driver circuit selects one of the voltages supplied from the gradation voltage generation circuit 150 according to the display pixel data fetched by each latch circuit, thereby converting the digital signal into an analog gradation voltage. A gradation voltage selection unit 130 including decoders (selectors) DEC1 to DEC400 for conversion is provided. Further, the source line driving circuit includes an output unit 140 including output amplifiers AMP1 to AMP400 that generate and output image signals Y1 to Yn corresponding to the converted analog voltages.

  The gradation voltage generation circuit 150 divides gradation voltages V0 to V8 and V9 to V17 supplied from a power supply circuit (not shown) by using, for example, a ladder resistor, and generates voltages having 256 gradations of positive polarity and negative polarity.

  Two decoders DEC1 to DEC400 are set as one set, and one is configured to select a positive voltage and the other a negative voltage. Further, two output amplifiers AMP1 to AMP400 are set as one set, and one is configured to output a positive voltage and the other is a negative voltage. The output amplifiers AMP1 to AMP400 can be configured by voltage followers. Note that in this specification, the negative voltage may be a negative voltage with respect to the ground potential, but in a broad sense, the liquid crystal when the liquid crystal is AC driven is the liquid crystal central potential when the AC drive is AC. Means the lower voltage.

  In the present embodiment, display pixel data latched by the latch circuits LATi, LATi + 1 is placed between a pair of latch circuits LATi, LATi + 1 and a pair of decoders DECi, DETi + 1. A switching circuit 120 including switching gates CG1d, CG2d,... That is supplied to the next-stage decoders DECi, DECi + 1 without or intersecting is provided.

  On the other hand, on the liquid crystal panel 200 side, a signal applied to the external terminal is crossed between the external terminals P1, P2, P3... And the coupling nodes N1, N2, N3. Switching gates CG1p, CG2p,... That transmit to the coupling nodes N1, N2, N3,. The switching gates CG1d, CG2d,... And CG1p, CG2p,... Are switched almost simultaneously by the control signals CSd and CSp.

  The switches SW1, SW2, SW3,... Are selectively turned on in turn by three clocks φ1, φ2, φ3 having different phases as shown in FIG. Then, the output amplifiers AMP1 to AMP400 of the liquid crystal driver output drive signals of each color in the order of red (R), blue (B), and green (G) in synchronization with the clocks φ1, φ2, and φ3.

  At this time, the positive red driving signal (R +) and the blue driving signal (B +) at φ1 and φ2 are transferred to the odd group GO side, and the negative red driving signal (R−) and the blue driving signal (B−). Is supplied to the even group GE side. Subsequently, the switching circuits CG1a, CG2a,... And CG1b, CG2b,. To the GO side, the positive polarity green drive signal (G +) is supplied to the even-numbered group GE side.

  In this way, when the output of three signals from each output amplifier is completed within one horizontal period 1H, the switches SW1, SW2, SW3,... Are again selectively turned on in order by the clocks φ1, φ2, φ3. To be. Then, the output amplifiers AMP1 to AMP400 of the liquid crystal driver output drive signals of each color in the order of red (R), blue (B), and green (G) in synchronization with the clocks φ1, φ2, and φ3. At this time, first, at φ1, the negative red drive signal (R−) is supplied to the odd group GO side, and the positive red drive signal (R +) is supplied to the even group GE side. Subsequently, the switching circuit is switched, and in synchronization with φ2 and φ3, the positive blue drive signal (B +) and the green drive signal (G +) are sent to the odd group GO side, and the negative blue drive signal (B−) The green drive signal (G−) is supplied to the even number group GE side.

  It is possible to output red (R), green (G), and blue (B) in this order from the source line driving circuit, but as described above, red (R), blue (B), and green (G) By outputting each signal in this order, the switching frequency of the switching circuit can be reduced.

  That is, on the liquid crystal panel in which the pixels are arranged in the order of red (R), green (G), and blue (B), the drive signals of the signal lines are in the order of red (R), green (G), and blue (B). When output, it is necessary to switch the switching circuit every time. On the other hand, the switching circuits CG1d, CG2d,... And CG1p, CG2p,... Are switched every two dots by outputting each signal in the order of blue (B) and green (G) as in the embodiment. As a result, the frequency of the switching control signals CSd and CSp can be lowered to suppress an increase in power consumption.

  FIG. 3 shows an example of the overall configuration of the liquid crystal driver 100. In FIG. 3, the same circuit parts as those in FIG. A display data interface 160 that receives display image data supplied from the outside and sends it to the data latch unit 110 at a predetermined timing is provided in the preceding stage of the data latch unit 110.

  The liquid crystal driver 100 includes a power supply circuit 170 that generates voltages V0 to V17 and the like necessary for the gradation voltage generation circuit 150, a control circuit 180 that controls the entire chip, and a register unit that sets codes and data necessary for control. 191, a timing adjustment circuit 192 that adjusts the operation timing of the circuit inside the chip, and a level shift circuit 193 that outputs a signal for controlling the gate drive of the liquid crystal panel. One of the signals supplied from the level shift circuit 193 to the liquid crystal panel 200 is a signal VCOM applied to the common electrode.

  Further, the liquid crystal driver 100 reads / writes a serial interface 162 that exchanges signals with a system control device such as an MPU (microprocessor) that controls the entire system, and an external EPROM (nonvolatile memory). An EPROM interface 163 is provided. The timing adjustment circuit 192 has a function of generating and outputting a timing control signal for instructing operation timing to the data latch unit 110, the switching circuit 120, the decoder unit 130, the output unit 140, and the like.

  FIG. 4 shows a second embodiment of the source line driving circuit section and the liquid crystal panel of the liquid crystal driver to which the present invention is applied. In this embodiment, the liquid crystal panel is an amorphous liquid crystal panel. 1 differs from the embodiment of FIG. 1 in that switches SW1, SW2, SW3... For transmitting and blocking a signal applied to a source line provided on the liquid crystal panel 200 side in FIG. 1 and a switching gate CG1p. , CG2p,... Are provided on the liquid crystal driver 100 side. Other than that, it is substantially the same as the embodiment of FIG.

  FIG. 5 shows a third embodiment of the source line driver circuit portion and the liquid crystal panel of the liquid crystal driver to which the present invention is applied. In this embodiment, the liquid crystal panel is an LTPS liquid crystal panel. The difference from the embodiment of FIG. 1 is that in the embodiment of FIG. 1, the signal lines are grouped in groups of three and the signal lines are driven in three time divisions, whereas in this embodiment, six signal lines are used. The signal lines are configured to be grouped one by one and driven in 6 time divisions.

  In this embodiment, first, the switches SW1 and SW8 are turned on by the first clock φ1, and the positive red drive signal (R +) is sent to the signal line SL1 on the odd group GO side, and the negative green drive signal (G− ) Is supplied to the signal line SL8 on the even group GE side. Next, the switches SW3 and SW10 are turned on by the second clock φ2, and the positive blue drive signal (B +) is supplied to the signal line SL3 on the odd group GO side, and the negative red drive signal (R−) is an even number. The signal is supplied to the signal line SL10 on the group GE side.

  Subsequently, the switches SW5 and SW12 are turned on by the third clock φ3, the positive green drive signal (G +) is supplied to the signal line SL5 on the odd group GO side, and the negative blue drive signal (B−) is an even number. The signal is supplied to the signal line SL12 on the group GE side. Next, the switching gates CGd and CGp are switched, the switches SW2 and SW7 are turned on by the fourth clock φ4, and the negative green driving signal (G−) is positively connected to the signal line SL2 on the odd group GO side. Red driving signal (R +) is supplied to the signal line SL7 on the even-numbered group GE side.

  Thereafter, the switches SW4 and SW9 are turned on by the fifth clock φ5, the negative red drive signal (R−) is sent to the signal line SL4 on the odd group GO side, and the positive red drive signal (R +) is sent to the even group. The signal is supplied to the signal line SL9 on the GE side. Next, the switches SW6 and SW11 are turned on by the sixth clock φ6, the negative blue drive signal (B−) is sent to the signal line SL6 on the odd group GO side, and the positive green drive signal (G +) is even The signal is supplied to the signal line SL11 on the group GE side.

  Thereafter, the line, that is, the selection gate line is switched, and the above operation is repeated by the clocks φ1 to φ6. Incidentally, the negative red driving signal (R−) is supplied to the signal line SL1 at the first clock φ1 of the next line. As a result, the panel is driven by the dot inversion method. Further, unlike the first embodiment, since switching of the switching gates CGd and CGp is not required when the line changes, the number of switching of the switching gates CGd and CGp is reduced.

  In this embodiment, as in the first embodiment, since the signal lines are driven in a time division manner, the number of output amplifiers and decoders can be reduced, and a positive and negative pair of output amplifiers and positive amplifiers can be reduced. Since the negative tone selection decoder is shared by the two signal line groups GO and GE, the output amplifier and the tone selection decoder may be designed as a circuit exclusively for positive polarity or negative polarity. The circuit can be simplified and the chip size can be reduced. Further, since adjacent signal lines are not continuously driven, display flicker can be reduced.

  As in the embodiment of FIG. 4, even when the liquid crystal panel is an amorphous panel, the method of this embodiment is applied by providing the switch SW corresponding to the switching gate CGp and the signal line SL on the driver 200 side. be able to. Further, in the embodiment, the case of dot inversion driving has been described, but instead of inverting the polarity of each signal line every time the line changes as in the previous embodiment, the polarity of each signal line is changed to the previous frame every time the frame changes. It is also possible to drive the column inversion by changing the polarity to the polarity opposite to that at the time.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above-described embodiment, the case where the signal lines of the liquid crystal panel are grouped every three or six is described. However, the present invention is not limited to this, and every nine or 12 or an integral multiple of three. The present invention can be applied by grouping.

  In the above embodiment, the voltage follower is used as the output amplifier, but a differential amplifier or the like may be used. Further, the liquid crystal driver IC for receiving display data from the outside is shown in the above embodiment, but the present invention can also be applied to a liquid crystal display controller having a display RAM for storing display data inside the chip.

  In the above description, the invention made mainly by the present inventor has been described as being applied to a liquid crystal driver for driving a TFT color liquid crystal panel, which is the field of use behind it. However, the present invention is not limited thereto. In addition to color liquid crystal panels other than TFT, the present invention can also be applied to liquid crystal drivers for driving liquid crystal panels for monochrome display. The liquid crystal driver according to the present invention drives not only a small liquid crystal panel such as a liquid crystal panel for a mobile phone, but also a large liquid crystal panel such as a liquid crystal display for a television, a personal computer, and a liquid crystal monitor for a notebook computer. It can also be applied to.

It is a circuit block diagram which shows one Example of the source line drive circuit part and liquid crystal panel of the liquid crystal driver to which this invention is applied. 2 is a timing chart illustrating signal timings of respective units in the liquid crystal driver and the liquid crystal panel of the embodiment of FIG. 1. FIG. 2 is a block diagram illustrating a configuration example of the entire liquid crystal driver illustrated in FIG. 1. It is a circuit block diagram which shows the 2nd Example of the source line drive circuit part and liquid crystal panel of the liquid crystal driver to which this invention is applied. It is a circuit block diagram which shows the 3rd Example of the source line drive circuit part of the liquid crystal driver to which this invention is applied, and a liquid crystal panel. It is a circuit diagram which shows the structural example of the source line drive circuit part and liquid crystal panel of the conventional liquid crystal driver of a signal line time division drive system.

Explanation of symbols

100 Liquid crystal display drive device (Liquid crystal driver IC)
DESCRIPTION OF SYMBOLS 110 Data latch part 120 Switching circuit 130 Gradation voltage selection part 140 Output part 150 Gradation voltage generation circuit 200 Liquid crystal panel SL Signal line (source line)
GL scanning line (gate line)
DEC gradation voltage selection decoder (selector)
AMP output amplifier CGd, CGp switching gate

Claims (5)

A gradation voltage selection circuit for selecting a voltage to be applied to the signal line of a liquid crystal display panel including a plurality of scanning lines and a plurality of signal lines arranged so as to intersect the scanning lines according to display pixel data And an output circuit that outputs a voltage according to the voltage selected by the gradation voltage selection circuit,
The gradation voltage selection circuit and the output circuit are provided one by one for each signal line that is an integral multiple of 3 of the signal lines, and a gradation voltage selection circuit that selects a positive gradation voltage; An output circuit that outputs a positive voltage, a gradation voltage selection circuit that selects a negative gradation voltage, and an output circuit that outputs a negative voltage are provided in pairs,
Prior to the gradation voltage selection circuit, display pixel data is selectively transmitted to the gradation voltage selection circuit that selects the positive gradation voltage or the gradation voltage selection circuit that selects the negative gradation voltage. The switching circuit is configured to be switched after transmitting at least two sets of display pixel data to the positive polarity and negative polarity gradation voltage selection circuits. Liquid crystal display drive device. An output terminal corresponding to each signal line of the liquid crystal display panel, a switch provided corresponding to each of the output terminals and passing or blocking an output signal of the output circuit, and the output circuit and the switch. And a second switching circuit that selectively supplies an output signal of the positive polarity or negative polarity output circuit to the number of the integral multiples of 3 provided between the second switching circuit and the second switching circuit It is controlled in conjunction with the circuit, and the number of the integral multiples of the three is configured such that any one of them is sequentially turned on in a selection period of one scanning line at different timings. The liquid crystal display driving device according to claim 1, wherein A timing adjustment circuit that is provided corresponding to each signal line of the liquid crystal display panel and outputs a control signal for controlling a switch that passes or blocks the output signal of the output circuit; 3. The control signal according to claim 2, wherein the control signal is generated so that any one of an integral multiple of the switches is sequentially turned on within a selection period of one scanning line at different timings. Liquid crystal display drive device. 3. The switching circuit and the switch are controlled so that polarities of voltages applied to adjacent signal lines of the liquid crystal display panel are different within a selection period of one scanning line. The liquid crystal display drive device described. 5. The liquid crystal display driving device according to claim 4, wherein the switching circuit is controlled so as to invert the polarity of the voltage to be applied to each of the signal lines every time the selected scanning line is switched.

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