JP2003228351A - Liquid crystal driving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the load capacity of a data bus, to reduce the power consumption of the data bus and at the same time, to enhance the data transfer rate by separating the data latch bus and the data transfer bus of a cascade- connected liquid crystal driving device. <P>SOLUTION: In the liquid crystal driving device, suppression of power consumption of the data bus and high-speed data transfer become possible by providing a selector for separating the data latch bus and the data transfer bus and making only a bus being in operation to operate and by keeping a bus being in a standby in an operation stopping state while fixing the bus to an L state or to an H state. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving device incorporated in a liquid crystal driver for driving a TFT matrix color liquid crystal panel and used for a digital / analog converter for converting a digital color image signal into an analog voltage. It is a thing. When the liquid crystal driving device is integrated into a circuit, a TFT is formed on one semiconductor substrate.
A plurality of matrix color liquid crystal panels are arranged in parallel corresponding to the columns.

[0002]

2. Description of the Related Art FIG. 7A shows a liquid crystal display device using a conventional liquid crystal driving device.

A liquid crystal display device in which a liquid crystal driving device is mounted is for displaying an image by applying a potential difference to a liquid crystal layer filled between two opposing substrates.

The conventional liquid crystal driving device applies a signal potential to one electrode of the potential applied to the liquid crystal layer. A liquid crystal driving device is mounted with a large number of semiconductor integrated circuits of about 10 pieces, and display data, a data transfer clock, a display timing signal, and the like are applied to each liquid crystal driving device, and display is performed in row units (raster units).

In the conventional liquid crystal driving device shown in FIG. 7A, data applied to each liquid crystal driving device is supplied by a cascade connection between the liquid crystal driving devices.

FIG. 7A shows a case where the liquid crystal driving device is mounted by the COG method. Figure 7 (a)
The reference numeral 701 indicates a mutual cascade connection line.

Next, the operation of the conventional liquid crystal driving device will be described with reference to FIG.

A clock input signal 703, a start start signal 704, and image data 705 are input to the liquid crystal driving device 702. In addition to these, there is an image display control signal 702A, which controls analog conversion timing after data transfer, a reference voltage signal, and the like. These control signals are also propagated by cascade connection in FIG. 7B.

Clock signal 703 and start signal 704
Is input to the shift register unit 706, and the start signal is sequentially transferred in the shift register by the clock signal. The output 707 of the shift register unit 706 is input to the data latch unit 708.

The input image data 705 is temporarily held by the first stage latch 709 of the liquid crystal driving device 702, and then input to the data latch unit 708. This is performed in order to adjust the timing of data transfer in the conventional liquid crystal drive device connected in cascade.
The data latch unit 708 includes the shift register unit 706.
The output 707 from the data is sequentially latched.

When the data latch is completed, the liquid crystal driving device 702 transfers the clock output 711, the start signal 712 and the data signal 713 to the liquid crystal driving device 710 in the next stage. All data and control signals to the liquid crystal driving device 710 in the next stage and the liquid crystal driving devices subsequent thereto are propagated through the liquid crystal driving device 702.

Here, the image data 705 is basically R,
Each of G and B consists of 6 to 8 bits of binary data.
Although the number of data doubles, a means for reducing the data transfer rate by performing data transfer for two pixels, and conversely, a double data transfer by transferring data at every rising / falling edge of the clock There is a means to reduce the number of data buses depending on the speed. In the data output section, the output latch 720 adjusts the timing in order to secure a margin for the timing of fetching the data to the next stage due to the propagation delay of the data.

In a plurality of liquid crystal driving device groups connected in cascade, after the data transfer for one horizontal period (one raster cycle period) of the liquid crystal display device is completed, the DA converter 709 provided in each liquid crystal driving device causes After converting into an appropriate analog signal for displaying an image on the display device, current amplification is performed to display the image. The DA converter 709 includes a charge distribution method using a capacitance and a resistance division method.

After the display for one horizontal period is completed, a line to be displayed is selected by the liquid crystal driving device on the scanning side (generally called a gate driver), and the image data is transferred by the above-mentioned procedure, and the analog display data is displayed. Is converted to.

When data is transferred in a cascade connection and the clock signal propagates through a plurality of semiconductor integrated circuits, the clock signal is distorted due to the difference between the rising time and the falling time, and the liquid crystal driving device in the subsequent stage is distorted. Duty ratio 1:
In order to set to 1, a clock shaping means such as a PLL is taken.

[0016]

However, in the conventional liquid crystal drive device 702, the data transfer bus and the data latch bus are shared, so that the latch circuit element is always connected as a load to the data bus. However, there is a problem in that the power consumption of the buffer that drives the data bus increases.

Further, there is a problem that high-speed data transfer is difficult because the propagation delay of the data signal increases due to the load capacity of the data bus.

[0018]

In a first liquid crystal drive device, a plurality of divided data latch units and a data bus of a data latch unit that is not latching among the plurality of divided data latch units are provided. Since the control means for stopping the operation of the data bus is provided, it is possible to stop the data bus of the data latch section which is not latched and to operate the data bus only of the data latch section which is latched. The unnecessary load is reduced and the power consumption is reduced by dividing the load of the above into multiple operations.

In the second liquid crystal driving device, a plurality of shift register sections and a control means for stopping the clock operation of the shift register section that is not performing the shift operation among the plurality of shift register sections are provided. By preparing,
The clock load of the shift register unit is reduced to achieve low power consumption.

In the third liquid crystal drive device, a data transfer bus and a data latch bus are separated from each other, and a selector for selecting the operation of each data bus is provided. By operating the data latch bus and stopping the data transfer bus, only the data latch load operates. In addition, when transferring data to the next stage, the data latch bus is stopped, and on the other hand, only the data transfer bus is operated, so that it is possible to transfer with a light load during data transfer. Can be reduced and at the same time
By reducing the load capacity during data transfer, high-speed data transfer becomes possible.

In the fourth liquid crystal drive device, the number of data bus lines is reduced by multiplying and transferring the data transfer bus, decoding by the divided data bus, and performing data latch. In the case of a COG that mounts a frame like the conventional liquid crystal driving device, the reduction in the chip size of the semiconductor circuit leads to a reduction in the frame, so that the frame of the liquid crystal display device can be narrowed.

According to another aspect of the liquid crystal drive device of the present invention, a CMOS NA is used as the transfer clock buffer of the shift register section.
When circuits with different rise times / fall times such as ND and NOR are used, an even number of rise time / fall time asymmetric buffers are provided in order to shape the duty ratio to 1: 1. By arranging them so as to be inverted, clock distortion can be reduced.

According to another aspect of the present invention, the clock signal of the signal liquid crystal driver connected in cascade is inverted between the input phase and the output phase, and the timing of the output data and the output control signal of the signal liquid crystal driver is input. By setting the timing relationship between the data and the input control signal to be the same, it is possible to stabilize the duty of the clock signals that are cascade-connected to each other, and to enable stable operation of the system.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a liquid crystal drive device according to an embodiment of the first invention.

Reference numeral 101 denotes a first half data latch section when the data latch section is divided into two, and 102 denotes a second half data latch section. Reference numeral 103 is a selector for stopping the operation of the data bus of the first half data latch unit, 104 is a data bus for transferring data to the second half data latch unit, and 105
Is a latch that temporarily latches the data signal to the data latch unit in the latter half to adjust the timing, 106 is a selector for stopping the operation of the data bus of the data latch unit in the latter half, and 107 is the next-stage liquid crystal drive It is a bus for transferring data to the device.

The operation of the liquid crystal drive device of the first invention will be described.

As a state before data is input, the selector 103 which is the first half data bus control means is in the operation start state, and the selector 10 which is the second half data bus control means.
No. 6 is in a stopped state. These controls are generated from the shift register unit. These controls are based on the data latch signal generated when the start signal is input to the shift register section and the start signal is sequentially shifted and transferred, and the operation state of the first half data latch section or the second half data latch section is changed. Since it can be determined, it is possible to generate a control signal.

When the data is input, the first half data latch is put into the operation start state.

Similar to the conventional example, the operation of the first half data latch section is performed by the latch data from the shift register section, and when the first half data latch section is completed, the operation of the selector 103 is stopped by the CARRY2 signal from the shift register section. Then, the output of the selector 103 is fixed to L or H and the operation of the data bus is stopped.

Next, the selector 106 of the data latch section of the latter half section carries the carry signal CAR of the shift register of the latter half section.
The operation is started by RY2, and the data bus of the selector 2 becomes operable. The control of CARRY2 is performed by the CARRY1 signal of the shift register section in the first half.
The control signal can be generated since the operation of the second half shift register is started.

The data from the first half is temporarily latched by the latch 10 for adjusting the latch timing to the data latch in the second half.
After being held at 5, the operation of the latter half is started.

After the latch operation of the second half data latch section is completed, the operation of the selector 106 is stopped by CARRY2 of the shift register section, and the output of the selector 106 is fixed to L or H.

According to the liquid crystal driving device of the first invention, the data latching operation is divided and performed in the liquid crystal driving device.
Since the operation of the data transfer bus can be stopped during the latch operation of the first half and the latch operation of the second half can be stopped, the load of operating the bus can be reduced.

In the latter half of the data latch operation,
Since the data latch bus in the first half is stopped, the operation of the data bus can be reduced as described above.

In the present embodiment, the operation with two divisions has been described, but if the division operation with n divisions (n is an integer) is performed,
Further, the power consumption can be reduced.

Next, a liquid crystal drive device according to an embodiment of the second invention will be described.

In the second embodiment, the power consumption of the shift register section is reduced. In FIG. 2, reference numeral 201 denotes the same control signal as the data latch completion signal CARRY2 of the shift register portion in the first half portion. A power control unit 202 receives the CARRY2 signal 201 and controls the operation of the shift register unit and the data bus selector. Reference numeral 203 denotes a control signal output from the power control unit 202 and input to the data bus selector to stop the operation by fixing the bus operation to L or H when the data latch operation is not performed. Reference numeral 204 is an operation control signal of a transfer clock used in the shift register section. Reference numeral 205 denotes a control signal for controlling the operation start of the shift register section in the latter half when the operation of the shift register section in the first half is completed.

Next, the operation of the liquid crystal drive device according to the embodiment of the second invention will be described.

The clock, the start signal and the data are input to the first half, and the data latch operation is started for the data latch of the first half as in the first embodiment. Next, when the first half data latch operation is completed, a completion signal CA
RRY2 is output from the shift register unit to the power control unit 202.

From the power control unit 202, the CARRY
In response to the signal of 2, the data bus selector stops the operation of the data latch bus. In addition, the power control unit 20
From 2 the control signal 204 for stopping the shift register operation of the first half is output to the shift register section, and the shift register operation of the first half is stopped.

The clock output 206 to the shift register section in the latter half section stops the clock output while the shift register section in the first half section is operating, and is controlled by the control signal 204 from the power control section 202 in the first half section. When the operation of the shift register section of the above section is completed, the output of the clock 206 is started in order to start the operation of the shift register section of the latter half section.

After the operation of the first half is completed, the latter half is
The same operation as in the embodiment of

According to the embodiment of the second aspect of the invention, the clock control of the shift register section is performed, so that the power consumption of the clock signal can be reduced.

Next, FIG. 3 shows a circuit diagram of a liquid crystal drive device according to an embodiment of the third invention.

Reference numeral 301 denotes an input data output from the first stage latch 709, which is divided into a data latch bus used for data latch in the liquid crystal drive device and a data transfer bus to the next stage liquid crystal drive device. , 302 is a bus for transferring to the liquid crystal driving device at the next stage, 303 is generated from the shift register 606, and indicates that the internal data latch is completed, and the selector 301 is used for data transfer. It is a switching selection signal for switching the operation to the bus.

Next, the operation of the liquid crystal driving device of the third embodiment of the invention will be described.

The data, clock and start signal input to the liquid crystal driving device of the present invention are the same as those of the conventional liquid crystal driving device. The input data is temporarily held by the first stage latch. The selector 301 is initially selected so that the internal data latch bus operates. Therefore, the input data is sent from the latch 709 to the data latch unit 708.

On the other hand, the shift register sequentially transfers the start signal similarly to the conventional example, and the output 707 of the shift register causes the data latch in the data latch section.

At this time, as for the output of the selector 301, the data latch bus operates as in the conventional example, but the data transfer bus is fixed to L or H, so that power consumption by the data transfer bus does not occur.

When the necessary shift is completed in the shift register section 706, the carry signal CARRY1 is used to send the operation start timing to the liquid crystal drive device in the next stage. In addition to the carry signal CARRY1, the internal data latch is completed. This indicates that CARRY2 for controlling the operation of the selector 301 is generated and input to the selector 301.

In the selector 301, the operation of the internal data bus is stopped by fixing the data bus to the internal data bus to L or H according to the CARRY2 signal 303. On the other hand, the data transfer bus starts its operation by this CARRY2 signal 103.

In this way, the data bus selector 301
The bus switching signal 303 from the shift register selects a bus that needs to be operated, so that an unnecessary load is not generated and power consumption by the bus is reduced.

In the present invention, it has been described that the selector operates simultaneously with the switching of the internal data bus and the data transfer bus. Although a simultaneous suspension period may occur, even in this case, since the switching operation can be completely realized during the main time, low power consumption can be realized.

Next, a liquid crystal drive device according to an embodiment of the fourth invention will be described.

In addition to the embodiment of the third invention, FIG. 4 is provided with a data multiplication unit 401 in the data transfer bus in the first half and a data multiplication unit 402 in the same circuit in the data transfer bus in the second half.

The purpose of the data multiplication section is to reduce the width of the data bus passing between the liquid crystal driving devices.
As the multiplication means, a data signal transferred in synchronization with either the rising edge or the falling edge of the clock and input is transferred in synchronization with the rising or falling edge of the clock to transfer the data. Speed 2
The data bus width can be reduced to 1/2 as a result. Further, by using a PLL inside the liquid crystal driving device,
When the data is doubled and transferred, the number of data lines can be reduced to 1 / n.

After the data is multiplied and transferred, the second,
When the data latch unit is divided and the operation is controlled as in the third embodiment of the invention, the decoding unit 403 restores the data before sending the latch data to the latter half.

According to the fourth embodiment of the present invention, the bus width of the data transfer bus can be reduced to 1/2 to 1 / n (n is an integer multiplication number). The chip size can be reduced. In particular, when mounting on a liquid crystal display device by the COG method, the mounting area of the frame can be reduced, so that a narrow frame type liquid crystal drive device can be realized.

Next, a liquid crystal driving device according to an embodiment of the present invention will be described.

In the third and fourth inventions, the shift register section is provided with the clock control circuit. This clock control circuit is an N-type CMOS composed of 501 as shown in FIG.
It is an AND gate. In the liquid crystal drive device of the present invention as defined in claim 1, an even number of NAND gates are arranged in the first half and the second half, and the outputs of the respective NAND gates are arranged so as to be always inverted.

As the clock shaping circuit, a PLL circuit or the like as shown in the conventional example can be considered, but generally the PLL has a large circuit scale and is not practical in a small chip size liquid crystal drive device applied to a narrow frame. Therefore, it is desirable that the clock shaping circuit be shaped based on the inverter buffer.

The inverter composed of CMOS is a PMO
By setting the size according to the capability ratio of S and NMOS, it is possible to design the output rising time tPLH and the falling time tPHL to be equal. But the CMO
A NAND or NOR gate composed of S
In this case, since the NMOS transistors are connected in series, the substrate bias effect is different, so that the time between tPLH and tPHL differs depending on the state of the input signal. Similarly NO
In the case of R, since the PMOS transistors are connected in series, there is a difference between tPLH and tPHL depending on the state of the input signal.

In the liquid crystal drive device according to the first embodiment of the present invention, an even number of NAND gates are used when the NAND gates are used for clock control. In FIG. 5, if one NAND gate is provided in the first half and one is provided in the latter half, and the output of each NAND gate is inverted, the tPLH
And tPHL cancel each other out, so that the clock signal can be propagated without deteriorating the duty ratio.

Next, a liquid crystal driving device according to an embodiment of the present invention will be described with reference to FIG.

In FIG. 6, reference numerals 601 to 603 denote liquid crystal driving devices connected in cascade. The input clock signal of the liquid crystal driving device 602 is CLK_2_in, the input data signal is Dxx_2_in, and the input control signal is CTL_2_in. On the other hand, the output clock signal is CLK_2_out, the output data signal is Dxx_2_out, and the output control signal is C.
TL_2_out.

The timing of the input data is as shown in FIG. 6B, the input data Dxx_2_in and the input control signal CTL_2_in that are effective as the input of the liquid crystal driving device 602.
Is VALID, in the case of FIG. 6B, the liquid crystal driving device 602 is driven at the rising edge of the input clock CLK_2_in.
After the data is taken in and the data is taken in, the data is transferred to the liquid crystal drive device 603 in the next stage.

The clock, data and control signals are sent from the output of the liquid crystal driving device 602 to the liquid crystal driving device 603 in the next stage. In this case, the clock signal is the liquid crystal driving device 6
CLK_2_out that is the reverse of the phase of the input of 02 is output. Although the clock is inverted, the clock CLK_2_out, the data Dxx_2_out, and the control signal CTL_2_o when input to the liquid crystal drive device 603 in the next stage are input.
As in the case of input, ut has a relationship of being taken in in synchronization with the rising edge of the clock.

A propagation delay time td 604 is generated when a clock passes through the liquid crystal driving device 602, but it is not related to the phase inversion.

In the liquid crystal drive device according to the second aspect, the phases of the cascade-connected clocks are inverted and transmitted, and the relationship between the input clock and the data and the control signal and the relationship between the output clock, the data and the control signal are shown. By making the same, it is possible to reduce the duty distortion of the clock generated when passing through the liquid crystal drive device.

When operated by the in-phase clock, the liquid crystal drive device composed of the semiconductor integrated circuit is changed to the H level of the clock cascade-connected to the next stage due to variations in the characteristics of the Pch transistor and the Nch transistor due to variations in the diffusion process. , Deviation of the L level signal width occurs,
If the number of cascaded stages is large, there is a risk of malfunction, but in the liquid crystal drive device according to the second aspect, by inverting and connecting the clocks, characteristic variations are averaged and stable operation can be achieved.

[0072]

According to the first liquid crystal driving device, the data latch unit and the shift register unit of the liquid crystal driving device are divided into integers, and thus the data latch unit to be operated can be divided and latched. The power consumption can be reduced by stopping the operation of unnecessary circuits.

According to the second liquid crystal drive device, it is possible to reduce the power consumption by performing the clock division operation of the shift register section.

According to the third liquid crystal drive device, in the liquid crystal drive device connected in cascade, the data latch bus and the data transfer bus for the cascade are switched by the selector so that only the data latch bus is latched at the time of data latch. When the data is transferred, the operation of the data latch bus is stopped, so that the load on the data bus can be reduced and the power consumption can be reduced.

Further, since the load during data transfer is reduced, high speed data transfer becomes possible.

According to the fourth liquid crystal drive device, when data is transferred, the data can be multiplied and transferred to reduce the bus width of the data bus. When the liquid crystal drive device is a semiconductor integrated circuit, The chip size can be reduced,
In particular, when the liquid crystal driving device is mounted by the COG method, a liquid crystal display device with a narrow frame can be realized.

According to the liquid crystal drive device of the first aspect, in the clock buffer for controlling the clock operation, an even number of buffer circuits having asymmetric rise / fall times are used, and the output of each buffer is inverted. As a result, the clock can be shaped without using a large-scale circuit such as a PLL, and a highly accurate clock signal transfer can be performed with a small circuit scale.

According to the liquid crystal driving device of the second aspect, the clocks included in the control signals are cascade-connected, and the input phase and the output phase of the signal liquid crystal driver are inverted, and the output data of the signal liquid crystal driver is obtained. By making the timing relationship of the output control signal the same as the timing relationship of the input data and the input control signal, clock shaping can be performed and clock signal transfer with term accuracy becomes possible.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the first invention.

FIG. 2 is a diagram showing an embodiment of a second invention.

FIG. 3 is a diagram showing an embodiment of a third invention.

FIG. 4 is a diagram showing an embodiment of a fourth invention.

FIG. 5 is a diagram showing an embodiment of the present invention according to claim 1;

FIG. 6 is a diagram showing an embodiment of the present invention according to claim 2;

FIG. 7 is a diagram showing a conventional liquid crystal drive device.

[Explanation of symbols]

202 power control unit 301 selector 401 multiplier 706 shift register section 708 data latch section 709 DA converter

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kazuyoshi Nishi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 2H093 NA06 NC11 NC21 NC22 NC26                       NC49 ND34 ND37 ND39                 5C006 AF68 AF72 AF82 BB16 BC12                       BC24 BF03 BF04 BF24 BF26                       BF27 EB05 FA13 FA47                 5C080 AA10 BB05 DD08 DD26 FF11                       JJ02 JJ04 JJ06

Claims (2)

[Claims] 1. A liquid crystal driver for each signal transmits data and a control signal, and with respect to a clock included in the control signal, an even number of asymmetric buffers having different rise times and fall times are transmitted. The liquid crystal drive device is characterized in that the outputs of the two are mutually inverted. 2. Data and control signals of each signal liquid crystal driver are cascade-connected between the respective drivers, and with respect to a clock included in the control signal, an input phase and an output phase of the signal liquid crystal driver are inverted, A liquid crystal driving device, wherein a timing relationship between output data of the signal liquid crystal driver and an output control signal is the same as a timing relationship between input data of the signal liquid crystal driver and an input control signal.