JP3460651B2 - Liquid crystal drive - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving device incorporated in a liquid crystal driver for driving a TFT matrix color liquid crystal panel and used for a digital / analog converter for converting a digital color image signal into an analog voltage. It is a thing. When the liquid crystal driving device is integrated into a circuit, a TFT is formed on one semiconductor substrate.
A plurality of matrix color liquid crystal panels are arranged in parallel corresponding to the columns.

[0002]

BACKGROUND OF THE INVENTION FIGS. 3 (a) shows a liquid crystal display device using the conventional liquid crystal driving device.

A liquid crystal display device in which a liquid crystal driving device is mounted is for displaying an image by applying a potential difference to a liquid crystal layer filled between two opposing substrates.

The conventional liquid crystal driving device applies a signal potential to one electrode of the potential applied to the liquid crystal layer. A liquid crystal driving device is mounted with a large number of semiconductor integrated circuits of about 10 pieces, and display data, a data transfer clock, a display timing signal, and the like are applied to each liquid crystal driving device, and display is performed in row units (raster units).

[0005] In the conventional liquid crystal drive apparatus shown in FIG. 3 (a) the data applied to the respective liquid crystal driving device, and supplies the cascade connection between the liquid crystal drive apparatus other.

[0006] FIGS. 3 (a) In the liquid crystal driving device shows a case that is implemented by a COG method. Figure 3 (a)
The reference numeral 701 indicates a mutual cascade connection line.

[0007] Next will be described the operation of the conventional liquid crystal drive apparatus with reference to FIG. 3 (b).

A clock input signal 703, a start start signal 704, and image data 705 are input to the liquid crystal driving device 702. In addition to these, there is an image display control signal 702A, which controls analog conversion timing after data transfer, a reference voltage signal, and the like. These control signals are also propagated by cascade connection in FIG. 3 (b).

Clock signal 703 and start signal 704
Is input to the shift register unit 706, and the start signal is sequentially transferred in the shift register by the clock signal. The output 707 of the shift register unit 706 is input to the data latch unit 708.

The input image data 705 is temporarily held by the first stage latch 709 of the liquid crystal driving device 702, and then input to the data latch unit 708. This is performed in order to adjust the timing of data transfer in the conventional liquid crystal drive device connected in cascade.
The data latch unit 708 includes the shift register unit 706.
The output 707 from the data is sequentially latched.

When the data latch is completed, the liquid crystal driving device 702 transfers the clock output 711, the start signal 712 and the data signal 713 to the liquid crystal driving device 710 in the next stage. All data and control signals to the liquid crystal driving device 710 in the next stage and the liquid crystal driving devices subsequent thereto are propagated through the liquid crystal driving device 702.

Here, the image data 705 is basically R,
Each of G and B consists of 6 to 8 bits of binary data.
Although the number of data doubles, a means for reducing the data transfer rate by performing data transfer for two pixels, and conversely, a double data transfer by transferring data at every rising / falling edge of the clock There is a means to reduce the number of data buses depending on the speed. In the data output section, the output latch 720 adjusts the timing in order to secure a margin for the timing of fetching the data to the next stage due to the propagation delay of the data.

In a plurality of liquid crystal driving device groups connected in cascade, after the data transfer for one horizontal period (one raster cycle period) of the liquid crystal display device is completed, the DA converter 709 provided in each liquid crystal driving device causes After converting into an appropriate analog signal for displaying an image on the display device, current amplification is performed to display the image. The DA converter 709 includes a charge distribution method using a capacitance and a resistance division method.

After the display for one horizontal period is completed, a line to be displayed is selected by the liquid crystal driving device on the scanning side (generally called a gate driver), and the image data is transferred by the above-mentioned procedure, and the analog display data is displayed. Is converted to.

When data is transferred in a cascade connection and the clock signal propagates through a plurality of semiconductor integrated circuits, the clock signal is distorted due to the difference between the rising time and the falling time, and the liquid crystal driving device in the subsequent stage is distorted. Duty ratio 1:
In order to set to 1, a clock shaping means such as a PLL is taken.

[0016]

However, in the conventional liquid crystal drive device 702, the data transfer bus and the data latch bus are shared, so that the latch circuit element is always connected as a load to the data bus. However, there is a problem in that the power consumption of the buffer that drives the data bus increases.

Further, there is a problem that high-speed data transfer is difficult because the propagation delay of the data signal increases due to the load capacity of the data bus.

[0018]

[0019]

According to another aspect of the liquid crystal drive device of the present invention, the data transfer bus and the data latch bus are separated from each other, and a selector for selecting the operation of each data bus is provided. When the data latch is performed, the data latch bus is operated, while the data transfer bus is stopped so that only the load for the data latch is operated. In addition, when transferring data to the next stage, the data latch bus is stopped, and on the other hand, only the data transfer bus is operated, so that it is possible to transfer with a light load during data transfer. Can be reduced, and at the same time, high-speed data transfer can be achieved by reducing the load capacity during data transfer.

In the liquid crystal driving device according to the third aspect of the present invention, the number of data bus lines is reduced by multiplying and transferring the data transfer bus, decoding the divided data bus and performing data latch. In the case of a COG that mounts a frame like the conventional liquid crystal driving device, the reduction in the chip size of the semiconductor circuit leads to a reduction in the frame, so that the frame of the liquid crystal display device can be narrowed.

[0022]

[0023]

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

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[0044]

Next, FIG. 1 shows a circuit diagram of a liquid crystal drive device according to an embodiment of the present invention described in claims 1 and 2 .

Reference numeral 301 denotes an input data output from the first stage latch 709, which is divided into a data latch bus used for data latch in the liquid crystal drive device and a data transfer bus to the next stage liquid crystal drive device. , 302 is a bus for transferring to the liquid crystal driving device at the next stage, 303 is generated from the shift register 606, and indicates that the internal data latch is completed, and the selector 301 is used for data transfer. It is a switching selection signal for switching the operation to the bus.

[0047] Next will be described the operation of the LCD control system of an embodiment of the present invention of claim 1, wherein.

The data, clock and start signal input to the liquid crystal driving device of the present invention are the same as those of the conventional liquid crystal driving device. The input data is temporarily held by the first stage latch. The selector 301 is initially selected so that the internal data latch bus operates. Therefore, the input data is sent from the latch 709 to the data latch unit 708.

On the other hand, the shift register sequentially transfers the start signal similarly to the conventional example, and the output 707 of the shift register causes the data latch in the data latch section.

At this time, as for the output of the selector 301, the data latch bus operates as in the conventional example, but the data transfer bus is fixed to L or H, so that power consumption by the data transfer bus does not occur.

When the necessary shift is completed in the shift register section 706, the carry signal CARRY1 is used to send the operation start timing to the liquid crystal drive device in the next stage. In addition to the carry signal CARRY1, the internal data latch is completed. This indicates that CARRY2 for controlling the operation of the selector 301 is generated and input to the selector 301.

In the selector 301, the operation of the internal data bus is stopped by fixing the data bus to the internal data bus to L or H according to the CARRY2 signal 303. On the other hand, the data transfer bus starts its operation by this CARRY2 signal 103.

In this way, the data bus selector 301
The bus switching signal 303 from the shift register selects a bus that needs to be operated, so that an unnecessary load is not generated and power consumption by the bus is reduced.

In the present invention, it has been described that the selector operates simultaneously with the switching of the internal data bus and the data transfer bus. Although a simultaneous suspension period may occur, even in this case, since the switching operation can be completely realized during the main time, low power consumption can be realized.

[0055] Next, the liquid crystal driving device of an embodiment of the present invention described in claim 3 will be described.

In addition to the embodiments of the present invention as set forth in claims 1 and 2, FIG. 2 shows a data multiplication unit 40 in the data transfer bus in the first half.
1. The data multiplying unit 402 of the same circuit is provided in the data transfer buses of the first and second half parts.

The purpose of the data multiplication section is to reduce the width of the data bus passing between the liquid crystal driving devices.
As the multiplication means, a data signal transferred in synchronization with either the rising edge or the falling edge of the clock and input is transferred in synchronization with the rising or falling edge of the clock to transfer the data. Speed 2
The data bus width can be reduced to 1/2 as a result. Further, by using a PLL inside the liquid crystal driving device,
When the data is doubled and transferred, the number of data lines can be reduced to 1 / n.

After the data is multiplied and transferred, and when the data latch section is divided and the operation is controlled as in the embodiments of the present invention described in claims 2 and 3, before the latch data is sent to the latter half section. Causes the decoding unit 403 to restore the data.

According to the third embodiment of the present invention, the bus width of the data transfer bus can be reduced to 1/2 to 1 / n (n is an integer multiplication number), and the semiconductor integrated circuit. Can reduce the chip size when
When mounting on a liquid crystal display device by the OG method, the mounting area of the frame can be reduced, so that a narrow frame type liquid crystal drive device can be realized.

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[0074]

Effects of the Invention] According to the liquid crystal driving device according to claim 1, wherein, in the liquid crystal driving device be cascaded, by switching the data transfer bus for data latching bus and cascade selector, when data latched in the Only the data latch bus operates, and the operation of the data latch bus stops during data transfer, so that the load on the data bus can be reduced and the power consumption can be reduced.

Further, since the load during data transfer is reduced, high speed data transfer becomes possible.

According to the liquid crystal driving device of the third aspect , when the data is transferred, the bus width of the data bus can be reduced by multiplying and transferring the data, and the liquid crystal driving device is a semiconductor integrated circuit. In this case, the chip size can be reduced, and particularly when the liquid crystal driving device is mounted by the COG method, a liquid crystal display device with a narrow frame can be realized.

[0077]

[0078]

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention according to claims 1 and 2 .

FIG. 2 is a diagram showing an embodiment of the present invention according to claim 3 ;

FIG. 3 is a diagram showing a conventional liquid crystal drive device.

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-8-30239 (JP, A) JP-A-10-282939 (JP, A) JP-A-11-249626 (JP, A) JP-A-9- 16128 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 505 G09G 3/20 623

Claims (3)

(57) [Claims] 1. In a signal liquid crystal driver in which data and control signals are cascade-connected between respective signal liquid crystal drivers, a data latch unit for holding a data signal and data latch data for connecting data to the data latch unit. A liquid crystal driving device comprising: a bus; a cascade data transfer bus different from the data latch data bus; and a selector for controlling the data latch data bus and the cascade data transfer bus. 2. The liquid crystal drive device according to claim 1, wherein the operation of the cascade data transfer bus of the signal liquid crystal driver is stopped while the data latch unit is latching. 3. The liquid crystal drive device according to claim 1, wherein the data transfer bus of the signal liquid crystal driver includes a multiplication means for reducing the data bus width.