JP2000162577A - Flat display device, array substrate and drive method for flat display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flat display device preventing deterioration in display quality such as that contrast is lowered partially from occurring. SOLUTION: The signal line drive circuit of this liquid crystal display device is provided with a shift register 1, a shift control circuit 2, OR gates 31-3n, buffers 41-4n and an analog switch 5, and the shift register 1 is provided with a first register group 11 and a second register group 12. The first register group 11 shifts successively a start pulse. The second register group 12 shifts successively the register output of the final stage of the first register group 11. When the shift pulse is outputted from the register of the final stage of the second register group 12, all analog switches 5 are turned on, and all video bus lines L1-Ln are set in middle potential synchronized with this timing. Thus, all signal lines are precharged to the middle potential in a blanking interval.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a signal line of a flat display device such as a liquid crystal display device in which signal lines and scanning lines are arranged in a row.

[0002]

2. Description of the Related Art A flat display device represented by an active matrix type liquid crystal display device using a thin film transistor is widely used in a display device such as a computer because of its excellent high-speed response and high definition. 2. Description of the Related Art With the spread of portable devices such as notebook computers, great interest has been paid to a liquid crystal display device integrated with a driving circuit in which a liquid crystal display portion and a driving circuit portion are formed on the same substrate in the same process.

FIG. 5 is a block diagram showing a schematic configuration of a signal line driving circuit of a liquid crystal display device of this type integrated with a driving circuit. The signal line drive circuit of FIG. 5 includes a shift register 51 for sequentially shifting a start pulse XST input from the outside.
And buffers 41 to 4n connected to respective output terminals of the shift register 51, and an analog switch 5 that is turned on / off by output signals of the buffers 41 to 4n.

The signal line drive circuit shown in FIG. 5 performs a so-called block sequential drive in which a plurality of signal lines are driven simultaneously as one block. By performing such block sequential driving, the shift clocks XCK and / XCK of the shift register 51 are output.
Of the signal lines S1,
Since the number of S2,..., Sn can be increased, high definition display is possible.

FIG. 6 is a timing chart of input / output signals of the signal line driving circuit of FIG. 5, showing an example of performing V-line inversion driving.

Hereinafter, the operation of the circuit shown in FIG. 5 will be described with reference to FIG. Clocks XCK and / XCK whose logics are inverted to each other are input to the shift register 51. When the start pulse XST is input at time T11 in FIG.
The shift register 51 starts a shift operation, and each output terminal of the shift register 51 sequentially outputs a shift pulse.

For example, when a shift pulse is output from the output terminal of the shift register 51 at time T12 in FIG. 6, the analog switch 5 connected to this output terminal is turned on and connected to the analog switch 5. The voltage of the video bus line is supplied to the corresponding signal line and charged.
Thereafter, when the analog switch 5 is turned off at time T13 in FIG. 6, the voltage charged through the analog switch 5 is held on the signal line immediately before the analog switch 5 is turned off.

As a method of driving the signal lines, in addition to the frame inversion drive in which the polarity of the voltage with respect to the reference potential is switched for each screen in order to prevent the deterioration of the liquid crystal, the method is combined with the frame inversion drive and further flickers. As a driving method for reducing the occurrence of the occurrence, there are V line inversion driving in which the polarity of the voltage with respect to the reference potential differs for each adjacent signal line,
Alternatively, there is H-line inversion driving in which the polarity of the voltage with respect to the reference potential is switched for each of a plurality of horizontal lines, or HV inversion driving in which the polarity of the voltage with respect to the reference potential is switched in pixel units.

FIG. 7 is a timing chart of each part in the signal line driving circuit when H-line inversion driving is performed. The control signal input to the control terminal of the analog switch 5 and the video bus line The voltages on L1 to Lm and the signal line voltage are shown. In FIG. 7, the voltage level on the positive polarity side is 5.5 V for white and 9.5 V for black, and the voltage level on the negative polarity side is 4.5 V for white and 0.5 V for black.

FIG. 7 shows an example in which a black level voltage is held on the signal line at time T11, and this voltage is held until the next horizontal line period. Time T12 to T13 is a horizontal blanking period, and after time T13, the next horizontal line is displayed.

In the case of the H-line inversion drive or the HV inversion drive, for example, the polarity of the signal line voltage is switched with respect to the reference voltage for each horizontal line.
A pixel voltage having a negative polarity with respect to the reference voltage is supplied to the video bus line. FIG. 7 shows an example in which two adjacent horizontal lines are both set to the black level.

As described above, the H line inversion drive or HV
In the case of performing inversion driving, it is necessary to invert the polarity of the signal line voltage with respect to the reference voltage at a predetermined timing within one frame period. I have to change. For example, to set both adjacent horizontal lines to the black level, the potential difference between the two signal lines must be 9.5V-
0.5V = 9V.

However, when the block sequential driving as shown in FIG. 5 is performed, the period during which the analog switch 5 is on is several hundreds.
Since it is only nsec, it is difficult to rapidly change the voltage of the video bus line and further the voltage of the signal line during the ON period of the analog switch 5.

On the other hand, in order to set both adjacent horizontal lines to the white level, the potential difference between the two horizontal lines is 5.5 V-4.5.
V = 1.0 V, which is sufficiently smaller than the potential difference of 9 V in the case of the black level.
It is relatively easy to set the signal line to a desired voltage.

As described above, when H line inversion driving or HV inversion driving is performed in the conventional liquid crystal display device, the polarity of the voltage of the signal line must be switched for each predetermined horizontal line. Since the change width of the signal line voltage is larger, the writing failure to the signal line is more likely to occur, and the display failure such as lowering of the contrast occurs.

On the other hand, when the V-line inversion drive is performed, since the polarity is not inverted for each horizontal line, a decrease in contrast due to insufficient writing of the signal line voltage due to the above-described polarity inversion does not occur. However, the polarity of the horizontal line to be written immediately after the end of the vertical blanking period is different from the signal line voltage of the immediately preceding horizontal line, as in the case of performing the H-line inversion drive.
For example, as the color is closer to black, writing failure to the signal line is more likely to occur, the contrast is lower than that of other horizontal scanning lines, and the display quality is degraded, for example, a bright line appears on the screen.

As a technique for preventing the deterioration of display quality due to such an error of the signal line voltage, Japanese Patent Application Laid-Open No. 6-202076 discloses a technique of precharging a signal line capacitance during a blanking period, There is disclosed a technique for suppressing an influence on a pixel due to a voltage change.

FIG. 8 is a circuit diagram of the liquid crystal display device disclosed in the above-mentioned publication. The device shown in FIG. 8 includes a signal line driving circuit 60 including a first register group 60a and a second register group 60b, and turns on all the TFTs 61 connected to each signal line S in a blanking period. At the same time, the TFT 62 is turned on by the shift pulse output from the second register group 60b, and the reset signal line 63
Is used to precharge each signal line S.

[0019]

However, the liquid crystal display device disclosed in the publication of FIG. 8 aims at precharging the signal line S, and does not precharge the video bus. Therefore, when the load on the video bus is heavy, it takes time for the video bus to reach a desired voltage after the blanking period ends, so that the pixel displayed immediately after the blanking period and the other pixels are displayed. And uneven brightness may occur between them. Further, in the case of the device shown in FIG. 8, a reset signal line for precharging the signal line is indispensable, and there is a problem that the number of wirings in the array substrate increases.

The present invention has been made in view of such a problem, and has as its object to provide a flat display device, an array substrate, and a display device that do not cause deterioration in display quality such as a partial decrease in contrast. And a method for driving the flat panel display device.

[0021]

According to a first aspect of the present invention, a plurality of signal lines and a plurality of scanning lines arranged in rows and columns are connected to respective intersections through switching elements. A pixel electrode, a signal line driving circuit for supplying an analog video signal from a video control circuit to each of the signal lines, and a scanning line driving circuit for supplying a scanning pulse to each of the scanning lines are formed on an insulating substrate. A flat panel display device comprising: an array substrate, and an opposing substrate disposed on the array substrate with a light modulation layer interposed therebetween, wherein the signal line drive circuit includes a shift circuit in which a plurality of flip-flops are cascaded. A register, a bus line for transferring the analog video signal from the video control circuit, and each of the flip-flops connected between each of the signal lines and the bus line. And an analog switch for supplying the analog video signal on the bus wiring to each of the signal lines based on a force, wherein the video control circuit is configured to control at least one of the horizontal and vertical blanking periods. A predetermined period is set as a precharge period, and a voltage on the bus line is set to a substantially center voltage of a maximum and a minimum voltage of the analog video signal in a corresponding video bus line.

According to a fifteenth aspect of the present invention, there is provided a pixel electrode connected via a switching element to each intersection of a plurality of signal lines and scanning lines arranged in rows and columns, and an analog video signal from a video control circuit. A signal line driving circuit that supplies each of the lines, a scanning line driving circuit that supplies a scanning pulse to each of the scanning lines, an array substrate formed on an insulating substrate, and a light modulation layer on the array substrate. And a counter substrate disposed so as to face the substrate, and a bus line for transferring the analog video signal from the video control circuit is connected to each of the signal lines via an analog switch. Wherein the video control circuit comprises:
A predetermined period in at least one of the horizontal and vertical blanking periods is set as a precharge period, and a voltage on the bus line is set to a substantially center voltage of a maximum and a minimum voltage of the analog video signal in the corresponding bus line.

According to a sixteenth aspect of the present invention, there is provided a pixel electrode connected via a switching element to each intersection of a plurality of signal lines and scanning lines arranged in rows and columns, and an analog video signal from a video control circuit. A signal line driving circuit that supplies each of the lines, a scanning line driving circuit that supplies a scanning pulse to each of the scanning lines, an array substrate formed on an insulating substrate, and a light modulation layer on the array substrate. And a counter substrate disposed to face through the flat display device,
The signal line driving circuit includes a shift register in which a plurality of flip-flops are cascaded, a bus line for transferring the analog video signal from the video control circuit, and a bus line between each of the signal lines and the bus line. An analog switch connected to supply the analog video signal on the bus line to each of the signal lines based on each output of the flip-flop, wherein the video control circuit performs the horizontal and vertical blanking periods. A predetermined period in at least one of the periods is set as a precharge period, a voltage on the bus line is set to a substantially center voltage of a maximum and minimum voltage of the analog video signal, and the signal line driving circuit is set in the precharge period. Correspondingly, the analog switch is controlled to make the video bus wiring and the signal line conductive.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a liquid crystal display device according to the present invention will be specifically described with reference to the drawings.

The liquid crystal display device according to the present invention has a structure in which an array substrate and a counter substrate are sealed with a liquid crystal layer interposed therebetween. The array substrate includes, for example, a pixel array portion in which signal lines and scanning lines are arranged in rows on a glass substrate to form a display area, a signal line driving circuit for driving each signal line, and a scanning line driving circuit for driving each scanning line And the like are integrally provided.

(First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of a signal line drive circuit of a liquid crystal display device according to a first embodiment of the present invention. The signal line driving circuit of FIG.
This is a so-called block sequential drive in which a plurality of signal lines are simultaneously driven as a set, and an H line inversion drive in which the polarity of a voltage with respect to a reference potential is switched for each horizontal line is employed as a signal line drive method. Things.

The signal line driving circuit shown in FIG. 1 comprises a shift register 1 for outputting shift pulses for driving signal lines S1 to Sn arranged in a row in a liquid crystal display section;
, A plurality of OR gates 31 to 3n connected to respective output terminals of the shift register 1,
A plurality of buffers 41 to 4n connected to the output terminals of the OR gates 31 to 3n, and a plurality of analog switches 5 for switching whether to supply analog pixel voltages on the video bus lines L1 to Lm to the signal lines S1 to Sn. And

One block is constituted by a plurality of analog switches 5, and the analog switches 5 in each block are:
On / off control is performed at the same timing by outputs from the buffers 41 to 4n corresponding to each block. Each end of the analog switch 5 in each block is connected to a separate video bus line L1 to Lm, and the other end of the analog switch 5 is connected to a separate signal line S1 to Sn.

The shift register 1 includes a first register group 11 in which a number of registers SR1 corresponding to the number of the signal lines S1 to Sn are cascaded, and an output of the last register SR1 in the first register group 11. It has an OR gate 6 connected to the terminal, and a second register group 12 connected downstream of the OR gate 6 and cascaded with a predetermined number of registers SR2.

The shift control circuit 2 has a D flip-flop (clock toggle means) 7, AND gates (first logic operation means) 8, 9, and an inverter 10. The output signal of the last register of the second register group 12 in the shift register 1 is input to the clock terminal of the D flip-flop 7.

When the power is turned on, the D flip-flop 7 is temporarily reset, and the Q output terminal goes low. Thereafter, when the register output of the last stage of the second register group 12 changes from low level to high level,
The Q output terminal changes to high level. When the Q output terminal is at a low level, the output of the AND gate 9 is fixed at a low level, and the AND gate 8 outputs a start pulse XST. On the other hand, when the Q output terminal is at a high level,
The gate 9 outputs the start pulse XST, and the output of the AND gate 8 is fixed at a low level.

Each register SR1 in the first register group 11
Shifts the start pulse XST output from the AND gate 8 of the shift control circuit 2 sequentially in synchronization with a horizontal clock signal input from the outside and shift clocks XCK and / XCK which are inverted clock signals thereof. Below,
The pulse output from each register SR1 is called a shift pulse.

A shift pulse is output from the last register SR1 in the first register group 11, or
When the start pulse XST is output from the D gate 9, O
The output of the R gate 6 becomes high level, whereby the second register group 12 starts the shift operation.

Each register SR1 in the first register group 11
OR gates (second logic operation means) 31 to 3n connected to the output terminals of the shift control circuit 2 output the OR signal of the output signal of the corresponding register SR1 and the output signal of the AND gate 9 in the shift control circuit 2. .

The outputs of the OR gates 31 to 3n are supplied to the buffer 4
The signal is input to the control terminal of the corresponding analog switch 5 through 1 to 4n. A plurality of analog switches 5 in the block are simultaneously turned on / off by the output of one buffer. Each analog switch 5 is connected to a separate video bus line L1 to Lm, and a video control circuit 13 is connected to these video bus lines. The video control circuit 13 may be provided in the array substrate or on another substrate. In this example, the image control circuit 13 is provided on another substrate.

A D / A converter (not shown) is connected in the video control circuit 13. The D / A converter converts digital pixel data output from a computer or the like (not shown) into analog pixel voltages and supplies the analog pixel voltages to the video bus lines L1 to Lm in FIG.

FIG. 2 is a timing chart showing signal waveforms at various parts of the liquid crystal display device shown in FIG. 1. The shift clocks XCK, / XCK, start pulse XS
T, the output of each register SR1 in the first register group 11,
The output of the register SR2 at the last stage in the second register group 12, the Q output and the / Q output of the D flip-flop 7, the output of the AND gate 8, the output of the AND gate 9, and the control terminal of the analog switch 5 are input. The waveforms of the control signal, the signals on the video bus lines L1 to Lm, and the signal line voltage are shown.

Hereinafter, the operation of the liquid crystal display device of FIG. 1 will be described with reference to the timing chart of FIG. When the power is turned on, D
The flip-flop 7 is reset once and D
The Q output of the flip-flop 7 goes low and the output of the inverter 10 goes high. Thereafter, when the start pulse XST is input at time T1 in FIG. 2, the start pulse XST is input to the first-stage register SR1 in the first register group 11 via the AND gate 8. on the other hand,
At this point, the output of the AND gate 9 is at a low level.

Thereafter, each register in the first register group 11 sequentially outputs a shift pulse obtained by shifting the start pulse XST in synchronization with the shift clocks XCK and / XCK. The shift pulse output from the first register group 11 is input to the corresponding control terminal of the analog switch 5 via the OR gates 31 to 3n and the buffers 41 to 4n. When a shift pulse is input to the control terminal, the analog switch 5 is turned on, and the video bus lines L1 to L1 are turned on.
The analog pixel voltage on Lm is supplied to the corresponding signal line.

With such an operation, the corresponding analog switch 5 is turned on almost simultaneously with the output of the shift pulse from the first register group 11, and the signal line connected to the analog switch 5 is turned on. An analog pixel voltage on a video bus line is supplied.

FIG. 2 shows a voltage waveform of a signal line connected to the analog switch 5 which is turned off at time T2. As shown, the voltage immediately before the analog switch 5 is turned off is held on this signal line.

Next, at time T3 in FIG. 2, a shift pulse is output from the last register SR1 of the first register group 11, and the shift pulse is output from the second register group 12 via the OR gate 6. Is input to the first-stage register SR2. Thereafter, the second register group 12 starts the shift operation. At time T4, a shift pulse is output from the register SR2 at the last stage of the second register group 12, and this shift pulse is supplied to the clock terminal of the D flip-flop 7. Is input to As a result, the logic of the Q output and the / Q output of the D flip-flop 7 is inverted, the output of the AND circuit 8 is fixed at a low level, and the output of the AND circuit 9 is the start pulse XS
It goes high when T (time T5 in FIG. 2) is input.

When the output of the AND circuit 9 becomes high level, O
All the outputs of the R gates 31 to 3n also go high,
All the analog switches 5 are turned on. In synchronization with this timing, the D / A converter (not shown) sets all the video bus lines L1 to Lm to the intermediate potential of each amplitude. Here, the intermediate potential means a voltage near the middle of the voltage amplitude of each video bus line.
Thereby, all the video bus lines L1 to Lm and further all the signal lines S1 to Sn are precharged to the intermediate potential during the blanking period.

The output of the AND circuit 9 goes high during the blanking period only while the start signal XST is being input. After that, when the blanking period ends, at the time T6 in FIG.
When ST is input, the first register group 11 restarts the shift operation.

As described above, in the first embodiment, all the video bus lines L1 to Lm and all the signal lines are precharged to the intermediate potential during the blanking period. Of the video bus lines L1 to Lm and the signal lines, and the video bus lines L1 to Lm and the signal lines can be quickly set to desired voltages.

For example, when the intermediate potential is set to 5 V, the maximum voltages of the video bus lines L1 to Lm and the signal lines become 9.
Because it is 5V, after the blanking period ends
It is sufficient to boost the voltage by 4.5V, and the video bus lines L1 to L
There is no possibility that the voltage of m and the signal line may be boosted in time, so that the variation in contrast is suppressed and the display quality can be improved.

In the first embodiment, a start pulse XST is output during the blanking period, and all the video bus lines L1 to L1 are output using the start pulse XST.
Since the timing for setting Lm and the signal line to the intermediate potential is determined, the circuit configuration for timing setting can be simplified.

In the first embodiment, the signal lines are precharged via the video bus lines L1 to Lm.
There is no need to provide extra pre-charge bus wiring,
The size of the device can be reduced.

In the above embodiment, each of the video bus lines L1 to Lm transmits the positive and negative analog pixel voltages at a predetermined period with respect to the intermediate potential of 5V. The video bus line transmitting the analog pixel voltage on the positive polarity side of V and the analog pixel voltage on the negative polarity side of 0.5 to 4.5 V may be separated.

In such a case, during the blanking period,
For example, the video bus line on the positive polarity side is set to 7.5 V which is an intermediate voltage between 5.5 to 9.5 V of the amplitude of the analog pixel voltage on the video bus line, and the video bus line on the negative polarity side is the analog pixel voltage on the video bus line. Is precharged to 2.5V which is an intermediate voltage having an amplitude of 0.5 to 4.5V. Then, the voltage from the video bus line corresponding to the polarity to be written next is supplied to the signal line. For example, before the video bus line on the positive polarity side is selected, an intermediate voltage of 7.5 V is precharged to the signal line capacitance via the video bus line on the positive polarity side, thereby reducing the voltage change width of the signal line. As a result, the signal line can be quickly set to a desired voltage.

Also in this case, there is no need to newly provide a bus line for precharging, and an effect that the device can be downsized can be achieved.

The video bus lines L1 to Lm are set to 5.5
If the analog pixel voltage on the positive side of ~ 9.5V and the analog pixel voltage on the negative side of 0.5 ~ 4.5V are separated for transmission, during the blanking period, for example, the video bus line on the positive side The video bus line on the negative polarity side is precharged to 4.5 V, which is an approximate intermediate voltage of 0.5 to 9.5 V, and the signal line is connected to the signal line. It is also possible to configure so that a voltage from a video bus line corresponding to the polarity to be written next is supplied. For example, prior to the selection of the video bus line on the positive polarity side, the intermediate voltage of 5.5 V is precharged to the signal line capacitance via the video bus line on the positive polarity side, thereby reducing the voltage change width of the signal line. As a result, the signal line can be quickly set to a desired voltage.

(Second Embodiment) In a second embodiment, an analog switch is directly controlled by a shift pulse output from the last register SR2 in the second register group 12.

FIG. 3 is a block diagram showing a schematic configuration of a second embodiment of the signal line drive circuit of the liquid crystal display device according to the present invention. In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and different points will be mainly described below.

The signal line driving circuit of FIG. 3 has the same configuration as that of FIG. 1 except that the configurations of the shift register 1 and the shift control circuit 2 are different. The flip-flop (clock toggle means) 7 and AND gates (third logic operation means) 21 to 24 in FIG. 3 correspond to clock generation means, and the OR gates 31 to 3n correspond to fourth logic operation means.

The shift register 1 includes a first register group 1
1 in that it has a first register group 12 and a second register group 12, the output of the first register group 11 is not input to the second register group 12, and the OR gate 6 shown in FIG. do not have. Further, the first and second register groups 11, 12
Have separate shift clocks (XCK2, / XCK2), (X
CK3, / XCK3) are input.

The shift control circuit 2 shown in FIG. 3 includes a D flip-flop 7, AND gates 21 to 24, and an inverter 10
And The output signal of the OR gate 3n connected to the last-stage register SR1 in the first register group 11 is input to the clock terminal of the D flip-flop 7.

The Q output of the D flip-flop 7 is input to the AND gates 21 and 22 and the inverter 10. When the Q output is at a high level, the AND gates 21 and 22 output the clock XCK having the same logic as the external clocks XCK1 and / XCK1, respectively.
Outputs 2, / XCK2.

FIG. 4 is a timing chart showing signal waveforms at various parts of the signal line driving circuit of FIG. 3. Hereinafter, the operation of the signal line driving circuit of FIG. 3 will be described with reference to FIG.

When the power is turned on, the D flip-flop 7 is set once, and the Q output terminal goes high. Thereafter, at time T1 in FIG. 4, the start pulse XST is input to both the first and second register groups 11 and 12. At this point, the Q output of the D flip-flop 7 is at the high level, and the first register group 1
Each of the registers SR1 in 1 sequentially outputs a shift pulse in synchronization with the clocks XCK2 and / XCK2 output from the AND circuits 21 and 22.

The shift pulse output from the first register group 11 is input to the control terminal of the analog switch 5 via the OR gates 31 to 3n and the buffers 41 to 4n, and turns on the corresponding analog switch 5. Thus, the analog pixel voltages on the video bus lines L1 to Lm connected to one end of the analog switch 5 are supplied to the corresponding signal lines.

At time T2 in FIG. 4, a shift pulse is output from the last register SR1 in the first register group 11, and this shift pulse is supplied to the D gate via the OR gate 3n.
The signal is input to the clock terminal of the flip-flop 7. As a result, the Q output of the D flip-flop 7 is inverted, and AND
The output terminals of the gates 21 and 22 are both at the low level.

At this time, the output of the inverter 10 becomes high level, and the AND gates 23 and 24 output clocks XCK3 and / XCK3 having the same logic as the shift clocks XCK1 and / XCK1, respectively.

Thereafter, at time T3, a blanking period starts, and a start pulse XST is input at time T4 during the blanking period. As a result, the second register group 12 sequentially shifts the start pulse XST,
Shift pulses having a pulse width substantially equal to the start pulse XST are sequentially output.

At time T5 in FIG. 4, a shift pulse is output from the last-stage register SR2 in the second register group 12, and this shift pulse causes all OR gates 3
1 to 3n become high level, and all the analog switches 5 are turned on accordingly. At this time, D /
The A-converter sets all video bus lines to an intermediate potential.

As described above, in the second embodiment, as in the first embodiment, all the video bus lines L1 to Lm and the signal lines are set to the intermediate potential during the blanking period. Immediately after the termination, the voltages of the video bus lines L1 to Lm and the signal lines can be quickly set to a voltage near the black level or a voltage near the white level. As in the first embodiment, a start pulse XST is input during a blanking period, and the start pulse XS
Since the timing for setting the video bus lines L1 to Lm and the signal lines to the intermediate potential using T is determined, it can also be realized with a simple circuit configuration.

In FIGS. 1 and 3, the number of registers SR2 forming the second register group 12 is not particularly limited. It is sufficient to provide a number of registers corresponding to the input timing of the start pulse XST in the blanking period.

In the above-described embodiment, an example in which a plurality of signal lines are sequentially driven in blocks has been described. However, the number of signal lines forming a block is not particularly limited. Further, the present invention can be similarly applied to a case where signal lines are driven one by one.

In the above-described embodiment, an example in which the start pulse XST is input during the horizontal blanking period has been described. However, in the case of V-line inversion driving, the start pulse XST is input during the vertical blanking period. All the video bus lines L1 to Lm and the signal lines may be set to the intermediate potential in synchronization with the start pulse XST.
That is, the precharge period can be set in each horizontal blanking period, provided in each vertical blanking period, or provided in each of the horizontal and vertical blanking periods, depending on the driving method.

In each of the above-described embodiments, an example in which the present invention is applied to a liquid crystal display device has been described.
ctroluminescence) display device and PDP (Plasma Display
Panel) devices are equally applicable.

[0071]

According to the present invention, the voltage of the video bus line is set to an intermediate voltage of the maximum amplitude of the video signal after the driving of the signal lines for one horizontal line is completed. Inconveniences such as lowering of contrast and generation of a bright line due to insufficient writing of wiring are eliminated, and display quality can be improved.

Further, if the voltages of all the signal lines are set to an intermediate voltage of the maximum amplitude of the video signal via the video bus wiring, the display quality can be further improved. Further, according to the present invention, a start pulse is supplied to the signal line driving circuit during the horizontal blanking period, and the voltage of all the signal lines is set to a substantially intermediate voltage of the voltage amplitude on the signal line by using the start pulse. Since the timing to be set is determined, a timing setting circuit is not required, and the circuit configuration can be simplified.

Further, according to the present invention, problems such as a decrease in contrast due to insufficient writing and the occurrence of a bright line can be solved without significantly increasing the circuit configuration, and the display quality can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a signal line driving circuit of a liquid crystal display device according to the present invention.

FIG. 2 is a timing chart showing signal waveforms of various parts of the liquid crystal display device shown in FIG.

FIG. 3 is a block diagram showing a schematic configuration of a second embodiment of the signal line drive circuit of the liquid crystal display device according to the present invention.

FIG. 4 is a timing chart showing signal waveforms at various parts of the signal line driving circuit of FIG. 3;

FIG. 5 is a block diagram of a signal line driving circuit of a conventional driving circuit integrated type liquid crystal display device.

FIG. 6 is a timing chart of input / output signals of the signal line driving circuit in FIG. 5;

FIG. 7 is a timing chart of each part in a signal line driving circuit when performing H-line inversion driving.

FIG. 8 is a circuit diagram of a liquid crystal display device disclosed in the above publication.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register 2 Shift control circuit 31-3n OR gate 41-4n Buffer 5 Analog switch 6 OR gate 7 Flip-flop 8,9 AND gate 10 Inverter 11 First register group 12 Second register group 21-24 AND gate 31 To 3n OR gate L1 to Lm Video bus line S1 to Sn signal line

Claims (27)

[Claims] 1. A pixel electrode connected to each intersection of a plurality of signal lines and scanning lines arranged in rows and columns via a switching element, and an analog video signal from a video control circuit is supplied to each of the signal lines. A signal line driving circuit, and a scanning line driving circuit for supplying a scanning pulse to each of the scanning lines, an array substrate formed on an insulating substrate, and disposed opposite to each other via a light modulation layer on the array substrate. A signal line drive circuit, a shift register in which a plurality of flip-flops are cascaded, a bus line for transferring the analog video signal from the video control circuit, The analog video signal on the bus line is connected between each of the signal lines and the bus line based on each output of the flip-flop. And an analog switch for supplying a voltage on the bus line to a predetermined period in at least one of the horizontal and vertical blanking periods as a precharge period. A flat display device, wherein the center voltage is set to a substantially central voltage of a maximum and a minimum voltage of the analog video signal in a video bus wiring. 2. The flat display device according to claim 1, wherein the shift register turns on all of the analog switches during the precharge period. 3. The shift register according to claim 1, wherein a timing for turning on all the analog switches is set based on a start pulse input during at least one of a horizontal blanking period and a vertical blanking period. The flat panel display according to claim 2, wherein 4. A shift register, comprising: a first register having a plurality of flip-flops, and an on / off control of one or more corresponding analog switches by an output of each flip-flop; 4. A second register, comprising: a second register that generates a timing signal that defines a timing for turning on all of the analog switches by an output of a last-stage flip-flop of the first shift register. A flat display device as described in the above. 5. An n-number (where n is an integer of 2 or more) analog switch is provided corresponding to the output of each flip-flop constituting the first register. 5. The semiconductor device according to claim 4, wherein the bus lines are connected to n different bus lines.
4. The flat panel display according to claim 1. 6. Each flip-flop constituting the first register and the second register performs a shift operation based on a shift clock having the same frequency and the same phase, and each flip-flop constituting the second register. Is
The flat display device according to claim 4, wherein outputs of flip-flops at the last stage of the first register are sequentially shifted in synchronization with the shift clock. 7. A shift pulse output from a last-stage flip-flop of the first register and the start pulse input during at least one of the horizontal blanking period and the vertical blanking period. 7. The flat display device according to claim 6, further comprising input control means for inputting a signal to a first flip-flop of the second register. 8. A clock toggle means whose output logic is inverted when a shift pulse is output from a flip-flop at the last stage of said second register, and said start pulse is generated by said clock toggle means based on an output of said clock toggle means. A first logical operation means for switching whether or not to supply the first flip-flop of the first register; and a logic operation means provided for each flip-flop constituting the first register, based on an output of the corresponding flip-flop. And a plurality of second logical operation means for controlling on / off of the corresponding analog switch, wherein the first logical operation means outputs the output of the clock toggle means after the start of one horizontal line period. Until the logic is inverted, the start pulse can be supplied to the first-stage flip-flop of the first register; Each of the logical operation means is based on the output of the corresponding flip-flop of the first register until the shift pulse is output from the last flip-flop of the second register after the start of one horizontal line period. Controlling on / off of the corresponding analog switch,
From the last flip-flop of the second register, 1
5. The flat display device according to claim 4, wherein all the corresponding analog switches are turned on from the time when the second shift pulse is output until the time when the second shift pulse is output. 9. The first logic operation means, when the start pulse is input during at least one of the horizontal blanking period and the vertical blanking period, the first logical operation means outputs the start pulse to the first register. 9. The flat display device according to claim 8, wherein the signal is supplied to an input terminal of a first-stage flip-flop of the second register without being supplied to the second register. 10. The signal line drive circuit according to claim 1, wherein a first shift clock supplied to a clock terminal of each flip-flop of the first register and a clock terminal of each flip-flop of the second register. And clock generating means for generating a second shift clock. The clock generating means, after a reset period ends,
Until the last flip-flop of the first register outputs a shift pulse, the first shift clock is output without outputting the second shift clock, and the last flip-flop of the first register is output. The second shift clock is output without outputting the first shift clock until the flip-flop at the last stage of the second register outputs the shift pulse after the flip-flop outputs the shift pulse. Each flip-flop of the first register is connected to the first flip-flop.
The start pulse is sequentially shifted in synchronization with the shift clock of (i), and each flip-flop of the second register
The flat display device according to claim 4, wherein the start pulse is sequentially shifted in synchronization with the shift clock. 11. The clock generation means includes: clock toggle means for inverting output logic when a shift pulse is output from the last flip-flop of the first register; output from the clock toggle means and an external input The flat panel display according to claim 10, further comprising: third logic operation means for generating the first and second shift clocks based on the clock signal obtained. 12. An analog switch provided corresponding to each flip-flop of the first register and turning on the corresponding analog switch based on an output of the corresponding flip-flop.
A fourth logical operation unit that performs off-control, wherein the fourth logical operation unit performs one horizontal line period;
The analog switch corresponding to a case where a shift pulse is output from each flip-flop constituting the first register is turned on, and the at least one of the horizontal blanking period and the vertical blanking period is set to the second position. 12. The flat panel display according to claim 11, wherein all of the analog switches are turned on when a shift pulse is output from the last flip-flop of the second register. 13. The flat display device according to claim 1, wherein the video control circuit is provided separately from the array substrate and the counter substrate. 14. A pixel electrode connected via a switching element to each intersection of a plurality of signal lines and scanning lines arranged in rows and columns, and an analog video signal from a video control circuit is supplied to each of the signal lines. A signal line driving circuit, and a scanning line driving circuit for supplying a scanning pulse to each of the scanning lines, on an array substrate formed on an insulating substrate, wherein the signal line driving circuit includes a plurality of flip-flops connected in cascade. A shift register, a bus line for transferring the analog video signal from the video control circuit, and a bus line connected between each of the signal lines and the bus line based on each output of the flip-flop. And an analog switch for supplying the analog video signal to each of the signal lines. A predetermined period in at least one of the vertical blanking periods is set as a precharge period, and a voltage on the bus line is set to a substantially center voltage of a maximum and a minimum voltage of the analog video signal in a corresponding video bus line. Array substrate. 15. A pixel electrode connected through a switching element to each intersection of a plurality of signal lines and scanning lines arranged in rows and columns, and an analog video signal from a video control circuit is supplied to each of the signal lines. A signal line driving circuit, and a scanning line driving circuit for supplying a scanning pulse to each of the scanning lines, an array substrate formed on an insulating substrate, and disposed opposite to each other via a light modulation layer on the array substrate. A bus line for transferring the analog video signal from the video control circuit is connected to each of the signal lines via an analog switch, wherein the video control The circuit is configured such that a predetermined period within at least one of the horizontal and vertical blanking periods is a precharge period, and a voltage on the bus line is applied to a corresponding bus line. The driving method of the flat panel display and setting substantially at the center voltage of the maximum and minimum voltage of the analog video signal takes. 16. A pixel electrode connected through a switching element to each intersection of a plurality of signal lines and scanning lines arranged in rows and columns, and an analog video signal from a video control circuit is supplied to each of the signal lines. A signal line driving circuit, and a scanning line driving circuit for supplying a scanning pulse to each of the scanning lines, an array substrate formed on an insulating substrate, and disposed opposite to each other via a light modulation layer on the array substrate. A signal line drive circuit, a shift register in which a plurality of flip-flops are cascaded, a bus line for transferring the analog video signal from the video control circuit, The analog video signal on the bus line is connected between each of the signal lines and the bus line based on each output of the flip-flop. An analog switch for supplying a voltage to each of the lines, wherein the video control circuit sets a voltage on the bus line to a predetermined period within at least one of the horizontal and vertical blanking periods as a precharge period. The signal line drive circuit controls the analog switch corresponding to the precharge period to make the video bus line and the signal line conductive, while setting the voltage to be substantially the center voltage of the maximum and minimum voltages of the analog video signal. A flat display device characterized by the above-mentioned. 17. The flat display device according to claim 16, wherein the shift register turns on all the analog switches during the precharge period. 18. The shift register sets a timing for turning on all of the analog switches based on a start pulse input during at least one of a horizontal blanking period and a vertical blanking period. The flat panel display according to claim 17, wherein: 19. A shift register comprising: a first register having a plurality of flip-flops, and an on / off control of one or more corresponding analog switches by an output of each flip-flop; 19. A second register, comprising: a second register for generating a timing signal defining a timing for turning on all of the analog switches by an output of a last-stage flip-flop of the first shift register. A flat display device as described in the above. 20. An n-number (n is an integer of 2 or more) analog switch is provided for each output of each flip-flop constituting the first register. 2. The device according to claim 1, wherein said bus lines are connected to n different bus lines.
10. The flat panel display according to 9. 21. Each flip-flop forming the first register and the second register performs a shift operation based on a shift clock having the same frequency and the same phase, and each flip-flop forming the second register. Is
20. The flat-panel display device according to claim 19, wherein an output of a last-stage flip-flop of the first register is sequentially shifted in synchronization with the shift clock. 22. A shift pulse output from the last flip-flop of the first register and the start pulse input during at least one of the horizontal blanking period and the vertical blanking period. 22. The flat-panel display device according to claim 21, further comprising an input control unit for inputting a signal to a first flip-flop of the second register. 23. Clock toggle means for inverting output logic when a shift pulse is output from the last flip-flop of the second register, and the start pulse is supplied to the second register based on an output of the clock toggle means. A first logical operation means for switching whether or not to supply the first flip-flop of the first register; and a logic operation means provided for each flip-flop constituting the first register, based on an output of the corresponding flip-flop. And a plurality of second logical operation means for controlling on / off of the corresponding analog switch, wherein the first logical operation means outputs the output of the clock toggle means after the start of one horizontal line period. Until the logic is inverted, the start pulse can be supplied to the first-stage flip-flop of the first register; Each of the logical operation means is based on the output of the corresponding flip-flop of the first register until the shift pulse is output from the last flip-flop of the second register after the start of one horizontal line period. Controlling on / off of the corresponding analog switch,
From the last flip-flop of the second register, 1
20. The flat panel display according to claim 19, wherein all of the corresponding analog switches are turned on from the time when the second shift pulse is output until the time when the second shift pulse is output. 24. The first logical operation means, when the start pulse is input during at least one of the horizontal blanking period and the vertical blanking period, the first logical operation means outputs the start pulse to the first register. 9. The flat display device according to claim 8, wherein the signal is supplied to an input terminal of a first-stage flip-flop of the second register without being supplied to the second register. 25. The signal line driving circuit, wherein a first shift clock supplied to a clock terminal of each flip-flop of the first register and a clock terminal of each flip-flop of the second register. And clock generating means for generating a second shift clock. The clock generating means, after a reset period ends,
Until the last flip-flop of the first register outputs a shift pulse, the first shift clock is output without outputting the second shift clock, and the last flip-flop of the first register is output. The second shift clock is output without outputting the first shift clock until the flip-flop at the last stage of the second register outputs the shift pulse after the flip-flop outputs the shift pulse. , Each flip-flop of the first register includes the first flip-flop.
The start pulse is sequentially shifted in synchronization with the shift clock of the second register.
20. The flat display device according to claim 19, wherein the start pulse is sequentially shifted in synchronization with the shift clock. 26. A clock toggle means for inverting an output logic when a shift pulse is output from a last flip-flop of the first register, an output of the clock toggle means and an external input. 26. The flat display device according to claim 25, further comprising: third logic operation means for generating the first and second shift clocks based on the clock signal obtained. 27. A flip-flop provided in correspondence with each flip-flop of the first register, and turning on / off the corresponding analog switch based on an output of the corresponding flip-flop.
A fourth logical operation unit that performs off-control, wherein the fourth logical operation unit performs one horizontal line period;
The analog switch corresponding to a case where a shift pulse is output from each flip-flop constituting the first register is turned on, and the at least one of the horizontal blanking period and the vertical blanking period is set to the second position. 27. The flat panel display device according to claim 26, wherein all of the analog switches are turned on when a shift pulse is output from the last flip-flop of the second register.