JP2005300701A - Display apparatus and driving method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a size and cost of a display apparatus by improving a precharge method. <P>SOLUTION: An external video driver supplies a precharge signal of predetermined potential to a video line VIDEO in a display panel 33 during a precharge period preceding each horizontal scanning period. An external timing generator holds timing signals HST, HCK and DCK which are supplied to a horizontal driving circuit 17 in the display panel 33 during the precharge period. The horizontal driving circuit 17 operates according to a timing signal which is held and turns each sampling switch on during the precharge period and samples the precharge signal from the video line VIDEO to each signal line Y and performs precharging each signal line Y to predetermined potential in advance of sampling of an image signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an active matrix display device and a driving method thereof. More particularly, the present invention relates to a precharge technique for improving display screen uniformity.

When raster scanning is performed in an active matrix display device, a so-called 1H inversion driving method is performed in which a video signal written to each pixel is inverted every horizontal scanning period (1H). In the case of 1H inversion driving, when a charge / discharge current due to writing of a video signal to a signal line provided for each column of pixels arranged in a matrix is large, a so-called “vertical stripe” defect appears on the display screen. End up. In order to suppress the charge / discharge current due to the writing of the video signal as much as possible, a precharge driving method in which a precharge signal is applied to the signal line in advance prior to the writing of the video signal has been conventionally employed.
JP-A-7-295521 JP 2003-122317 A JP 2003-122320 A

  In general, an active matrix display device includes a flat display panel that forms a screen and an external peripheral drive circuit that drives the display panel. As described above, the current display panel inputs a precharge signal having the same polarity as the video signal before inputting the video signal in order to improve image quality uniformity. For this reason, a precharge signal external IC for generating a precharge signal separately from the video signal outside the display panel is required. Since the precharge signal external IC is composed of an analog buffer, it has a higher failure rate than other digital ICs, and is one of the causes of failure of the display panel drive board. In addition, a bus line for a precharge signal, a switch for sampling a precharge signal, and a control circuit for generating a pulse for controlling the switch are necessary even inside the display panel, which is an obstacle to further downsizing the panel size. Yes.

  In view of the above-described problems of the conventional technology, an object of the present invention is to improve the precharge method and reduce the size and cost of a display device. In order to achieve this purpose, the following measures were taken. That is, it comprises a display panel, a video driver that supplies video signals to the display panel, and a timing generator that also supplies a timing signal to the display panel. The display panel is arranged in the row direction and in the column direction. A pixel array unit composed of matrix-like pixels arranged at the intersections of the signal lines and the gate lines and the signal lines, and connected to the gate lines to sequentially select the pixels for each row in the vertical scanning period. A vertical drive circuit, a video line that takes in the video signal supplied from the video driver, a plurality of sampling switches connected between the video line and each signal line, and a timing signal supplied from the timing generator The video signal from the video line by sequentially turning on each sampling switch in the horizontal scanning period. In a display device including a horizontal drive circuit that sequentially samples each signal line and writes a video signal dot-sequentially to pixels in a selected row, the video driver includes a precharge preceding each horizontal scanning period. A precharge signal having a predetermined potential is supplied to the video line of the display panel during the period, and the timing generator adjusts a timing signal supplied to the horizontal drive circuit of the display panel during the precharge period, The driving circuit operates in accordance with the adjusted timing signal, turns on each sampling switch during the precharge period, samples the precharge signal from the video line to each signal line, and thereby samples the video signal. In advance, each signal line is precharged to a predetermined potential.

  In one aspect, the horizontal driving circuit simultaneously turns on the sampling switches during the precharge period to sample the precharge signals simultaneously onto the signal lines. In another aspect, the horizontal driving circuit alternately turns on at least one sampling switch every other time during the precharge period, and alternately samples the precharge signal on each signal line.

  The present invention also includes a display panel, a video driver for supplying a video signal thereto, and a timing generator for supplying a timing signal to the display panel. The display panel includes gate lines and columns arranged in a row direction. Signal lines arranged in the direction and a pixel array unit composed of matrix-like pixels arranged at the intersections of the gate lines and the signal lines, and connected to the gate lines for each pixel in the vertical scanning period. A vertical drive circuit for selecting sequentially, a video line for taking in a video signal supplied from the video driver, a plurality of sampling switches connected between the video line and each signal line, and a timing generator Operates in response to the timing signal, and turns on each sampling switch in the horizontal scanning period to display video from the video line. In a driving method of a display device including a horizontal driving circuit that sequentially samples a signal to each signal line and writes a video signal dot-sequentially to pixels in a selected row, the video driver is controlled, A precharge signal having a predetermined potential is supplied to the video line of the display panel during a precharge period preceding each horizontal scanning period, and the timing generator is controlled to be supplied to the horizontal drive circuit of the display panel during the precharge period. Adjusting the timing signal, operating the horizontal driving circuit of the display panel according to the adjusted timing signal, turning on each sampling switch during the precharge period, and supplying the precharge signal from the video line to each signal line Therefore, each signal line is precharged to a predetermined potential prior to video signal sampling. Characterized in that it put.

  According to the present invention, a precharge signal is supplied to the display panel using a video driver that supplies a video signal from the outside to the display panel. In other words, the video driver combines the precharge signal and the video signal in advance and supplies them to the display panel. As a result, the precharge signal external IC, which has been conventionally required, can be deleted. This is expected to reduce the cost of the panel drive board, reduce the board area, and reduce the failure rate. According to the present invention, the precharge signal is sampled using the horizontal drive circuit and the sampling switch for sampling the video signal to each pixel inside the display panel. For this reason, it is possible to delete a precharge signal bus line, a precharge signal selection switch, a control circuit for generating a pulse for controlling the switch, and the like, which are conventionally required. As a result, the panel size can be reduced, and when a large number of panel substrates are produced from a large wafer, an increase in the theoretical yield is expected. Note that the timing signal supplied from the external timing generator to the inside of the display panel is adjusted in order to perform the precharge operation by the horizontal drive circuit and the sampling switch inside the display panel.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, in order to clarify the background of the present invention, the general configuration of a general display device will be described with reference to FIG. As shown in the figure, the display device includes a display panel 33 constituting a screen, a video driver 19 that supplies video signals to the display panel 33, and a timing generator 18 that supplies various timing signals to the display panel 33. The timing signal includes primary clock signals HCK1 and HCK2, secondary clock signals DCK1 and DCK2, and further a horizontal start pulse HST.

  The display panel 33 includes a pixel array unit 15 and a vertical drive circuit 16, a horizontal drive circuit 17, a uniformity improvement circuit 20, and the like arranged around the pixel array unit 15. The pixel array unit 15 includes gate lines X arranged in the row direction, signal lines Y arranged in the column direction, and matrix-like pixels 11 arranged at portions where the gate lines X intersect with the signal lines Y. . The vertical drive circuit 16 is connected to the gate line X from the left and right, and sequentially selects each pixel 11 for each row in the vertical scanning period (V). The horizontal drive circuit 17 takes in a video signal from an external video driver 19 via a video line VIDEO. Although not shown, the horizontal drive circuit 17 includes a plurality of sampling switches and is connected between the video line VIDEO and each signal line Y. The horizontal driving circuit 17 operates in accordance with various timing signals supplied from the timing generator 18 and sequentially turns on each sampling switch in the horizontal scanning period (H) to convert the video signal from the video line VIDEO to each signal line Y. Sampling is performed, and video signals are written in the dot sequence to the pixels 11 in the selected row.

  The uniformity improvement circuit 20 is connected to the lower end of each signal line Y on the side opposite to the horizontal drive circuit 17. The uniformity improvement circuit 20 precharges each signal line Y prior to writing a video signal to each pixel 11. Specifically, using a blanking period preceding the horizontal scanning period (H), a precharge signal is applied to each signal line Y and charged to a predetermined potential in advance. The period during which this precharge operation is performed is called a precharge period in the specification and is generally included in the blanking period.

  FIG. 2 is a circuit diagram showing a specific configuration inside the display panel shown in FIG. As described above, the display panel 33 includes the central pixel array unit 15 and the vertical drive circuit 16, the horizontal drive circuit 17, and the uniformity improvement circuit 20 that surround the pixel array unit 15. In the pixel array unit 15, gate lines X1, X2 and signal lines Y1, Y2, Y3 are arranged in a lattice pattern, and pixels 11 are arranged at each intersection. In the present embodiment, each pixel 11 includes a liquid crystal element LC and a thin film transistor TFT that drives the liquid crystal element LC. The gate electrode of the thin film transistor TFT is connected to the corresponding gate line X, the source electrode is connected to the corresponding signal line Y, and the drain electrode is connected to one electrode (pixel electrode) of the corresponding liquid crystal element LC. The other electrode (counter electrode) of the liquid crystal element LC is fixed at a predetermined potential (counter potential).

  The vertical drive circuit 16 is connected to one end of each of the gate lines X1, X2, and selects the gate lines X1, X2,... Sequentially in one vertical scanning period (1V). For example, when the gate line X1 is selected, the TFTs to which the gates are connected are simultaneously turned on and the pixels 11 for one row are selected.

  On the other hand, sampling switches HSW1, HSW2, HSW3,... Are connected between the signal lines Y1, Y2, Y3,. These sampling switches HSW are sequentially turned on and off by the horizontal drive circuit 17. Specifically, the horizontal drive circuit 17 is configured by a shift register, operates in accordance with clock signals HCK and DCK supplied from an external timing generator, and sequentially transfers start pulses HST supplied from the outside. Thus, the sampling switches HSW1, HSW2, and HSW3 are sequentially turned on within one horizontal period (1H). As a result, the video signal is sampled from the video line VIDEO to each signal line Y1, Y2, Y3... And written to each liquid crystal element LC of the pixel 11 for one row in the selected state.

  A precharge bus line (precharge line) for taking in a precharge signal PSIG from the outside is disposed below the pixel array section 15 in addition to the video line VIDEO. Precharge switches (precharge switches) PSW1, PSW2, PSW3,... Are connected between the precharge line and the signal lines Y1, Y2, Y3,. These precharge switches PSW are ON / OFF controlled by the uniformity improving circuit 20. Specifically, the uniformity improvement circuit 20 operates according to the timing signal PCG supplied from the external timing generator during the precharge period, and turns on the precharge switches PSW all at once. Thus, the precharge signal PSIG supplied from the precharge line is sampled on each signal line Y. The precharge operation for the signal line Y is performed prior to the sampling of the video signal for each pixel 11. In other words, each signal line Y is charged to a predetermined potential in advance by a precharge operation, and the amount of charge / discharge is reduced when the video signal is actually sampled thereafter, so that the image quality uniformity can be improved.

  FIG. 3 is a circuit diagram showing a specific configuration of the horizontal drive circuit 17 shown in FIG. As shown in the figure, the horizontal drive circuit 17 includes shift registers S / R connected in multiple stages corresponding to the signal lines Y1, Y2, Y3, and Y4. Extraction switches SW1, SW2, SW3, SW4 are connected to the output stage of each shift register S / R. The outputs of the sampling switches SW1, SW2, SW3, SW4 are connected to corresponding sampling switches HSW1, HSW2, HSW3, HSW4 via corresponding delay circuits DLY1, DLY2, DLY3, DLY4. In the present embodiment, the sampling switch SW and the sampling switch HSW are composed of transmission gate elements composed of a pair of P-channel transistors and N-channel transistors. The delay circuit DLY is composed of seven inverters.

  The shift registers S / R connected in multiple stages operate according to primary clock signals HCK1 and HCK2 that are opposite in phase to each other supplied from the timing generator, and sequentially transfer horizontal start pulses HST supplied from the timing generator, The corresponding extraction switches SW1, SW2, SW3, SW4 are sequentially turned on. The odd-numbered sampling switches SW1, SW3,... Are supplied with the secondary clock signal DCK1 from the timing generator, and the even-numbered sampling switches SW2, SW4,. A signal DCK2 is supplied. When the extraction switch SW1 is turned on by the shift register, one pulse is extracted from the DCK1, and after phase adjustment and amplification are performed with the corresponding DLY1, the HSW1 is turned on. As a result, the video signal is sampled from the video line VIDEO to the signal line Y1. Subsequently, the extraction switch SW2 is turned on, one pulse of DCK2 is extracted, phase adjustment and amplification are performed by the delay circuit DLY2, and then applied to the sampling switch HSW2 to turn it on. As a result, the video signal is sampled from the video line VIDEO to the corresponding signal line Y2.

  FIG. 4 is a timing chart for explaining the operation of the general display device shown in FIGS. First, precharge for each signal line is performed within a period (horizontal blanking period) from the end of video signal writing to the previous pixel row to the start of video signal writing to the next pixel row. The period during which precharge is performed is represented as a precharge period in the timing chart of FIG. In this precharge period, no selection pulse is applied to the sampling switches HSW1, HSW2,. On the other hand, the pulse PCG for controlling the precharge signal selection switches PSW1, PSW2,... Is set to the high level, and the precharge signal selection switches PSW1, PSW2,. At this time, the precharge signal PSIG input from the precharge signal bus line is precharged to the signal lines Y1, Y2,. As a result, the signal lines Y1, Y2,... Are charged to a predetermined potential. For example, if the level of the precharge signal PSIG is set to the counter potential, each signal line Y1, Y2,... Is charged from the negative potential written in the previous frame or field to the counter potential. Thereafter, immediately before the start of writing the video signal, the PCG is switched to the low level, and the precharge signal selection switch PSW is turned off in all stages.

  Subsequently, the dot-sequential writing of the video signal starts, and first, a start pulse HST is input from the timing generator. The shift register operates in accordance with HCK1 and HCK2, and sequentially transfers HST every half cycle and outputs it from each stage. DCK1 is extracted by the start pulse HST output from the first stage of the shift register, and thereby HSW1 is turned on. Subsequently, DCK2 is extracted by the start pulse HST output from the second stage of the shift register, and HSW2 is turned on accordingly. As is apparent from the timing chart of the figure, the pulses extracted from the DCK are narrower than the HST pulses and do not overlap each other. Thus, each sampling switch HSW1, HSW2,... Can sample the correct video signal level from the video line without interfering with each other. When HSW1 is turned on, a positive video signal is sampled on the signal line Y1. At this time, since the signal line Y1 is precharged to the counter potential in advance, the charge amount of the positive video signal can be small. If precharge is not performed, the signal line Y1 must be charged at once from the negative video signal potential written in the previous frame or field to the positive video signal potential, resulting in image quality disturbance. . Similarly, when HSW2 is turned on, the video signal is sampled on the corresponding signal line Y2.

  As is clear from the above description, in a general display device, a circuit dedicated to precharging is necessary to perform precharging. On the other hand, FIG. 5 shows the first embodiment of the display device according to the present invention, and simplifies the circuit around the precharge. FIG. 5A is a block diagram showing a display panel which constitutes a main part of the display device according to the present invention. For easy understanding, portions corresponding to the display panel of the reference example shown in FIG. 2 are given corresponding reference numbers. As shown in the figure, the display panel 33 is composed of a pixel array unit 15 and a vertical drive circuit 16 and a horizontal drive circuit 17 arranged around the pixel array unit 15, and a uniformity improvement circuit is excluded. The pixel array unit 15 is arranged at gate lines X1, X2 arranged in the row direction, signal lines Y1, Y2, Y3,... Arranged in the column direction, and portions where each gate line X and each signal line Y intersect. The matrix pixel 11 is formed. The vertical drive circuit 16 is connected to the gate lines X1 and X2, and sequentially selects the pixels 11 for each row in the vertical scanning period. The video line VIDEO takes in a video signal supplied from an external video driver. The sampling switches HSW1, HSW2, and HSW3 are connected between the video line VIDEO and the signal lines Y1, Y2, and Y3. The horizontal drive circuit 17 operates in response to timing signals HST, HCK, and DCK supplied from an external timing generator, sequentially turns on the sampling switches HSW1, HSW2, and HSW3 during the horizontal scanning period, and outputs video from the video line VIDEO. The signal is sampled sequentially on each signal line Y1, Y2, Y3, and the video signal is written dot-sequentially to the pixels 11 in the selected row.

  As a feature of the present invention, the external video driver outputs a precharge signal of a predetermined potential (for example, a counter potential of a liquid crystal element included in a pixel) in the precharge period preceding the horizontal scanning period (H). Supply to line VIDEO. Similarly, the external timing generator adjusts timing signals HST, HCK, and DCK supplied to the horizontal drive circuit 17 of the display panel 33 during the precharge period. For example, all timing signals HST, HCK, and DCK are held at a high level during the precharge period. The horizontal drive circuit 17 in the display panel 33 operates in response to the timing signals HST, HCK, and DCK thus held at the high level, and turns on the sampling switches HSW1, HSW2, and HSW3 during the precharge period to turn on the video line. A precharge signal is sampled from the VIDEO to the signal lines Y1, Y2, and Y3, so that the signal lines Y1, Y2, and Y3 are precharged to a predetermined potential before sampling the video signal.

  (B) is a timing chart for explaining the operation of the display panel shown in (A). First, various timing signals (HST, HCK1, HCK2, DCK1, and DCK2), which are horizontal drive digital signals, are fixed to a constant potential (high level) during the precharge period. As a result, the video signal sampling switches HSW1, HSW2,... Are all turned on, and the precharge signals input from the video lines VIDEO are precharged to the signal lines Y1, Y2,. After that, the timing signal is returned to the normal waveform immediately before the start of writing the video signal, and the sampling switches HSW1, HSW2,. By using this precharge driving system, the precharge signal external IC and the uniformity improvement circuit inside the panel can be eliminated.

  FIG. 6 shows a second embodiment of the display device according to the present invention, and is a circuit diagram of a display panel as a main part thereof. For easy understanding, portions corresponding to the circuit diagram of the display panel according to the reference example shown in FIG. 3 are denoted by corresponding reference numerals. In the present display panel, a vertical drive circuit 16 and a horizontal drive circuit 17 are arranged around the pixel array section 15, and a uniformity improving circuit is omitted. The horizontal drive circuit 17 includes a shift register S / R, sampling switches SW1, SW2, SW3, SW4... And sampling switches HSW1, HSW2, HSW3, HSW4. In the present embodiment, HCK1, HCK2, and HST are held at a high level during the precharge period, while DCK1 and DCK2 use the same pulse waveform as in the horizontal scanning period. As a result, the horizontal drive circuit 17 alternately turns on at least one sampling switch HSW1, HSW2, HSW3, HSW4 during the precharge period, and turns the precharge signal to each signal line Y1, Y2, Y3, Y4. Every other sample can be sampled alternately.

  FIG. 7 is a timing chart for explaining the operation of the display panel according to the second embodiment shown in FIG. As described above, during the precharge period, HST, HCK1, and HCK2 are held at a high level, while DCK1 and DCK2 are input with normal waveforms. If it does in this way, DCK1 and DCK2 of mutually opposite phase will be extracted as it is with the extraction switch, and will be applied to HSW1 and HSW2. For this reason, during the precharge period, the video signal sampling switch can be turned on alternately at odd stages and even stages, not at all stages. As a result, the increase in current consumption can be halved compared to the first embodiment. In the first embodiment shown in FIG. 5, since the sampling switches are turned on all at once during the precharge period, the current consumption of the horizontal drive circuit may increase rapidly.

It is a block diagram which shows the whole structure of a general display apparatus. FIG. 2 is a circuit diagram illustrating a configuration example of the display panel illustrated in FIG. 1. FIG. 3 is a circuit diagram showing a specific circuit configuration of the horizontal drive circuit shown in FIG. 2. 3 is a timing chart for explaining the operation of the display panel shown in FIG. 2. 1 is a circuit diagram and a timing chart showing a first embodiment of a display device according to the present invention. It is a circuit diagram which shows 2nd Embodiment of the display apparatus which concerns on this invention. It is a timing chart with which it uses for operation | movement description of 2nd Embodiment shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Pixel, 15 ... Pixel array part, 16 ... Vertical drive circuit, 17 ... Horizontal drive circuit, 18 ... Timing generator, 19 ... Video driver

Claims (4)

It consists of a display panel, a video driver that supplies video signals to the display panel, and a timing generator that also supplies timing signals to the display panel.
The display panel includes a gate array arranged in a row direction, a signal line arranged in a column direction, and a pixel array unit composed of matrix-like pixels arranged in a portion where each gate line and each signal line intersect each other, Connected between the video line and each signal line, a vertical drive circuit that connects to the gate line and sequentially selects each pixel for each row in the vertical scanning period, a video line that receives the video signal supplied from the video driver A plurality of sampling switches that operate in response to timing signals supplied from the timing generator, sequentially turn on each sampling switch in a horizontal scanning period, and sequentially sample video signals from the video lines to the signal lines, In a display device comprising a horizontal drive circuit for writing video signals dot-sequentially to pixels in a selected row,
The video driver supplies a precharge signal having a predetermined potential to a video line of the display panel in a precharge period preceding each horizontal scanning period,
The timing generator adjusts a timing signal supplied to the horizontal driving circuit of the display panel in the precharge period;
The horizontal driving circuit of the display panel operates according to the adjusted timing signal, and turns on each sampling switch during the precharge period to sample a precharge signal from the video line to each signal line, thereby A display device in which each signal line is precharged to a predetermined potential prior to sampling of a video signal.   2. The display device according to claim 1, wherein the horizontal driving circuit simultaneously turns on the sampling switches during the precharge period to sample the precharge signals onto the signal lines at the same time.   2. The horizontal driving circuit according to claim 1, wherein at least one sampling switch is alternately turned on in the precharge period, and the precharge signal is alternately sampled on each signal line. Display device. A display panel, a video driver for supplying a video signal to the display panel, and a timing generator for supplying a timing signal to the display panel. The display panel is disposed in a row direction and in a column direction. A pixel array unit composed of matrix-like pixels arranged at the intersection of the signal line and each gate line and each signal line, and vertical drive connected to each gate line and sequentially selecting each pixel for each row in the vertical scanning period A circuit, a video line that takes in a video signal supplied from the video driver, a plurality of sampling switches connected between the video line and each signal line, and a timing signal supplied from the timing generator Operates and sequentially turns on each sampling switch in the horizontal scanning period and outputs video signals from the video line. Sequentially sampled in, dot-sequentially to the pixels of the selected row I than in the driving method of a display device and a horizontal driving circuit for writing the video signal,
Controlling the video driver to supply a precharge signal of a predetermined potential to the video line of the display panel in a precharge period preceding each horizontal scanning period;
Controlling the timing generator to adjust the timing signal supplied to the horizontal drive circuit of the display panel during the precharge period;
The horizontal driving circuit of the display panel is operated according to the adjusted timing signal, and each sampling switch is turned on during the precharge period to sample a precharge signal from the video line to each signal line,
Accordingly, a driving method of a display device, wherein each signal line is precharged to a predetermined potential prior to sampling of a video signal.

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