JP5137873B2 - Display device and driving device - Google Patents

Description

  The present invention relates to a display device such as a liquid crystal display device, and also relates to a driving device used in the display device.

  In recent years, liquid crystal display devices are used in a wide range of fields from home TVs to industrial displays.

  The configuration of the liquid crystal display device is roughly divided into a liquid crystal panel and a drive device that drives the liquid crystal panel. The conventional driving device includes a plurality of image signal line driving circuits, a plurality of scanning line driving circuits, and a timing controller as a control circuit for driving these driving circuits. In such a conventional configuration, the timing controller is provided outside the image signal line driving circuit and the scanning line driving circuit.

  Each image signal line driving circuit is an integrated circuit for driving the image signal lines of the liquid crystal panel, and drives all the image signal lines of the liquid crystal panel using a plurality of the integrated circuits. Similarly, each scanning line driving circuit is an integrated circuit for driving the scanning lines of the liquid crystal panel, and drives all the scanning lines of the liquid crystal panel using a plurality of the integrated circuits.

  The timing controller receives image data, a control reference signal serving as a reference when controlling the image signal line driving circuit and the scanning line driving circuit, and a dot clock (DCLK) serving as a reference when performing processing. The control reference signal includes a horizontal synchronization signal (HD) used as a reference signal for synchronizing the liquid crystal panel in the horizontal direction, and a vertical synchronization signal used as a reference signal for synchronizing the liquid crystal panel in the vertical direction. (VD), a data enable signal (DENA) indicating a period during which the image data is valid, and the like are included.

  The timing controller generates a driving signal for driving the image signal line driving circuit and the scanning line driving circuit by using the various signals inputted.

  The drive signal for the image signal line drive circuit includes image data (several bits) composed of red (R), green (G), and blue (B) digital signals generated based on the image data input to the timing controller. Having a width bus configuration).

  Further, the drive signal for the image signal line drive circuit includes a clock (CLKH) serving as a reference when performing various processes in the image signal line drive circuit, a start pulse (STH) indicating the start of image data in the horizontal direction, Control signals such as a polarity inversion signal (POL) for inverting the polarity of the liquid crystal drive and a latch pulse (LP) for transmitting the image data to the image signal line of the liquid crystal panel on the output side of the image signal line drive circuit are included. It is.

  The driving signal for the scanning line driving circuit includes control signals such as a clock (CLKV) serving as a reference when performing various processes in the scanning line driving circuit, a start pulse (STV) indicating the start of image data in the vertical direction, and the like. included.

  The control signals for the image signal line driving circuit and the scanning line driving circuit are dot-based on the horizontal synchronization signal (HD), vertical synchronization signal (VD), and data enable signal (DENA) input to the timing controller. It is generated using a clock (DCLK).

  The image signal line driving circuit applies a predetermined voltage (gradation voltage) corresponding to the image data of each pixel to each pixel of the scanning line selected by the scanning line driving circuit. The scanning line driving circuit sequentially selects the scanning lines, whereby the entire image is displayed.

  In contrast to the above-described conventional configuration, a composite drive circuit in which a timing controller is mounted (incorporated) in an image signal line drive circuit has been developed. According to such a composite drive circuit, the circuit board for the timing controller is not necessary, so that the member cost can be reduced. As a result, the price of the liquid crystal display device can be reduced.

  A plurality of image signal line driving circuits with a built-in timing controller are provided in the liquid crystal display device. However, one timing controller is sufficient. For this reason, one of the plurality of image signal line driving circuits is used in the master mode, and the remaining image signal line driving circuits are used in the slave mode. More specifically, the master mode image signal line drive circuit operates based on its own timing controller, and the slave mode image signal line drive circuit receives a control signal from the timing controller of the master mode image signal line drive circuit. Operate. In this case, power consumption can be reduced by stopping the timing controller of the image signal line driver circuit in the slave mode.

JP 2003-216127 A Japanese Patent Laid-Open No. 10-62746

  Generally, an image signal line driving circuit has a data latch circuit for latching image data.

  In a configuration in which a plurality of image signal line drive circuits are provided, image data of image signal lines not assigned to the image signal line drive circuit is also input to each image signal line drive circuit. Even during such unnecessary image data input period, the transistors constituting the data latch circuit repeat the switching operation and consume power.

  An object of the present invention is to provide a display device and a driving device that can reduce power consumption during an input period of the above-described unnecessary image data.

The display device according to the present invention includes, as one aspect thereof, a display panel including a plurality of image signal lines, and a plurality of image signal lines each driving a predetermined number of image signal lines allocated in advance among the plurality of image signal lines. An image signal line driving circuit and an image data supply line for supplying image data to the plurality of image signal line driving circuits, each of the plurality of image signal line driving circuits controlling the plurality of image signal line driving circuits A timing controller having a control signal generating function for generating a control signal for performing the control signal, and one of the plurality of image signal line driving circuits is used in a master mode in which the control signal generating function is operated. In addition, the rest of the plurality of image signal line drive circuits are used in a slave mode in which the control signal generation function is not operated, and the plurality of image signal line drive circuits are used. Each of the image data extraction circuit for extracting a part of the image data corresponding to the predetermined number of image signal lines allocated in advance from the image data, and the image data extracted by the image data extraction circuit. A data latch circuit for latching, wherein the image data extraction circuit supplies a signal of a constant potential to the data latch circuit in a period other than the image data extraction period, and the image data extraction circuit A start pulse indicating the start timing in the horizontal direction is received, a predetermined time determined according to the number of the predetermined number of image signal lines from the reception of the start pulse is counted, and the first potential is indicated while counting is being performed. A counter that outputs an image data extraction control signal indicating the second potential during the pause, the image data and the previous When the image data extraction control signal is the first potential, the received image data is supplied to the data latch circuit, and the image data extraction control signal is the second potential. Comprises a logic circuit for supplying the signal of the constant potential to the data latch circuit .

According to the above aspect of the display device of the present invention, a signal having a constant potential is input to the data latch circuit in a period other than the image data extraction period. For this reason, it is possible to stop the switching operation of the transistors of the data latch circuit in a period other than the image data extraction period. Therefore, power saving of the image signal line driving circuit can be achieved, and as a result, power saving of the display device can be achieved. In addition, the image data extraction circuit can be realized with a simple configuration.

1 is a block diagram outlining a liquid crystal display device according to Embodiment 1 of the present invention. 1 is a plan view outlining a liquid crystal panel of a liquid crystal display device according to Embodiment 1. FIG. FIG. 3 is a circuit diagram outlining the pixels of the liquid crystal panel in the first embodiment. 1 is a block diagram outlining an image signal line driving circuit according to a first embodiment of the present invention (master mode). 1 is a block diagram outlining an image signal line driving circuit according to a first embodiment of the present invention (slave mode). 1 is a block diagram outlining an image signal line driving circuit according to a first embodiment of the present invention. 3 is a timing chart outlining the operation of the image signal line driving circuit according to the first embodiment of the present invention. 3 is a timing chart outlining the operation of the liquid crystal display device according to the first embodiment of the present invention. It is a block diagram which outlines the liquid crystal display device which concerns on Embodiment 2 of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the embodiment, as a display device according to the present invention, a liquid crystal display device capable of color display (which may be any of a transmissive type, a reflective type, and a transflective type) is illustrated. However, the display device according to the present invention is not limited to this. For example, a liquid crystal display device for monochrome display (not limited to black and white), a display device other than the liquid crystal display device (for example, a display device using an organic EL (Electro-Luminescent) or an inorganic EL), the configuration described below, and the like Is true. The driving device according to the present invention is applicable not only to a liquid crystal panel but also to various display panels.

Embodiment 1 FIG.
FIG. 1 shows a block diagram outlining a liquid crystal display device 1 according to Embodiment 1 of the present invention. In the example of FIG. 1, the liquid crystal display device 1 includes a liquid crystal panel 100 and a driving device 200 that drives the liquid crystal panel 100.

  FIG. 2 shows a schematic plan view of the liquid crystal panel 100. As illustrated in FIG. 2, the liquid crystal panel 100 is roughly divided into a pixel arrangement region 101 and a peripheral region 102 surrounding the region 101. The peripheral area is also referred to as a frame area. The shapes, dimensions, and the like of the liquid crystal panel 100, the pixel arrangement region 101, and the peripheral region 102 are not limited to the illustrated example. The liquid crystal panel 100 includes a plurality of pixels PX, a plurality of image signal lines 130, and a plurality of scanning lines 140. As illustrated in FIG. 2, each pixel PX is connected to any one of the plurality of image signal lines 130 and any one of the plurality of scanning lines 140.

  The pixels PX form a display screen on which images (including characters and the like) are displayed by being dispersedly arranged in a planar shape within the pixel arrangement region 101. In the example of FIG. 2, the pixels PX are aligned in both the row direction (left-right direction in the drawing) and the column direction (up-down direction in the drawing) in the pixel arrangement region 101. That is, a plurality of pixels PX are arranged in a matrix. It is also possible to arrange a plurality of pixels PX in a so-called delta shape.

  The image signal line 130 is a wiring for applying a voltage (gradation voltage) having a voltage value corresponding to the image data (more specifically, gradation data) of the pixel PX to the pixel PX. The image signal line may be referred to as a data line or the like. In the example of FIG. 2, each image signal line 130 extends in the column direction, and a plurality of such image signal lines 130 are arranged in the row direction. Each image signal line 130 extends over the pixel arrangement region 101 and the peripheral region 102. FIG. 2 illustrates a case where all the image signal lines 130 extend to one side (lower side in the drawing) of the peripheral region 102.

  The scanning line 140 is a wiring for selecting the pixel PX to which the gradation voltage is applied. The selection of the pixel PX is performed by sequentially selecting the plurality of scanning lines 140, in other words, scanning. Note that the scanning line may be referred to as a pixel selection line, a gate line, an address line, or the like. In the example of FIG. 2, each scanning line 140 extends in the row direction, and a plurality of scanning lines 140 are arranged in the column direction. Each scanning line 140 extends over the pixel arrangement region 101 and the peripheral region 102. FIG. 2 illustrates a case where all the scanning lines 140 extend to one side (the left side in the drawing) of the peripheral region 102.

  As described above, each pixel PX is connected to any one of the plurality of image signal lines 130 and any one of the plurality of scanning lines 140. For this reason, each image signal line 130 is connected to a plurality of pixels PX (some pixels PX among all the pixels PX) connected to different scanning lines 140. Each scanning line 140 is connected to a plurality of pixels PX (a part of all pixels PX) connected to different image signal lines 130. In this case, each pixel PX can be specified by a combination of the image signal line 130 and the scanning line 140.

  FIG. 3 shows a circuit diagram outlining the pixel PX. A pixel PX illustrated in FIG. 3 includes a thin film transistor (TFT) 111, a basic cell 112, and a storage capacitor 113.

  The gate of the TFT 111 is connected to the scanning line 140, the source of the TFT 111 is connected to the image signal line 130, and the drain of the TFT 111 is connected to the basic cell 112. Note that in some cases, the source is referred to as a drain and the drain is referred to as a source because of the structure of the TFT. Instead of the TFT 111, other switching elements can be used.

  The basic cell 112 is a structure that is a basic unit of the pixel PX, and is provided for each pixel PX, a pixel electrode connected to the drain of the TFT 111, a common electrode for supplying a common potential to each pixel PX, And a liquid crystal layer. Note that the pixel electrode and the common electrode are provided on separate substrates facing each other through a liquid crystal layer in a TN (Twisted Nematic) mode, for example. In contrast, for example, in the IPS (In Plane Switching) mode, the FFS (Fringe Field Switching) mode, and the like, the liquid crystal panel 100 is provided on the same substrate.

  One electrode of the storage capacitor 113 is connected to the drain of the TFT 111. The other electrode of the storage capacitor 113 is connected to a predetermined potential, for example, a common potential applied to the common electrode. Note that a pixel configuration without the storage capacitor 113 may be employed. The holding capacity is also referred to as an auxiliary capacity.

  In the case of the pixel PX having such a structure, when the gate of the TFT 111 is turned on by applying a voltage to the scanning line 140, the voltage (corresponding to image data) of the image signal line 130 at that time is supplied to the pixel electrode. The electric field between the pixel electrode and the common electrode generated at this time changes the alignment state of the liquid crystal molecules in the liquid crystal layer, thereby changing the display luminance of the pixel PX. The potential of the pixel electrode is held by the holding capacitor 113.

  The display color of each pixel PX is defined by providing a color filter in the basic cell 112, for example. At this time, for example, a unit for color display is constituted by an aggregate (that is, a pixel group) of pixels PX for display colors of adjacent red (R), green (G), and blue (B).

  Returning to FIG. 1, the driving device 200 illustrated in FIG. 1 includes a plurality of (herein, four are exemplified) image signal line driving circuits 301 to 304 and a plurality (here, two are exemplified). Scanning line drive circuits 401 and 402 and various wirings 501 to 513. Although not shown, the drive device 200 includes a power supply circuit that supplies various voltages used in the drive circuits 301 to 304, 401, and 402.

  Each of the image signal line driving circuits 301 to 304 is a circuit for driving the image signal line 130, that is, for applying a gradation voltage to the image signal line 130. Here, each of the image signal line drive circuits 301 to 304 is configured by a so-called integrated circuit (IC).

  Each of the image signal line drive circuits 301 to 304 has a plurality of output ends for outputting gradation voltages. A plurality of image signal lines 130 (part of all image signal lines 130) are assigned in advance to each of the image signal line drive circuits 301 to 304. The plurality of output ends of the image signal line drive circuits 301 to 304 are connected to the plurality of image signal lines 130 assigned to the drive circuits 301 to 304, respectively. Accordingly, a predetermined number of image signal lines 130 assigned in advance are driven by the image signal line driving circuits 301 to 304.

  Note that the output end of each of the image signal line drive circuits 301 to 304 is directly connected to the portion of the image signal line 130 drawn to the peripheral region 102 of the liquid crystal panel 100 on the glass or is flexible. It is connected via a member such as a tape (TCP: Tape Carrier Package / COF: Chip on Film).

  Here, a case where the same number of image signal lines 130 is assigned to each of the image signal line drive circuits 301 to 304 and the assigned image signal lines 130 are continuously arranged is illustrated. More specifically, when the total number of image signal lines 130 is (4 × M) where M is a natural number, the image signals from the first to the M-th counted from the left in the plan view of FIG. A line 130 is assigned to the image signal line driving circuit 301. Similarly, the image signal lines 130 from the (M + 1) th to the (2 × M) th are assigned to the image signal line driving circuit 302, and the (2 × M + 1) th to (3 × M) th are from the (2 × M + 1) th to the (3 × M) th. The image signal lines 130 are assigned to the image signal line drive circuit 303, and the image signal lines 130 from the (3 × M + 1) th to (4 × M) th are assigned to the image signal line drive circuit 304.

  The scanning line driving circuits 401 and 402 are both circuits for driving the scanning line 140, that is, for applying a scanning voltage (also referred to as a scanning line selection voltage) to the scanning line 140. Here, each of the scanning line driving circuits 401 and 402 is configured by a so-called integrated circuit (IC).

  Each of the scanning line driving circuits 401 and 402 has a plurality of output terminals for outputting a scanning voltage. The connection form of the scanning line drive circuits 401 and 402 and the scanning line 140 is the same as the connection form of the image signal line drive circuits 301 to 304 and the image signal line 130 described above. As a result, the scanning lines driving circuits 401 and 402 drive a predetermined number of scanning lines 140 assigned in advance to the driving circuits 401 and 402.

  4 and 5 are block diagrams outlining the image signal line driving circuits 301 to 304. FIG. 4 and 5 illustrate the same configuration, and FIG. 4 illustrates a case where the image signal line driving circuits 301 to 304 are used as a master mode image signal line driving circuit 300MST, which will be described later. FIG. 5 illustrates a case where the slave mode image signal line driver circuit 300SLV is used.

  Each of the image signal line driving circuits 301 to 304 includes a timing controller 310, in other words, a built-in timing controller 310. The timing controller 310 basically has the same function as an existing timing controller (referred to as an external timing controller) provided outside the image signal line driving circuit in the conventional driving device. Have.

  The timing controller 310 receives a signal related to a display image, and generates a signal for driving the drive circuits 301 to 304, 401, and 402 by applying the input signal to a predetermined process defined in advance. A control circuit configured to output a drive signal.

  The signal related to the display image input to the timing controller 310 includes, for example, image data RGB data to be displayed and a control reference signal S0 related to the display image. The control reference signal S0 related to the display image is used as, for example, a horizontal synchronization signal HD used as a reference signal for synchronizing the liquid crystal panel 100 in the horizontal direction and a reference signal for synchronizing the liquid crystal panel 100 in the vertical direction. Vertical synchronization signal VD, data enable signal DENA indicating a period during which image data RGBdata is valid, and the like are included.

  Note that the display image signals such as the image data RGBdata, the horizontal synchronization signal HD, the vertical synchronization signal VD, and the data enable signal DENA are display images of a TV tuner, a video, a personal computer, etc. provided outside the driving device 200, for example. It is supplied from a signal supply device (not shown).

  The timing controller 310 receives a dot clock DCLK that is used as a reference (for example, a reference for the timing of processing operations and pulse generation) when executing the predetermined processing. The dot clock DCLK is supplied from a clock generation circuit (not shown) provided outside or inside the driving device 200.

  The drive signal output from the timing controller 310 includes a signal for driving the image signal line drive circuits 301 to 304 and a signal for driving the scanning line drive circuits 401 and 402.

  As the drive signals for the image signal line drive circuits 301 to 304, for example, image data RGBdata (for the sake of simplicity, the same reference numerals as those of the image data of the input signal) and the image signal line drive circuit 301 are used. Control signal S1 for .about.304.

  The image data RGBdata output from the image signal line driving circuits 301 to 304 is obtained by, for example, performing various data processes that are defined in advance as part of the predetermined process on the input image data RGBdata. It is. As the image data processing defined in advance, for example, a process of converting input image data RGB data into data in a format suitable for driving the image signal line 130 can be cited. More specifically, for example, when each pixel PX for red (R), green (G), and blue (B) is driven with 256 gradations, the input image data RGBdata has an 8-bit width for each display color. The process of converting into gradation data having a bus configuration is exemplified. It is also possible to adopt a configuration in which input image data RGBdata is output without performing data processing.

  The control signal S1 for the image signal line drive circuits 301 to 304 includes, for example, a start pulse STH, a latch pulse LP, and the like. The start pulse STH is a signal indicating the start timing of the image data RGBdata in the horizontal direction. The start pulse STH is generated from the dot clock DCLK in synchronization with the horizontal synchronization signal HD, for example. The latch pulse LP is a signal that gives a timing for transmitting the image data RGBdata latched for all the image signal lines 130 from the image signal line driving circuits 301 to 304 to the image signal line 130 of the liquid crystal panel 100.

  Although detailed description is omitted here, the control signal S1 for the image signal line drive circuits 301 to 304 is, for example, a polarity inversion signal (POL, not shown) for inverting the polarity of the liquid crystal drive. It is possible to include.

  The driving signals for the scanning line driving circuits 401 and 402 include, for example, a clock CLKV that serves as a reference when signal processing is performed by the scanning line driving circuits 401 and 402, and a start pulse STV that indicates the start timing in the vertical direction of the image data RGBdata. The control signal S2 is included.

  For the predetermined processing in the timing controller 310, various processing methods employed in an existing external timing controller can be employed. For this reason, detailed description of the predetermined processing in the timing controller 310 is omitted here.

  The predetermined processing performed by the timing controller 310 includes control signal generation processing for generating the control signals S1 and S2 for the drive circuits 301 to 304, 401, and 402 as described above. That is, the timing controller 310 has a control signal generation function (in other words, a control signal generation circuit) that generates the control signals S1 and S2 for the drive circuits 301 to 304, 401, and 402.

  The predetermined processing performed by the timing controller 310 may include image data processing for the image data RGBdata. That is, the timing controller 310 may have an image data processing function (in other words, an image data processing circuit) for the image data RGBdata.

  As described above, each of the image signal line driving circuits 301 to 304 includes the timing controller 310, but one of the image signal line driving circuits 301 to 304 operates a control signal generation function of the timing controller 310. It is used in the mode (see FIG. 4), and the remaining image signal line driving circuits are used in the slave mode (see FIG. 5) in which the control signal generation function is not operated. When the timing controller 310 has an image data processing function, the image data processing function is operated in both master and slave modes. In FIG. 5, signals that are not output from the timing controller 310 are indicated by broken lines in accordance with the slave mode. Here, a case where the image signal line driving circuit 301 (see FIG. 1) is used in the master mode is illustrated.

  The master mode and the slave mode can be set by a mode setting signal S300 input from outside the image signal line driving circuits 301 to 304. For example, in the master mode, power is supplied through a switch (not shown) that is turned on by a mode setting signal S300 at a high potential level (hereinafter referred to as a high level or an H level), thereby causing the control signal generation circuit to Make it work. On the contrary, in the slave mode, the power supply to the control signal generation circuit is cut off by turning off the switch by the mode setting signal S300 at the low potential level (hereinafter referred to as the Low level or the L level).

  The level of the mode setting signal S300 is set, for example, by a dip switch or the like (not shown) in the middle of the mode setting signal line 501 from the H level voltage supply source (for example, a power supply circuit not shown) to the image signal line drive circuits 301 to 304. This is possible by inserting an abbreviation) and setting the on / off state of the switch. In the example of FIG. 1, the mode setting signal line 501 includes a total of four wirings for the image signal line driving circuits 301 to 304. According to such a configuration example, it is possible to easily change the master mode and the slave mode for the image signal line drive circuits 301 to 304 by switching the ON / OFF state of the DIP switch. Further, such a change can be easily performed even after the product is completed.

  Each of the image signal line drive circuits 301 to 304 has an input end for the dot clock DCLK, and the input end is connected to the dot clock supply line 502. The dot clock DCLK is used not only in the timing controller 310 as described above but also in various places in the drive circuits 301 to 304. In FIGS. 4 and 5, the illustration of the supply form of the dot clock DCLK to locations other than the timing controller 310 is omitted to avoid complication of the drawings.

  Each of the image signal line drive circuits 301 to 304 has input ends for image data RGB data, horizontal synchronization signal HD, vertical synchronization signal VD, and data enable signal DENA. These input ends are connected to an image data supply line 503, a horizontal synchronizing signal line 504, a vertical synchronizing signal line 505, and a data enable signal line 506, respectively. In this example, the control reference signal S0 (the horizontal synchronization signal HD, the vertical synchronization signal VD, and the data enable signal is determined by a wiring group including the horizontal synchronization signal line 504, the vertical synchronization signal line 505, and the data enable signal line 506. A control reference signal line 600 for transmitting (DENA) is configured.

  As shown in FIG. 1, in the liquid crystal display device 1, the wirings 502 to 506 are all connected to the image signal line driving circuits 301 to 304 in parallel, and the image signal line driving circuits 301 are connected in parallel. To 304. Therefore, in the liquid crystal display device 1, the dot clock DCLK, the image data RGBdata, the horizontal synchronization signal HD, the vertical synchronization signal VD, and the data enable signal DENA are parallel to the image signal line drive circuits 301 to 304. In other words, they are supplied at the same time.

  Each of the image signal line driving circuits 301 to 304 has an input end for taking in the start pulse STH from the outside of the circuit, and a first output for outputting the start pulse STH generated by the timing controller 310 to the outside of the circuit. And an end portion and a second output end portion for outputting the start pulse STH output from the final stage of the shift register 340 (described later) to the outside of the circuit.

  In the example of FIG. 1, the second start pulse output end of the drive circuit 301 is connected to the start pulse input end of the drive circuit 302 via the start pulse transmission line 507. The second start pulse output end of the drive circuit 302 is connected to the start pulse input end of the drive circuit 303 via the start pulse transmission line 508. The second start pulse output end of the drive circuit 303 is connected to the start pulse input end of the drive circuit 304 via the start pulse transmission line 509.

  Although not shown in FIG. 1 to avoid complication of the drawing, the first start pulse output end of each of the image signal line drive circuits 301 to 304 is a start pulse of the image signal line drive circuit 301. Connected to the input end.

  According to this connection form, the start pulse STH generated by the image signal line drive circuit 300MST in the master mode is input to the drive circuit 301 regardless of which of the image signal line drive circuits 301 to 304 is selected as the master mode. Thereafter, the signals are sequentially transmitted to the driving circuits 302 to 304 in the subsequent stage.

  Each of the image signal line drive circuits 301 to 304 has an input end for taking in the latch pulse LP from the outside of the circuit and an output end for outputting the latch pulse LP generated by the timing controller 310 to the outside of the circuit. doing. 4 and 5, the supply form of the externally input latch pulse LP in the drive circuits 301 to 304 is not shown. However, as described above, the latch pulse LP is output from the drive circuits 301 to 304 as an image. A voltage application timing to the signal line 130 is given.

  In the example of FIG. 1, the latch pulse output end of the drive circuit 301 is connected to the latch pulse input ends of the drive circuits 302 to 304 via the latch pulse transmission line 510. Although omitted in FIG. 1, the latch pulse transmission line 510 is connected to the latch pulse output end of the drive circuit 301 also to its own latch pulse input end. Although omitted in FIG. 1, the latch pulse output ends of the remaining drive circuits 302 to 304 are also connected to the input ends of all the drive circuits 301 to 304.

  According to this connection form, regardless of which of the image signal line drive circuits 301 to 304 is selected as the master mode, the latch pulse LP generated by the image signal line drive circuit 300MST in the master mode is transmitted to all the drive circuits 301 to 304. To 304 at the same time.

  Each of the image signal line drive circuits 301 to 304 has an output end for the clock CLKV. The output ends of the image signal line drive circuits 301 to 304 are connected to the clock transmission line 511. The clock transmission line 511 is connected to the scanning line driving circuits 401 and 402 by connecting the scanning line driving circuits 401 and 402 in parallel. In the example of FIG. 1, only the clock transmission line 511 connecting the driving circuit 301 exemplified as the master mode image signal line driving circuit 300MST and the scanning line driving circuits 401 and 402 is illustrated in order to avoid complication of the drawing. Show.

  Each of the image signal line drive circuits 301 to 304 has an output end for the start pulse STV. The output ends of the image signal line drive circuits 301 to 304 are connected to the start pulse transmission line 512. In the example of FIG. 1, the start pulse transmission line 512 is connected to the scanning line driving circuit 401, and the two scanning line driving circuits 401 and 402 are connected via another start pulse transmission line 513. According to this connection mode, the start pulse STV is transmitted from the scanning line driving circuit 401 to the scanning line driving circuit 402. In the example of FIG. 1, only the start pulse transmission line 512 that connects the driving circuit 301 exemplified as the master mode image signal line driving circuit 300MST and the scanning line driving circuit 401 is provided in order to avoid complication of the drawing. It is shown.

  The various output ends described above are configured by one or a plurality of output terminals depending on the form of wiring to be connected. The same applies to the various input ends described above.

  For example, the scanning line driving circuit 401 inputs the input start pulse STV to a shift register (not shown), and transfers the inside of the shift register according to the clock CLKV. In accordance with such pulse transfer, the scanning lines 140 assigned to the respective stages in the shift register are sequentially driven. When the start pulse STV is output from the final stage of the shift register in the scan line driver circuit 401, the start pulse STV is input to the scan line driver circuit 402 via the transmission line 513. Similarly, the scanning line driving circuit 402 sequentially drives the scanning lines 140 using the start pulse STV.

  In synchronization with scanning of the scanning line 140, the image signal line driving circuits 301 to 304 apply a predetermined voltage to each pixel PX connected to the selected scanning line 140 as described later. Thereby, the entire image is displayed.

  The image signal line drive circuits 301 to 304 will be further described below with reference to FIGS. FIG. 6 is a block diagram outlining a part of the configuration in FIG. 4 and FIG. 7 and 8 are timing charts outlining the operations of the image signal line driving circuits 301 to 304. FIG.

  Each of the image signal line drive circuits 301 to 304 includes a shift register 340, an image data extraction circuit 350, and a data latch circuit 360 in the examples of FIGS.

  An existing shift register can be applied to the shift register 340. A dot clock DCLK and a start pulse STH are input to the shift register 340. 4 and 5, the start pulse STH input from the outside is supplied to the shift register 340 in any of the image signal line drive circuits 301 to 304. According to the above example of the image signal line driving circuits 301 to 304, even if the image signal line driving circuit 300MST is in the master mode, the start pulse STH generated by the timing controller 310 is once transmitted to the outside of the circuit 300MST. It is because it is outputting.

  As illustrated in FIG. 6, the dot clock DCLK is input to each of the plurality of latch circuits 341 constituting the shift register 340. Here, a case where the number of latch circuits 341 is the same as the number of image signal lines 130 assigned to the image signal line driving circuit is illustrated. The start pulse STH is input to the first-stage latch circuit 341.

  Thereby, the shift register 340 sequentially transfers the start pulse STH to the latch circuit 341 at the next stage in synchronization with the dot clock DCLK. The output of the latch circuit 341 at each stage is supplied to the data latch circuit 360. The start pulse STH output from the last-stage latch circuit 341 is output to the outside of the drive circuit and transferred to the image signal line drive circuit 300SLV in the next-stage slave mode.

  The image data extraction circuit 350 is a circuit that receives the image data RGBdata, extracts data of a desired portion from the image data RGBdata, and outputs the extracted image data RGBdata. The image data RGBdata to be extracted is data of a portion necessary for driving the image signal line 130 (see FIG. 1) assigned in advance among the input image data RGBdata. The image data RGBdata output from the image data extraction circuit 350 is supplied to the data latch circuit 360.

  4 and 5, the image data RGBdata is supplied from the timing controller 310 to the image data extraction circuit 350. On the other hand, for example, when the timing controller 310 does not use the image data RGBdata, the image data RGBdata is directly input to the image data extraction circuit 350 from the image data input ends of the image signal line drive circuits 301 to 304. .

  The image data extraction circuit 350 includes a counter 351 and an AND circuit (logical product circuit) 352 in the example of FIG.

  The counter 351 receives the start pulse STH, starts the count operation using the start pulse STH as a trigger, and continues the count operation until a predetermined end value is reached. In the case of the configuration example of FIGS. 4 and 5, the start pulse STH supplied from the outside is supplied to the counter 351 in any of the image signal line driving circuits 301 to 304 as in the case of the shift register 340. Is done.

  In the counting operation, the counter 351 receives the dot clock DCLK, and performs the counting operation in synchronization with the dot clock DCLK. Here, a case where the count end value of the counter 351 is set in advance to the same value as the number of the image signal lines 130 assigned to the image signal line driving circuit is illustrated. In this case, the counter 351 obtains a time obtained by integrating the number of the assigned image signal lines 130 and the time of one cycle of the dot clock DCLK, that is, a time determined according to the number of assigned image signal lines 130. Will be counted.

  The counter 351 outputs an H level signal as the image data extraction enable signal EN during the counting operation (see FIGS. 7 and 8). Note that the image data extraction enable signal EN is in the L level while the counter 351 pauses the counting operation. The enable signal EN is supplied to the AND circuit 352.

  The AND circuit 352 receives the image data extraction enable signal EN and the image data RGBdata as input signals. In view of the waveform of the image data extraction enable signal EN, the AND circuit 352 allows the input image data RGBdata to pass as an output signal only when the enable signal EN is at the H level. On the contrary, while the enable signal EN is at the L level, the image data RGBdata is not masked and output by the AND circuit 352, and the output from the AND circuit 352 continues at the L level. An output signal from the AND circuit 352 is supplied to the data latch circuit 360.

  Thereby, the image data extraction circuit 350 illustrated in FIG. 6 can extract data of a desired portion from the input image data RGBdata.

  An existing data latch circuit can be applied to the data latch circuit 360. The data latch circuit 360 receives an output signal from the image data extraction circuit 350 as an input signal to be latched, and also gives a start pulse STH for shifting in the shift register 340 to a latch signal (so-called latch signal). Receive as. As shown in FIG. 6, the output signal of the image data extraction circuit 350 is input to each of a plurality of latch circuits 361 constituting the data latch circuit 360. The output signal of the latch circuit 341 at each stage of the shift register 340 is input to the latch circuit 361 at the corresponding stage of the data latch circuit 360. In other words, m is a natural number, and the output signal of the m-th latch circuit 341 of the shift register 340 is input to the m-th latch circuit 361 of the data latch circuit 360.

  As a result, the latch circuit 361 at each stage of the data latch circuit 360 outputs the output signal of the output signal of the image data extraction circuit 350 in synchronization with the corresponding latch circuit 341 of the shift register 340 outputting the start pulse STH. Latch.

  In the example of FIG. 6, the number of latch circuits 361 in the data latch circuit 360 is the same as the number of image signal lines 130 assigned to the image signal line driving circuit. That is, each latch circuit 361 has a circuit configuration that captures data necessary to drive one image signal line 130. For example, when the image data RGBdata is 8 bits wide for each display color, each latch circuit 361 illustrated in FIG. 6 has a circuit configuration that latches data for 8 bits simultaneously.

  The image data (that is, gradation data) RGBdata for each image signal line 130 taken in by the data latch circuit 360 is converted into an analog gradation voltage by a D / A converter (not shown), for example, and is output via an output buffer (not shown). Are output to the corresponding image signal line 130. The output timing from the output buffer is defined by a latch pulse LP, and the latch pulse LP is simultaneously supplied to the image signal line driving circuits 301 to 304.

  In the example of FIG. 7, the shift operation of the start pulse STH in the shift register 340, the count operation in the counter 351, and the latch operation in the data latch circuit 360 are performed every cycle of the dot clock DCLK. .

  According to the above configuration, the image data extraction circuit 350 continuously supplies an L level signal to the data latch circuit 360 during a period other than the image data RGB data extraction period. For this reason, in the period other than the image data extraction period, the switching operation of the transistors constituting the data latch circuit 360 can be suspended. Therefore, power saving of the image signal line driving circuits 301 to 304 can be achieved, and as a result, power saving of the driving device 200 and the liquid crystal display device 1 can be achieved.

  In addition, according to the image data extraction circuit 350 illustrated above, a general counter 351 and an AND circuit 352 are applied while a start pulse STH generally used in an image signal line driving circuit is used. Therefore, the image data extraction circuit 350 can be realized with a simple configuration.

  Here, the data extraction function of the image data extraction circuit 350 can be realized by other circuit configurations, and the same effect can be obtained.

  For example, there is a circuit configuration in which the counter 351 is configured to output a signal EN having a waveform obtained by inverting the above waveform, and an OR circuit (logical sum circuit) is provided instead of the AND circuit 352. According to such an example, since the H level signal is input from the counter 351 to the OR circuit during the period other than the image data extraction period, the H level signal is continuously supplied to the data latch circuit 360. Thereby, the switching operation of the transistors constituting the data latch circuit 360 can be suspended.

  In view of this example, the AND circuit 352 and the OR circuit are examples of logic circuits that perform the following functions or operations. That is, when the image data extraction control signal output from the counter 352 (the image data extraction enable signal EN is exemplified above) indicates the first potential, the logic circuit receives the received image data RGBdata as a data latch circuit 360. To supply. On the other hand, when the image data extraction control signal indicates a second potential different from the first potential, the logic circuit uses a constant potential signal (in the above example, a level or H level signal) as data. Supply to the latch circuit.

Embodiment 2. FIG.
FIG. 9 shows a block diagram outlining a liquid crystal display device 1B according to Embodiment 2 of the present invention. The liquid crystal display device 1B illustrated in FIG. 9 has a configuration in which the driving device 200 is replaced with the driving device 200B in the liquid crystal display device 1 (see FIG. 1) according to the first embodiment. The driving device 200B is the same as the driving device 200 according to the first embodiment except that one of the image signal line driving circuits 301 to 304 is fixedly used in the master mode and the wiring form associated therewith. It has a configuration.

  In the example of FIG. 9, the image signal line drive circuit 301 is fixedly used in the master mode. In this case, the control reference signal line 600 for supplying the control reference signal S0 is connected to the image signal line drive circuit 301 in the master mode, but is connected to the image signal line drive circuits 302 to 304 in the slave mode. Not.

  For this reason, the number of wirings is reduced as compared with the configuration according to the first embodiment in which the control reference signal line 600 is connected to all the image signal line drive circuits 301 to 304. Therefore, the wiring arrangement area can be reduced, and as a result, the small driving device 200B and the liquid crystal display device 1B can be obtained. Further, the cost of the wiring member can be reduced by reducing the number of wirings, and the price of the driving device 200B and the liquid crystal display device 1B can be reduced. Further, by reducing the number of wires, noise radiation and reception due to the wires can be reduced, and stable operation of the driving device 200B and the liquid crystal display device 1B can be achieved.

  In addition, the driving signal CLKV and STV wirings 511 and 512 of the scanning line driving circuits 401 and 402 need only be connected to the image signal line driving circuit 301 in the master mode. The above effects can also be obtained with this wiring form.

  Similar effects can be obtained when the image signal line driving circuits 302 to 304 are used in the master mode.

Modified example.
In the first and second embodiments, a case where the liquid crystal panel 100 and the image signal line driving circuits 301 to 304 are connected via a member such as a flexible tape (TCP: Tape Carrier Package / COF: Chip on Film) is illustrated. did. On the other hand, for example, a semiconductor chip on which the image signal line driving circuits 301 to 304 are formed may be mounted on the substrate of the liquid crystal panel 100 in a chip on glass (COG) form. Alternatively, the image signal line drive circuits 301 to 304 can be formed on the substrate of the liquid crystal panel 100 together with the TFTs 111 (see FIG. 3) for the pixels PX. In this case, according to the configuration of the second embodiment, the liquid crystal panel 100 can be downsized by reducing the number of wirings.

  1, 1B liquid crystal display device (display device), 100 liquid crystal display panel (display panel), 130 image signal line, 200, 200B drive device, 300 MST image signal line drive circuit in master mode, image signal line drive circuit in 300 SLV slave mode , 301 to 304 Image signal line drive circuit, 310 timing controller, 350 image data extraction circuit, 351 counter, 352 AND circuit (logic circuit), 360 data latch circuit, 503 image data supply line, 600 control reference signal line, EN image Data extraction enable signal (image data extraction control signal), RGB data image data, S0 control reference signal, S1 control signal, STH start pulse.

Claims (4)

A display panel including a plurality of image signal lines;
A plurality of image signal line drive circuits each driving a predetermined number of image signal lines assigned in advance among the plurality of image signal lines;
An image data supply line for supplying image data to the plurality of image signal line drive circuits,
Each of the plurality of image signal line driving circuits includes a timing controller having a control signal generation function for generating a control signal for controlling the plurality of image signal line driving circuits, and the plurality of image signal line driving circuits One of the drive circuits is used in a master mode that operates the control signal generation function, and the rest of the plurality of image signal line drive circuits is used in a slave mode that does not operate the control signal generation function,
Each of the plurality of image signal line driving circuits includes:
An image data extraction circuit for extracting image data of a portion corresponding to the predetermined number of image signal lines assigned in advance from the image data;
A data latch circuit that latches the image data extracted by the image data extraction circuit,
The image data extraction circuit supplies a signal having a constant potential to the data latch circuit in a period other than the image data extraction period ,
The image data extraction circuit includes:
A start pulse indicating the start timing in the horizontal direction of the image data is received, a predetermined time determined according to the number of the predetermined number of image signal lines from the reception of the start pulse is counted, and the first potential is indicated during the counting operation. On the other hand, a counter that outputs an image data extraction control signal indicating the second potential during the count pause,
The image data and the image data extraction control signal are received, and when the image data extraction control signal is the first potential, the received image data is supplied to the data latch circuit, and the image data extraction control signal is A logic circuit for supplying the signal of the constant potential to the data latch circuit in the case of the second potential;
Having
Display device. The display device according to claim 1,
A control reference signal line for supplying a control reference signal used when the timing controller generates the control signal;
The control reference signal line is connected to the image signal line drive circuit in the master mode, but is not connected to the image signal line drive circuit in the slave mode.
Display device. A drive device for driving a display panel including a plurality of image signal lines,
A plurality of image signal line drive circuits each driving a predetermined number of image signal lines assigned in advance among the plurality of image signal lines;
An image data supply line for supplying image data to the plurality of image signal line drive circuits,
Each of the plurality of image signal line driving circuits includes a timing controller having a control signal generation function for generating a control signal for controlling the plurality of image signal line driving circuits, and the plurality of image signal line driving circuits One of the drive circuits is used in a master mode that operates the control signal generation function, and the rest of the plurality of image signal line drive circuits is used in a slave mode that does not operate the control signal generation function,
Each of the plurality of image signal line driving circuits includes:
An image data extraction circuit for extracting image data of a portion corresponding to the predetermined number of image signal lines assigned in advance from the image data;
A data latch circuit that latches the image data extracted by the image data extraction circuit,
The image data extraction circuit supplies a signal having a constant potential to the data latch circuit in a period other than the image data extraction period ,
The image data extraction circuit includes:
A start pulse indicating the start timing in the horizontal direction of the image data is received, a predetermined time determined according to the number of the predetermined number of image signal lines from the reception of the start pulse is counted, and the first potential is indicated during the counting operation. On the other hand, a counter that outputs an image data extraction control signal indicating the second potential during the count pause,
The image data and the image data extraction control signal are received, and when the image data extraction control signal is the first potential, the received image data is supplied to the data latch circuit, and the image data extraction control signal is A logic circuit for supplying the signal of the constant potential to the data latch circuit in the case of the second potential;
Having
Drive device. The drive device according to claim 3 ,
A control reference signal line for supplying a control reference signal used when the timing controller generates the control signal;
The control reference signal line is connected to the image signal line drive circuit in the master mode, but is not connected to the image signal line drive circuit in the slave mode.
Drive device.

Images