JP2007219205A - Electrooptical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To compatibly provide both low power consumption and high resolution in normal use. <P>SOLUTION: A subpixel 110 in a first display area 100 has a gray scale corresponding to the voltage of a data signal supplied to a data line 114 when a scanning line 112 is selected. A pixel 210 in a second display area 200 has a memory circuit 220, and is in an ON display state when one logic level is held in the memory circuit 220 and in an OFF display state when the other is held. A Y driver 30 while selecting scanning lines 112, row by row, in an entire-screen display mode does not select the scanning lines 112 in a partial display mode. An X driver 40 outputs a data signal corresponding to the gray scale of a subpixel 110 corresponding to a selected scanning line 112 in the entire-screen display mode and also outputs a data signal specifying the ON display or OFF display of a pixel 210 corresponding to a selected row select line 212. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for reducing power consumption of an electro-optical device.

In portable electronic devices such as mobile phones and personal information terminals, battery driving is the principle, so there is a strong demand for low power consumption. Accordingly, there is a strong demand for low power consumption in display devices used for portable electronic devices. For this reason, the full-screen display mode (first display mode) is usually set, while only a partial area of the screen is displayed during standby or the like, and the partial display mode in which other areas are turned off (second display mode) Attempts have been made to reduce power consumption (see Patent Document 1).
JP 2001-255850 A (see FIG. 5)

By the way, such an electro-optical device originally has low power consumption. However, in recent electronic devices, the electro-optical device itself has further low power consumption due to various reasons such as expansion of continuous use time and downsizing of a battery. There is also a strong demand for conversion. On the other hand, there is still a strong demand for high-resolution display, which is one of the performance guidelines for display devices during normal use.
The present invention has been made in view of the above-described circumstances, and an object thereof is an electro-optical device capable of achieving both low power consumption and high resolution during normal use. And providing electronic equipment.

In order to solve the above problems, the electro-optical device according to the present invention is provided in the first display area corresponding to the intersection of the plurality of scanning lines and the plurality of data lines, and each of the scanning lines is selected. Corresponding to a plurality of first pixels having a gradation corresponding to a data signal supplied to the data line, a plurality of row selection lines in the second display region, and a part of the plurality of data lines. Provided in correspondence with intersections with a plurality of bit lines, each having a memory circuit that holds 1 bit, and is turned on when one of the logic levels held in the memory circuit is one On the other hand, a scanning line driving circuit for selecting a plurality of second pixels that are turned off when the logic level is the other, and the scanning lines and the row selection lines, in a predetermined first display mode In some cases, select at least the plurality of scan lines On the other hand, in the predetermined second display mode, at least the scanning line driving circuit that does not select the plurality of scanning lines, and in the first display mode, the gradation of the pixel corresponding to the selected scanning line. In the second display mode, a data signal designating on display or off display of a pixel corresponding to the selected row selection line is output to the bit line. And a data line driving circuit for outputting to a data line corresponding to. According to the present invention, when the first display mode is set, high-resolution display is possible in the first display area, while when the second display mode is set, the display is consumed by at least the display using the second display area. It becomes possible to suppress electric power.

In the present invention, the data line driving circuit includes a D / A conversion circuit that converts data designating a gradation of a pixel corresponding to the selected scanning line into a voltage corresponding to the gradation, and the second In the display mode, the conversion operation by the D / A conversion circuit may be stopped.
In this invention, it is good also as a structure which has a light source which irradiates light to the said 2nd display area, and stops the irradiation by the said light source when it is the said 2nd display mode.
Further, in the present invention, the first pixel has a switching element that is turned on when a logic level when the scanning line is selected is one or the other, and the memory circuit in the second pixel is When the logic level when the row selection line is selected is one or the other, the logic level of the data signal supplied to the bit line is held, and the difference between one and the other of the logic levels of the scanning line A certain logic amplitude is preferably larger than a logic amplitude which is a difference between one and the other of the logic levels of the row selection line.
In this configuration, when the one-bit logic level held in the memory circuit is one of the second pixels, the second pixel selects an OFF signal having the same logic as the common signal, and the held one-bit logic is selected. A selection circuit that selects an ON signal that is in a logically inverted relationship with the OFF signal when the level is the other, and a pixel electrode to which an ON signal or an OFF signal selected by the selection circuit is applied, The pixel electrode may be opposed to a common electrode to which a common signal having the same logic as the off signal is applied. Furthermore, it is desirable that the common signal, the on signal, and the off signal have a low amplitude width that is the same as the logical amplitude of the row selection line.

On the other hand, in the present invention, when the scanning line driving circuit is in the second display mode, the scanning line driving circuit selects a row selection line corresponding to a second pixel for rewriting 1-bit data held in the memory circuit. Also good. Further, in the present invention, the plurality of data lines are divided into blocks each having a predetermined number of columns of 2 or more, and the bit line corresponds to one column of data lines belonging to each block, and the data line driving circuit Sequentially selects data lines of a predetermined number of columns belonging to each block in the first display mode, while the bits of the data lines of a predetermined number of columns belonging to the blocks in the second display mode. A demultiplexer that selects a data line corresponding to the line may be provided.

The above problem is provided in the first display area corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, each of which is a data signal supplied to the data line when the scanning line is selected. A plurality of first pixels having gradations corresponding to the second display area, and a second display area corresponding to intersections of a plurality of row selection lines and a plurality of bit lines, each of which holds 1 bit A plurality of second pixels that are turned on when one of the logic levels held in the memory circuit is one, and turned off when the logic level is the other, A decoder that is provided in a part of the plurality of data lines and that supplies a logic signal supplied to the data line to a bit line of a specified column that is a part of the plurality of bit lines; For selecting the scanning line and the row selection line A scanning line driving circuit that selects at least the plurality of scanning lines when in a predetermined first display mode, and does not select at least the plurality of scanning lines when in a predetermined second display mode. When the scanning line driving circuit and the first display mode are selected, the data signal corresponding to the gradation of the pixel corresponding to the selected scanning line is output to the data line, while the second display mode is selected. A data line driving circuit for outputting a data signal designating on display or off display of a pixel corresponding to the selected row selection line to a data line provided with the decoder is also solved. Is possible.
The present invention can be conceptualized not only as an electro-optical device but also as an electronic apparatus having the electro-optical device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating an electrical configuration of an electro-optical device according to an embodiment of the present invention, and FIG. 2 is a plan view illustrating a configuration of the electro-optical device.
As shown in FIG. 1, the electro-optical device 10 is roughly divided into a voltage generation circuit 12, a control circuit 14, and a display panel 20. Among these, the display panel 20 has a configuration in which an element substrate 22 and a counter substrate 24 are attached to each other as shown in FIG.
As will be described later, the element substrate 22 and the counter substrate 24 are bonded to each other while maintaining a certain gap so that the electrode forming surfaces face each other. For example, TN (twis
ted nematic) type liquid crystal.

The display panel 20 is divided into a first display area 100 and a second display area 200 which are rectangular and have substantially the same length in the X direction. The element substrate 22 has a Y driver 3.
0 is formed on the side in the Y direction adjacent to the first display region 100 and the second display region 200, while the demultiplexer 50 is along the outer side in the X direction in the first display region 100. Is formed. Further, in the element substrate 22, the X driver 40, which is a semiconductor integrated circuit, is located outside the region where the demultiplexer 50 is formed and extends from the counter substrate 24.
Is implemented by COG (chip on glass) technology or the like.
The light source 102 is a so-called backlight unit having a white LED or the like, and uniformly irradiates the first display region 100 with light from the rear element substrate 22 side. Similarly, the light source 20
2 uniformly irradiates the second display area 200 with light from the rear element substrate 22 side.

As shown in FIG. 1, in the first display area 100, 120 scanning lines 112 are arranged in a row (X).
360 (= 120 × 3) provided to extend in the direction and grouped every three columns
) The column data lines 114 are provided so as to extend in the column (Y) direction and to be electrically insulated from each scanning line 112.
The sub-pixels (first pixels) 110 are arranged corresponding to the intersections of the 120 rows of scanning lines 112 and the 360 columns of data lines 114, respectively. Of these, the three sub-pixels 110 corresponding to the intersection of the same scanning line 112 and the three columns of data lines 114 belonging to the same group correspond to R (red), G (green), and B (blue), respectively. Thus, one dot is formed. Therefore,
In the present embodiment, in the first display area 100, when viewed from the sub-pixel 110, the vertical 120 rows × the horizontal 3
It will be arranged in a matrix with 60 columns.
Here, for convenience, in order to generalize and describe the columns in the display area, if an integer j of 1 to 120 is used, the (3j-2) th column from the left in FIG. 1 and (3j-2) The data lines 114 in the column and the (3j) column belong to the j-th block, and R, G
, B series.

On the other hand, in the second display area 200, 20 row selection lines 212 are provided so as to extend in the X direction, and 120 column bit lines 214 are extended in the Y direction, and each row selection line is selected. It is provided so as to maintain electrical insulation from the wire 212. Pixel (second pixel) 2
10 are arranged corresponding to the intersections of the row selection lines 212 of 20 rows and the bit lines 214 of 120 columns, respectively. Therefore, in the present embodiment, in the second display region 200, the pixel 2
10 are arranged in a matrix of 20 rows × 120 columns.
The sub-pixel 110 in the first display area 100 displays the gradation of each color corresponding to any of R, G, and B, but the pixel 210 in the second display area 200 is white (on display).
Alternatively, only black (off display) is displayed.

Data line 114 in first display area 100 and bit line 2 in second display area 200
14, in each block, the logic level in the R-series data line 114 is inverted by the NOT circuit 152, and the inverted logic level is re-inverted by the NOT circuit 154 and supplied to the bit line 214 corresponding to the block. There is a relationship that is.
Therefore, when a data signal supplied corresponding to the j-th block is expressed as dj, the logical level of the data signal dj and the logical level of the bit line 214 corresponding to the j-th block are the same. Therefore, the data signal supplied to the bit line is denoted by dj having the same sign.
Further, in the first display area 100, the sub-pixels 110 correspond to the R, G, and B series data lines of each block, so that three columns are provided for one block, whereas the second display area 200 is provided.
In the pixel 210, the normal signal of the logical signal supplied to the R series data line 114 is supplied to the bit line 214. For this reason, the sub-pixel 210 is provided for each block by one column.
On the other hand, since the pixel 210 has a complementary memory circuit as will be described later in the present embodiment, the bit line 214 of each column is provided with the inverted bit line 215 on a one-to-one basis, and N
The inverted signal from the OT circuit 152 is supplied. For this reason, the data signal d
The logic level of j and the logic level of the inverted bit line 215 corresponding to the jth block are:
Since they are in an inversion relationship with each other, a signal supplied to the inversion bit line is indicated by / dj indicating “/” indicating inversion. For NOT circuits 152 and 154,
This is the low amplitude logic described later.

Although the first display area 100 and the second display area 200 are distinguished for convenience, when all the sub-pixels 110 are in the darkest state and all the pixels 210 are turned off (black display), the display is performed. It is difficult to visually recognize the above difference. Therefore, the first display area 100
In order to explain the display area as an integrated display area without distinguishing the second display area 200, the row selection is performed for the pixel rows, such as the scanning lines 112 in the first to 120th rows and the row selection lines 212 in the 121th to 140th rows. The row number of the line 212 will be described by the serial number following the scanning line 112.

The voltage generation circuit 12 generates a voltage used in this embodiment and supplies it to each unit. More specifically, the logic level of the electro-optical device 10 is 2 between high amplitude logic and low amplitude logic.
Since there are types, the voltage generation circuit 12 has a voltage Vdh corresponding to the H level in the high amplitude logic.
-H, voltage Vdh-L corresponding to L level in high amplitude logic, voltage Vdl-H corresponding to H level in low amplitude logic, and voltage Vdl-L corresponding to L level in low amplitude logic, respectively To do. Among them, the voltage Vdh-L is actually the voltage reference 0 volt and is the ground potential Gnd, and the voltage relationship is Vdh-L (= 0) <Vdl-L <Vdl-H < Vdh-H (see, for example, FIGS. 8 and 9).

The control circuit 14 outputs various control signals for controlling the display panel 20 in accordance with the display mode. In the present embodiment, as a display mode, a full screen display mode (first display mode) for performing display using both the first display area 100 and the second display area 200,
There are two partial display modes (second display mode) in which display is performed using only the second display area 200, and control signal groups Cty, X for controlling the Y driver 30 in accordance with this display mode.
A control signal Sel-R for causing the control signal group Ctx for controlling the driver 40 and the demultiplexer 50 to select one of the R, G, and B series data lines 114 in each block.
, Sel-G and Sel-B are output.
The display mode may be defined by the control circuit 14 itself, or may be specified by a host control circuit or an operator not shown. In any case, the control circuit 1
4, when specifying the full screen display mode, the signal Mod described later is set to H level,
When the partial display mode is designated, the signal Mod is set to L level.

The control circuit 14 controls lighting / non-lighting of the light sources 102 and 202 in accordance with the display mode, and a low-amplitude logic common whose logic level is inverted approximately every 16.7 milliseconds regardless of the display mode. The signal Vcom2 and the off signal Voff having the same logic level as the common signal Vcom2
And an ON signal Von whose logic level is inverted with respect to the common signal Vcom2,
The second display area 200 is supplied.
In FIG. 1, the off signal Voff and the on signal Von are not shown. Also,
As long as the power is turned on, the control circuit 14 continuously executes the logic inversion operation of the common signal Vcom2. The same applies to the off signal Voff and the on signal Von.

In the full screen display mode, the Y driver 30 sequentially selects the scanning lines 112 in the 1st to 120th rows and the row selection lines 212 in the 121st to 140th rows, and the selected scanning line 112.
Alternatively, an H level logic signal is supplied to the row selection line 212 while in the partial display mode,
All the scanning lines 112 in the first to 120th rows are not selected and an L level logic signal is supplied, and in the second display area 200, the row selection line 212 corresponding to the row whose display content is changed is set to the H level. The logic signal is supplied.
Here, logic signals output to the scanning lines 112 in the 1st to 120th rows and the row selection lines 212 in the 121st to 140th rows are denoted as G1 to G120 and G121 to G140. For convenience, when the logic signal output to the scanning line 112 is generally described without specifying the row number, Gm
(M is an integer from 1 to 120), and a logic signal output to the row selection line 212 is generally expressed as Gn (n is a number) when the row number is not specified. It is an integer from 121 to 140).
As will be described later, while the logic signals G1 to G120 are high amplitude logic, the logic signal G
121 to G140 are low amplitude logic.

In the full screen display mode, the X driver 40 uses the Y driver 30 to scan lines 112.
Is selected, the scanning line 112 and three columns of data lines 114 in each block are selected.
Among them, the Y driver 30 outputs a data signal having a voltage corresponding to the gradation of the sub-pixel 110 corresponding to the intersection with the data line designated by the control signals Sel-R, Sel-G, and Sel-B. When the row selection line 212 is selected, the pixel 2 corresponding to the row selection line 212 and each block
The data signal of the logic level according to the display content of 10 is output.
For convenience, the data signal output corresponding to the 1st to 120th blocks is represented by d1.
This is expressed as ~ d120. The data signals d1 to d120 output corresponding to each block are
In the case of general description without specifying the block number, it is expressed as Gj (j is an integer of 1 to 120).
Detailed configurations of the Y driver 30 and the X driver 40 will be described later.

The demultiplexer 50 includes a transmission gate 5 provided for each data line 114.
It is an aggregate of four. Here, the input ends of the three transmission gates 54 corresponding to the data lines 114 belonging to the same block are connected in common and the data signal corresponding to the block is supplied, while the output ends of the transmission gates 54 are It is connected to one end of the data line 114. Further, a control signal Sel-R is supplied to the control terminal (gate) of the transmission gate 54 corresponding to the R-series data line 114, while its inversion control terminal (
A signal obtained by logically inverting the control signal Sel-R by the NOT circuit 28 is supplied to the inverting gate. Similarly, control signals Sel-G and Sel-B are supplied to the control terminal of the transmission gate 54 corresponding to the G and B series data lines 114, while the control signal Sel is supplied to the inversion control terminal.
-G and Sel-B logic inversion signals are supplied.
That is, the j-th block is composed of the data lines 114 of the (3j-2) th column of the R series, the (3j-1) th column of the G series, and the (3j) th column of the B series. The input terminals of the transmission gates 54 corresponding to the data lines 114 in the column are connected in common and supplied with the data signal dj.
Since the data signal is supplied to the data line 114 by the X driver 40 and the demultiplexer 50, the concept of the X driver 40 and the demultiplexer 50 together is a data line driving circuit.

Next, the configuration of the sub-pixel 110 in the first display area 100 and the pixel 210 in the second display area 200 will be described. FIG. 3A is a diagram illustrating an electrical configuration of the sub-pixel 110, and FIG. 3B is a diagram illustrating an electrical configuration of the pixel 210.
Here, FIG. 3A shows three sub-pixels 110 corresponding to the intersections of the m-th scanning line 112 and the three columns of data lines 114 belonging to the j-th group in FIG. The configuration is shown.

As shown in FIG. 3A, the three sub-pixels 110 have the same configuration, and each is an n-channel thin film transistor (hereinafter simply referred to as “TFT”).
116) and a liquid crystal capacitor 140. Among these, the gate of the TFT 116 is connected to the m-th scanning line 112, while the source thereof is the data line 11 corresponding to the pixel.
4 and the drain thereof is connected to the pixel electrode 118 which is one end of the liquid crystal capacitor 140. The other end of the liquid crystal capacitor 140 is the first common electrode 108. This first common electrode 1
08 is common to all the sub-pixels 110 in the first display region 100, and a common signal Vcom1 having a voltage Vdl-L that is constant in time is applied thereto.
In this sub-pixel 110, the logic signal supplied to the m-th scanning line 112 is set to H level (selection voltage is applied), the TFT 116 is turned on (conductive), and the data line 114 and the on-state are connected to the pixel electrode 118. The high (positive polarity) or low (negative polarity) voltage corresponding to the target gradation (brightness) as compared with the voltage Vdl-L of the common signal Vcom1 is applied via the TFT 116 in the state. Thus, the liquid crystal capacitor 140 can hold a voltage corresponding to the gradation.
Each of the sub-pixels 110 is provided with a storage capacitor so as to be electrically in parallel with the liquid crystal capacitor 140, but is not shown because it is not directly related to the present invention.

On the other hand, FIG. 3B shows the configuration of the pixel 210 corresponding to the intersection of the n-th row selection line 212 and the j-th bit line 214 counted from the left in FIG.
As shown in this figure, the pixel 210 includes a static memory circuit 220, a selection circuit 230, and a liquid crystal capacitor 240. Among these, the memory circuit 220 includes n-channel TFTs 221 and 222 and NOT circuits 225 and 226. The TFT 221 has its source connected to the j-th bit line 214, its drain connected to the input terminal of the NOT circuit 225, and its gate connected to the n-th row selection line 212. The output terminal of the NOT circuit 225 is connected to the input terminal of the NOT circuit 226, and the output terminal of the NOT circuit 226 is fed back to the input terminal of the NOT circuit 225.
Note that since the memory circuit 220 is a complementary type, the source of the TFT 222 is connected to the inverted bit line 215 of the j-th column, its drain is connected to the input terminal of the NOT circuit 226, and its gate is the n-th row. Are connected to the row selection line 212.

Therefore, in the memory circuit 220, the logic signal G supplied to the row selection line 212 of the nth row.
When n becomes H level, both the TFTs 221 and 222 are turned on, and the logic level of the data signal dj supplied to the bit line 214 is stored at the terminal Q (the inverted data signal // supplied to the inverted bit line 215). dj is stored at the terminal / Q), and thereafter, even if the logic signal Gn becomes L level and the TFTs 221 and 222 are turned off, the stored contents are statically held.

The selection circuit 230 has transmission gates 232 and 234. Here, the input terminal of the transmission gate 232 is connected to the signal line 251 to which the ON signal Von is supplied, while the input terminal of the transmission gate 234 is connected to the signal line 252 to which the OFF signal Voff is supplied. The output ends of the gates 232 and 234 are commonly connected to pixel electrodes 218 formed individually for each pixel.
Also, the control gate of transmission gate 232 and the inversion control gate of transmission gate 234 are connected to terminal Q in memory circuit 220, while the inversion control gate of transmission gate 232 and the control gate of transmission gate 234 are in memory circuit 220. Connected to terminal / Q.
Therefore, if the logic signal held at the terminal Q is H level (if the terminal / Q is L level), the transmission gates 232 and 234 are turned on and off, respectively, and the on signal Von is applied to the pixel electrode 218. On the other hand, if the logic signal held at the terminal Q is L level (if the terminal / Q is H level), the transmission gates 232 and 234 are turned off and on, respectively, and the off signal Voff is changed to the pixel electrode 218. It is the structure applied to.
The liquid crystal capacitor 240 has a pixel electrode 218 at one end and a second common electrode 208 at the other end.
Thus, the liquid crystal 105 is sandwiched. Here, the second common electrode 208 is common to all the pixels 210 in the second display region 200, and the common signal Vcom2 that is logically inverted every frame period is applied thereto.

In the present embodiment, the average amount of transmitted light per unit time of the liquid crystal capacitor 140 in the first display region 100 and the liquid crystal capacitor 240 in the second display region 200 changes according to the held voltage effective value. Specifically, both the liquid crystal capacitors 140 and 240 are set to be in a normally black mode in which the amount of transmitted light decreases as the held voltage decreases.
However, since the liquid crystal capacitor 140 holds a voltage corresponding to the gradation, gradation display is possible, whereas the liquid crystal capacitor 240 holds only a voltage corresponding to on or off. Only a binary display of a bright state (white) or a dark state (black) is possible.

Next, details of the Y driver (scanning line driving circuit) 30 will be described. FIG. 4 is a diagram illustrating the configuration of the Y driver 30.
In the figure, the shift register 31 uses the low-amplitude logic voltage Vdl-H and voltage Vdl-L (the difference voltage) as the power supply, and is the sum of the number of scanning lines “120” and the row selection line “20”. 140 ". Here, the shift register 31 receives the clock signal CLY as shown in FIG.
Transfer start pulse D having a pulse width corresponding to a half cycle of the clock signal CLY every time.
Y is sequentially shifted, and the shift signals are output as Y1, Y2, Y3,..., Y120, Y121,.
In the present embodiment, the shift register 31 is in the partial display mode even in the full screen display mode, and continuously executes the shift operation as long as the power is turned on.
Further, which shift signal becomes the H level is determined by the number of transitions of the logic level of the clock signal CLY after the input of the transfer start pulse DY. Therefore, regarding the state of the shift operation in the shift register 31, the transfer start pulse DY and the clock signal CLY
Can be grasped on the control circuit 14 side from the output.

The level shifter (LS) 32, the NAND circuit 33, and the NOT circuit 34 are respectively 1 to
It is provided corresponding to the scanning line 112 in the 120th row, and operates using the voltage Vdh-H and the voltage Vdh-L of high amplitude logic as power sources. Among them, the level shifters 32 in the 1st to 120th rows respectively convert the low amplitude logic shift signals Y1, Y2, Y3,..., Y120 into high amplitude logic signals.
On the other hand, the level shifter (LS) 36 operates using the high-amplitude logic voltage Vdh-H and the voltage Vdh-L as power sources, and converts the low-amplitude logic output permission signal Oe into a high-amplitude logic signal.
The NAND circuit 33 outputs a negative logical product signal of the shift signal converted to high amplitude logic and the output permission signal Oe, and the NOT circuit 34 reinverts the logic of the negative logical product signal to scan line 1.
12 is supplied. In other words, a signal output from the NOT circuit 34 corresponding to the m-th row is supplied to the m-th scanning line 112 as the logic signal Gm.

On the other hand, the NAND circuit 37 and the NOT circuit 38 are provided corresponding to the row selection lines 212 of the 121st to 140th rows, respectively, and operate using the low amplitude logic voltage Vdl-H and the voltage Vdl-L as power sources.
More specifically, the NAND circuit 37 outputs a negative logical product signal of the low amplitude logic shift signal and the output permission signal Oe, and the NOT circuit 38 reinverts the logic of the negative logical product signal to re-invert the row selection line 212. To supply. In other words, a signal output from the NOT circuit 38 corresponding to the nth row is supplied to the row selection line 212 of the nth row as the logic signal Gn.
The low-amplitude logic clock signal CLY, the transfer start pulse DY, and the output permission signal Oe
Is supplied from the control circuit 14 (see FIG. 1), and a generic term for these is the control signal group Cty.

Next, details of the X driver 40 will be described. FIG. 6 is a diagram illustrating the configuration of the X driver 40.
As shown in this figure, a memory circuit 402, a latch circuit (L) 404, a D / A conversion circuit (DAC) 406, a normal / inversion amplification circuit 408, and switches 410 and 412 are provided corresponding to each block. It is done. Among these, the storage circuit 402 has storage areas of 120 rows × 3 columns and 20 rows × 1 column. Here, for example, the storage circuit 402 corresponding to the first block has R, G, and B sub-pixels that constitute the pixels of the first column in the first to 120th rows in the storage area of 120 rows × 3 columns. While data defining 110 gradations is stored, data defining on / off of the pixels 210 in the 121st to 140th rows and the first column is stored in a storage area of 20 rows × 1 column, respectively.

Furthermore, in the memory circuit 402, when the row designated by the control signal Sy is the 1st to 120th rows, if the control signal Sel-R is H level from the storage area corresponding to the designated row, R
The data defining the gradation of the sub-pixel 110 is read out, and similarly, the control signals Sel-G, Sel-B
If H is H level, data defining the gradation of the B and G sub-pixels 110 is read out. Further, in the memory circuit 402, when the rows designated by the control signal Sy are the 121st to 140th rows, the data defining the on / off of the pixel 210 is read from the storage area corresponding to the designated row. It is. Here, the row specified by the control signal Sy coincides with the scanning operation by the shift register 31, that is, the scanning line 112 or the row selection line 212 corresponding to the shift signal that becomes the H level.
The data defining the gradation of the sub-pixel 110 is a plurality of bits (for example, 8 bits), but the data defining the on / off of the pixel 210 is 1 bit, and the display contents of these data are changed. In such a case, the upper control circuit (not shown) can be rewritten.

The latch circuit 404 latches data read from the storage circuit 402. The D / A conversion circuit 406 receives the data latched by the latch circuit 404 as the subpixel 11.
In the case of a plurality of bits of data defining a gradation of 0, the voltage Vdl-L (first common electrode 10
8) is converted into a high-order analog signal by a voltage corresponding to the data of the plurality of bits. When the polarity instruction signal Pol is at the H level, the normal rotation / inversion amplification circuit 408 outputs the analog signal from the D / A conversion circuit 406 in the normal rotation (voltage amplification coefficient “+1”), while the polarity instruction signal Pol is L If it is level, the analog signal is inverted and output (voltage amplification coefficient “−1”) with reference to the voltage Vdl-L.
The D / A conversion circuit 406 and the normal / inversion amplification circuit 408 are configured to stop operating when the signal Mod becomes L level and the partial display mode is designated.
The polarity instruction signal Pol is a signal for designating the writing polarity for the liquid crystal capacitor 140.
For example, if H level, positive polarity writing is designated, and if L level, negative polarity writing is designated. In addition,
In the present embodiment, the polarity of the polarity instruction signal Pol is inverted every frame period as shown in FIG. For this reason, in the period of one frame, all the liquid crystal capacitors 140 have the same writing polarity, and the writing polarity is inverted every frame. In this embodiment, so-called surface inversion driving is performed. This is not intended to limit the present invention.

On the other hand, the switch 410 is a double throw type, and when the data latched by the latch circuit 404 is 1-bit data defining the gradation of the pixel 210, the logic of the data is “
If “1”, the power supply line of the voltage Vdl-H corresponding to the H level of the low amplitude logic is selected as indicated by the solid line, and if the data is “0”, the low amplitude is indicated as indicated by the broken line. A power supply line with a voltage Vdl-L corresponding to a logical L level is selected.
The switch 412 is a double throw type. When the control signal Scn is at the H level, the switch 412 selects the output signal from the forward / reverse amplification circuit 408 as shown by the solid line, whereas when the control signal Scn is at the L level, it is indicated by the broken line. The output terminal (common terminal) of the switch 410 is selected so as to be selected. Here, the control signal S
cn becomes H level over a period when any one of the shift signals Y1 to Y120 by the shift register 31 is H level, and becomes L level over a period when any one of the shift signals Y121 to Y140 becomes H level (FIG. 5). reference).

Such a memory circuit 402, latch circuit (L) 404, D / A conversion circuit (DAC) 40
6, a normal / inversion amplification circuit 408 and a set of switches 410 and 412 are provided corresponding to the first to 120th blocks, and the signal selected by the switch 412 is the data signal d.
1 to d120 are output.
Note that the polarity instruction signal Pol, the control signals Scn, Sy, the signal Mod, and the access signal (not shown) to the storage circuit 402 are supplied from the control circuit 14 and are collectively referred to as the control signal group Ctx in FIG. It corresponds to.

In this configuration, if the signal Mod is at the H level and the full screen display mode, the X driver 40 operates the D / A conversion circuit 406 and the normal / inversion amplification circuit 408 and shift signals Y1 to Y120. Is one of the H levels (the control signal Scn is at the H level), the switch 412 selects the output signal from the normal / inversion amplification circuit 408, so that the data signal dj corresponding to the jth block is at the H level. A scanning line 112 to which a logic signal is supplied, and has a voltage corresponding to the gradation of the sub-pixel 110 specified by the control signals Sel-R, Sel-G, and Sel-B among R, G, and B in the block. In addition, the voltage has the polarity specified by the polarity instruction signal Pol.
In the full screen display mode, if any of the shift signals Y121 to Y140 is H level (the control signal Scn is L level), the switch 412 selects the output terminal of the switch 410, so the data signal dj Is a low-amplitude logic signal designating on or off of the pixel 210 corresponding to the row selection line 212 and the block to which the H-level logic signal is supplied.

On the other hand, if the signal Mod is at the L level and the partial display mode, the X driver 40
Since the / A conversion circuit 406 and the normal / inversion amplification circuit 408 stop operating, the switch 41
Even if 2 selects the output signal from the normal / inversion amplification circuit 408, the data line 114 is not driven.
In the partial display mode, if any of the shift signals Y121 to Y140 is H level (the control signal Scn is L level), the data signal dj is the same as in the full screen display mode.
The data signal dj is a low-amplitude logic signal designating on or off of the pixel 210 corresponding to the row selection line 212 and the block to which the H level logic signal is supplied.

Next, the operation of the electro-optical device 10 will be described.
In this embodiment, as described above, there are two display modes, the full screen display mode and the partial display mode, so the case of the full screen display mode will be described first, and then the case of the partial display mode. I will explain.

FIG. 7 is a diagram for explaining the operation on the Y side in the full screen display mode, and FIGS. 8 and 9 are diagrams for explaining the operation on the X side.
First, in the full screen display mode, the control circuit 14 sets both the light sources 102 and 202 in order to set the signal Mod to the H level and perform display using both the first display area 100 and the second display area 200. Lights up.
Further, in the full screen display mode, the control circuit 14 fixes the output permission signal Oe to the H level. As a result, in the Y driver 30, the shift signal Y1-
Among Y140, Y1 to Y120 are converted to high amplitude logic by the level shifter 32, and
Y121 to Y140 are output as logic signals G1 to G140, respectively, in a state where they are kept at low amplitude logic.
In other words, in the full screen display mode, the logic signals G1 to G120 are exclusively at the H level in order for each period H over a period of one frame. Here, the period of one frame is about 16.7.
Milliseconds (the reciprocal of 60 Hz). In FIG. 7, since the level of the logic signal is a problem, the difference in amplitude between the low amplitude logic and the high amplitude logic is ignored.

Next, the display operation of the first display area 100 in the full screen display mode will be described. In the full-screen display mode, the logic signals G1 to G120 are sequentially set to the H level every period H. At this time, as shown in FIG. 7, the control circuit 14 controls the control signal Scn over a period in which the logic signal G1 (shift signal Y1) to the logic signal G120 (shift signal Y120) are at the H level.
To H level.
Here, in order to generalize the logic signals G1 to G120 without specifying a row, the logic signal G
Explaining the period during which m is at the H level, as shown in FIG.
In this period, the control signals Sel-R, Sel-G, and Sel-B are exclusively set to the H level in this order.

When the control signal Sel-R becomes H level in the period when the logic signal Gm supplied to the m-th scanning line 112 becomes H level, for example, the data signal dj output corresponding to the jth block. As described above, the scanning line 112 in the m-th row and R in the j-th block
It is a voltage according to the gradation of the sub-pixel 110 corresponding to the data line 114 of the series, and has a polarity specified by the polarity instruction signal Pol. Further, when the control signal Sel-R becomes H level, the transmission gate 54 corresponding to the R series data line 114 is turned on.
The data signal dj is supplied to the R series data line 114 in the j-th block.
When the logic signal Gm becomes H level, the sub-pixel 11 corresponding to the m-th scanning line 112 is displayed.
Since the TFT 116 is turned on at all 0s, the data signal dj supplied to the R-series data line 114 in the j-th block passes through the turned-on TFT 116 and the scanning line 112 in the m-th row and the j-th block. R corresponding to intersection with R series data line 114
Applied to the pixel electrode 118 of the sub-pixel 110. Thus, the liquid crystal capacitor 140 of the R subpixel has a voltage corresponding to the difference between the voltage Vdl-L of the first common electrode 108 and the voltage of the data signal dj, that is, the gradation of the R subpixel. Written.

Next, when the control signals Sel-G and Sel-B become H level in this order, the data signal dj is transmitted between the m-th scanning line 112 and the G- and B-series data lines 114 in the j-th block. G and B series data lines in the j-th block, which are voltages according to the gradation of the G and B sub-pixels 110 corresponding to the intersection, and which have the polarity specified by the polarity instruction signal Pol. 114 are sequentially supplied, and voltages corresponding to the gradations of the G and B subpixels are written in the liquid crystal capacitors 140 of the G and B subpixels, respectively.
As a result, voltages corresponding to gradations are sequentially applied to the three sub-pixels corresponding to the intersections of the m-th scanning line 112 and the R-, G-, and B-series data lines 114 constituting the j-th block. It is written.

FIG. 8 shows the voltage change of the data signal dj output corresponding to the jth block during the period H in which the logic signal Gm is at the H level.
The voltage of the data signal dj in the period H changes from the voltage Vbp corresponding to the darkest state to the brightest state in the normally black mode if the polarity instruction signal Pol is H level and the positive polarity writing is designated. In the range up to the corresponding voltage Vwp, on the other hand, the polarity indication signal P
If ol is L level and negative polarity writing is specified, the voltage Vbm corresponding to the darkest state
In the range from the voltage Vwm corresponding to the brightest state to the voltage Vdl-L of the first common electrode 108, the voltage has a difference corresponding to the gradation of the pixel.
Here, the positive voltage Vwp (and Vbp) and the negative voltage Vwm (Vbm) are symmetrical with each other around the voltage Vdl-L.
As described above, the voltage reference in the present embodiment is Vdh-L (= Gnd).
Regarding the writing polarity, since it is a problem whether the voltage of the pixel electrode 118 is higher or lower than the voltage of the first common electrode 108 in the liquid crystal capacitor 140, the reference potential of the writing polarity is the first This is the voltage Vdh-L of the common electrode 108. That is, the higher side than the voltage Vdh-L has a positive polarity, and the lower side has a negative polarity.
Note that the vertical scale of the voltage of the data signal dj in FIG. 8 is enlarged as compared with the voltage waveforms of other logic signals (this is also true for FIG. 9).

Here, the writing operation has been described for the three sub-pixels corresponding to the j-th block. However, in the period in which the logic signal Gm is at the H level, the m-th row is 1, 2, 3,.
, The same writing operation is also executed in parallel for the sub-pixels 110 corresponding to the 120th block.
Further, here, the writing operation for one row of pixels located on the m-th scanning line 112 has been described. However, in reality, the logic signals G1 to G120 sequentially become H level. Are executed in the order of the first, second, third,..., 120th rows.

Next, the display operation of the second display area 200 in the full screen display mode will be described.
Similarly, in the full screen display mode, the logic signals G121 to G140 sequentially become H level exclusively every period H. However, as shown in FIG. 7, the control circuit 14 detects the logic signal G121 (shift signal Y1).
21) to the logic signal G140 (shift signal Y140), the control signal Scn is set to the L level during the period in which the control signal Sel-R is set to the H level.
The control signals Sel-G and Sel-B are set to L level.

Here, in order to generalize the logic signals G121 to G140 without specifying a row, a period in which the logic signal Gn is at the H level will be described. As shown in FIG. 9, during the period when the logic signal Gn supplied to the row selection line 212 of the nth row is at the H level, for example, the data signal dj output corresponding to the jth block is the above-described one. As described above, the voltage corresponds to the ON or OFF state of the pixel 210 corresponding to the nth row selection line 212 and the jth block.
Specifically, as shown in FIG. 9, when the pixel 210 is turned on (white display in the normally black mode), the data signal dj is a voltage corresponding to the H level of the low amplitude logic as shown by the solid line. Vdl-H. For this reason, the inverted data signal / dj becomes a voltage Vdl-L corresponding to the L level of the low amplitude logic as shown by the broken line.
On the other hand, when the pixel 210 is turned off (black display in the normally black mode), the data signal dj becomes the voltage Vdl-L as shown by the solid line. For this reason, the inverted data signal / dj becomes the voltage Vdl-H as shown by the broken line.

When the control signal Sel-R becomes H level, the transmission gate 54 corresponding to the R series data line 114 is turned on, so that the data signal dj is supplied to the R series data line 114 in the jth block. Then, the signal is supplied to the bit line 214 through two inversions by the NOT circuits 152 and 154, and is supplied to the inversion bit line 215 through one inversion by only the NOT circuit 152.
When the logic signal Gn becomes H level, the TFTs 221 and 222 in the pixel 210 in the n-th row.
Is turned on, the logic level of the data signal dj supplied to the bit line 214 is written to the terminal Q in the memory circuit 220, and the logic level of the inverted data signal / dj is written to the terminal / Q.

Here, the writing operation has been described for the pixel 210 corresponding to the j-th block. However, in the period in which the logic signal Gn is at the H level, the n-th row is 1, 2, 3,.
A similar writing operation is also performed in parallel on the pixels 210 of the 120th block.
Further, here, the writing operation for one row of pixels located on the n-th scanning line 112 has been described. However, in reality, the logic signals G121 to G140 sequentially become H level. Is written after the last 120th line in the first display area 100 is written.
121, 122, 123,..., Executed in the order of the 140th row.

Next, it will be described from the viewpoint of what happens to the liquid crystal capacitor 240 when the logic level of the data signal is written in the memory circuit 220. FIG. 10 shows the voltage applied to the liquid crystal capacitor 240 according to the logic level held in the memory circuit 220 and the common signal Vcom2.
It is a figure shown in the relationship between the ON signal Von and the OFF signal Vof f.
As described above and as shown in FIG. 10, the off signal Voff and the on signal Von have the same and inverted relationship with the logic level of the common signal Vcom2 applied to the second common electrode 208. In the memory circuit 220 of the pixel 210, when an L level logic signal is held at the terminal Q (when an H level logic signal is held at the terminal / Q), the transmission gates 232 and 234 are turned off and on, respectively. Therefore, the pixel electrode 21 of the pixel
8 is applied with an off signal Vof f having the same logic level as that of the common signal Vcom2.
For this reason, the voltage VLC applied to the liquid crystal capacitor 240, here, the voltage obtained by subtracting the potential of the second common electrode 208 from the potential of the pixel electrode 218 becomes zero as shown in FIG. If the mode is selected, the pixel is turned off.

On the other hand, in memory circuit 220, when a logic signal at H level is held at terminal Q (when a logic signal at L level is held at terminal / Q), transmission gate 2
Since 32 and 234 are turned on and off, respectively, an on signal Von having a relationship in which the logic level of the common signal Vcom2 is inverted is applied to the pixel electrode 218 of the pixel. Therefore, the voltage VLC applied to the liquid crystal capacitor 240 is + (Vdh−H) or − (Vdh−L). Therefore, in the normally black mode, the pixel is turned on.

Thus, in the full screen display mode, the logic signals G1 to G1
G140 becomes H level every period H in this order, and among these, the logic signals G1 to G120 become H level in order, so that the voltage of the data signal is written to each sub-pixel 110 in the first display area 100. The gradation display according to the voltage is performed while the logic signals G121 to G121
When G140 sequentially becomes H level, the logic level of the data signal designating ON / OFF is written to the memory circuit 220 of each pixel 210 in the second display area 200,
On (white) / off (black) display according to the logic level is performed.

In this embodiment, the logic level of the polarity instruction signal Pol for designating the writing polarity for the liquid crystal capacitor 140 is inverted every one frame period, and the logic level of the common signal Vcom2 applied to the second common electrode 208 is also changed. For example, if the polarity instruction signal Pol becomes H level in the odd-numbered n frame (see FIG. 7) and the common signal Vcom2 is in L level (see FIG. 10), the first display is performed in the odd-numbered n frame. Subpixel 1 in region 100
In the ten pixel electrodes 118, a positive voltage is written, and the pixel 2 in the second display area 200 is written.
If the ten pixel electrodes 218 are turned on, a higher voltage than the second common electrode potential is written. On the next even (n + 1) frame, a negative voltage is written on the pixel electrode 118 and on the pixel electrode 218. In the case of display, a lower voltage than the second common electrode potential is written.
For this reason, in both the liquid crystal capacitor 140 of the first display region 100 and the liquid crystal capacitor 240 of the second display region 200, the holding voltage is inverted (AC drive) for each frame. Deterioration will be prevented.

In the present embodiment, the logic signals G121 to G140 are sequentially set to the H level in the full screen display mode. However, since the memory circuit 220 is a static type, the pixel 210 whose on or off state is not changed is described. Therefore, it is not necessary to rewrite the contents held in the memory circuit 220. For this reason, the output permission signal Oe is set to the L level at the timing when the shift signal corresponding to the row becomes the H level for the pixels 210 for one row whose ON or OFF state is not changed even in the full screen display mode. The logic signal supplied to the row selection line 212 of the row may be set to the L level.

Next, the operation in the partial display mode will be described.
When shifting from the full screen display mode to the partial display mode, the control circuit 14 causes all the sub-pixels 110 in the first display region 100 to be in the darkest state using the last one frame period in the full screen display mode. Write voltage Vbp or Vbm. As a result, regardless of the data defining the gradation of the subpixel 110 stored in the memory circuit 402, all the subpixels 110 are forcibly displayed in black corresponding to the off display in the normally black mode.
Next, in the partial display mode, the control circuit 14 sets the signal Mod to the L level and turns off the light source 102 to perform display using only the second display region 200, and the light source 2.
Turn on only 02.

By the way, the partial display mode is divided into a case where the display content of the pixel 210 in the region is changed and a case where the display content is not changed.
In the partial display mode, when the display content of the pixel 210 in the second display area 200 is changed, the control circuit 14 causes the shift signal corresponding to the row whose display content needs to be rewritten in the second display area 200 to be H level. The output permission signal Oe is set to the H level only during the period, and the output permission signal Oe is set to the L level during the other periods.

FIG. 11 shows an example of changing the display contents of the pixels 210 in all rows in the 121st to 140th rows belonging to the second display region 200 in the partial display mode.
In the partial display mode, since the output permission signal Oe is at L level during the period when the shift signals Y1 to Y120 are at H level, the logic signals G1 to G120 are all at L level. For this reason, all the sub-pixels 110 in the first display region 100 maintain black display.
When the shift signal corresponding to the row whose display content needs to be rewritten in the second display area 200 becomes H level, the output permission signal Oe becomes H level. Therefore, the H level shift signal is directly used as a logic signal. This is supplied to the selection line 212. At this time, when the logic signal Gn supplied to the row selection line 212 of the nth row becomes H level, as described above, the pixels of the 120th block in the nth row and in the 1, 2, 3,. 210 (the memory circuit 220) is written with data designating ON or OFF, respectively.
Then, the ON signal Von according to the logic level of the data held in the memory circuit 220.
Alternatively, since the off signal Voff is selected by the selection circuit 230 and applied to the pixel electrode 218, each pixel 210 is turned on (white) or off (black) according to the logical level of the data.

On the other hand, in the partial display mode, when all the display contents of the pixels 210 in the second display area 200 are not changed, the control circuit 14 fixes the output permission signal Oe at the L level.
For this reason, not only the logic signals G1 to G120 but also the logic signals G121 to G140 are all at L level regardless of the shift signal, so that all the sub-pixels 110 in the first display area maintain black display. The pixels 210 in the second display area are turned on (white) or turned off (black) according to the logic level of the stored data.
Note that the common signal Vcom2 (the ON signal Von and the OFF signal Voff) is logically inverted every frame period even in the partial display mode, so that a DC component is applied to the liquid crystal capacitor 240 of the pixel 210 that is turned on. There is no.

As described above, in the partial display mode, only the logic signal corresponding to the row whose display content needs to be rewritten in the second display area 200 is set to the H level, so that the scanning line 112 and the row selection line 212 that do not need to be rewritten are not driven. . For this reason, it becomes possible to suppress the power consumed by the parasitic capacitance.
Further, in the partial display mode, the logic signals G 1 to G 120 do not become H level, so that it is not necessary to operate the D / A conversion circuit 406 and the buffer circuit 408 in the X driver 40. For this reason, in the present embodiment, when the partial display mode is designated by the mode signal Mod, the operations of the D / A conversion circuit 406 and the buffer circuit 408 are prohibited, and thus the power consumed by these circuits. In addition, since the data line 114 is not driven,
Low power consumption can be achieved. Similarly, since the light source 102 that irradiates the first display region 100 with light is not turned on, power consumption can be reduced accordingly.
In the period during which the output permission signal Oe is at the L level, the level shifter 32 in the Y driver 30 does not output the voltage Vdh-H corresponding to the H level in the high amplitude logic, so that the boosting operation is stopped. It is also good.

In the above-described embodiment, the pixel 210 in the second display area includes the memory circuit 220.
Although only binary display of ON display or OFF display can be performed according to the logic level of the data signal held in FIG. 1, one pixel is expressed by a plurality of subpixels similarly to the subpixel 110 described above. Depending on the number (area) of on-display (or off-display) of subpixels, one pixel may be displayed in gray scale, or a color gray scale display may be performed using area gray scale in combination.
In the embodiment, the pixel 210 of the second display area 200 is provided in one column for the three series of R, G, and B of the first display area 100. However, the columns 6, 9, 12,. On the other hand, a configuration in which one column is provided may be used, or 1 may be applied to two or more sequences other than multiples of 3 ignoring the color relationship.
A configuration in which rows are provided may be employed.
Furthermore, for example, C (cyan) or the like may be added to RGB to form one dot with four or more subpixels.

On the other hand, the pixel 210 has a more complicated circuit configuration than the sub-pixel 110 (see FIG. 3).
The aperture ratio cannot be increased due to the relationship between wiring and element space. Therefore, the pixel 210
May be of a reflective type. When the pixel 210 is of a reflective type, the sub-pixel 210 may be semi-transmissive having both transmissive and reflective properties so that the sub-pixel 210 also has reflective characteristics. Note that when the pixel 210 is of a reflective type, the light source 202 is not necessary.

In the embodiment described above, one column 210 of pixels in the second display region 200 is provided for three columns of sub-pixels 110 in the first display region.
If the two arrangement pitches are equal, the display resolution of the second display area 200 is the first display area 100.
It will be inferior to the display resolution.
Therefore, the display resolution of the second display area 200 may be equal to the display resolution of the first display area 100. However, the bit line 214 and the inverted bit line 2 are simply connected to the data line 114 in one column.
15, the pixel 210 in a certain row in the second display area 200 is configured.
In order to write the logic level of the data signal to the (memory circuit 220), all the data lines 114 are driven with low amplitude logic, which is not a good measure from the viewpoint of reducing power consumption.

For this reason, as shown in FIG. 12, the decoder 160 may distribute the logic level and the inverted logic level of the data line 114 to any of the R, G, and B groups.
Specifically, in the second display area 200, the bit line 214 and the inverted bit line 21 are set so as to be the same as the arrangement pitch of the R, G, B series data lines 114 in the first display area 100.
Five R, G, and B pairs are provided, and R, G,
A B sub-pixel 210 is provided. In FIG. 12, the second display area 200
Then, reference numeral 210 changes from a pixel to a sub-pixel, but the circuit configuration itself is the same as in FIG.
In the example shown in FIG. 12, the decoder 160 controls the pair of the logical level of the R-series data line 114 that is normally rotated by the NOT circuits 152 and 154 and the one that is inverted by the NOT circuit 152. The signal Sel-1 and Sel-2 are distributed in order to any pair (bit line 214 and inverted bit line 215) designated by 2 bits of the signals Sel-1 and Sel-2.
In FIG. 12, the X driver 40 and the Y driver 30 in the display panel 20 are omitted for convenience.

According to this configuration, in order to write the logic level of the data signal to the sub-pixels 210 in a row in the second display region 200, only the R-series data line 114 has to be driven with low amplitude logic. As a result, it is possible to reduce the power consumption.
Note that, here, the decoder 160 is provided in a ratio of one for three columns in the first display area, but it may be provided in a ratio of one for two or more columns. For example, it may be provided at a rate of one for six rows. Thus, as the ratio of the decoder 160 to the column is reduced,
When writing the logic level of the data signal to the sub-pixel 210, the number of columns for driving the data line 114 can be reduced, which is convenient for reducing power consumption. It must be noted that the number of wirings increases as the number of control signals increases as the number of control signals increases.

In the above description, the voltage V applied to the first common electrode 108 is used as the reference for the write polarity.
This is a case where the TFT 116 in the sub-pixel 110 functions as an ideal switch. Actually, the state is switched from on to off due to the parasitic capacitance between the gate and the drain of the TFT 116. When the voltage changes, a phenomenon that the potential of the drain (pixel electrode 118) decreases (referred to as push-down, penetration, field-through, etc.) occurs. In order to prevent the deterioration of the liquid crystal, the liquid crystal capacitor is basically driven by alternating current, but the first common electrode 1
When the AC drive is performed using the voltage Vdl-L applied to 08 as a reference for the writing polarity, the voltage effective value of the liquid crystal capacitor 140 by the negative polarity writing is slightly larger than the effective value by the positive polarity writing due to pushdown. It becomes large (when TFT 116 is n-channel). Therefore, in practice,
The reference voltage of the write polarity and the voltage Vdl-L of the first common electrode 108 are separated, and more specifically, the reference voltage of the write polarity is set to a voltage Vdl-L so that the influence of pushdown is offset. Is also set offset to the higher side.

In the above description, the level of the common signal Vcom2 and the ON signal Von that is in a logically inverted relationship with the common signal Vcom2 are inverted in the period of one frame. It is only for AC driving 140 and 240. For this reason, for example, the common signal Vcom2 and the on signal Von may be inverted in level at a period of 2 frames or more.
Furthermore, although the liquid crystal capacitors 140 and 240 are in a normally black mode, they may be in a normally white mode that is bright when no voltage is applied.
Further, the electro-optical element is not limited to a liquid crystal capacitive element, and can be applied to, for example, an EL (electroluminescence) element. That is, according to the present invention, pixels having gradation corresponding to the voltage or current of the data signal are arranged in the first display area, and the on display or the off display is performed according to the logic level of the data signal held in the memory circuit. The present invention can be applied to all electro-optical devices in which pixels are arranged in the second display area.

Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 13 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 10 according to the embodiment.
As shown in this figure, the cellular phone 1200 includes a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206, and the first display area 100 and the second display area 200 described above are used as display surfaces. It is Note that components of the electro-optical device 10 other than the first display area 100 and the second display area 200 do not appear as appearance.

As an electronic apparatus to which the electro-optical device 10 is applied, in addition to the mobile phone shown in FIG. 13, a digital still camera, a notebook computer, a liquid crystal television, a viewfinder type (
Or a monitor direct view type video recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a videophone, a POS terminal, a device equipped with a touch panel, and the like. And as a display device for these various electronic devices,
Needless to say, the above-described electro-optical device 1 is applicable. In any electronic device, the electro-optical device 10 can benefit from low power consumption.

1 is a diagram illustrating an electrical configuration of an electro-optical device according to an embodiment of the invention. FIG. It is a top view which shows the structure of the same electro-optical apparatus. 3 is a diagram showing pixels in first and second display areas of the same electro-optical device. FIG. It is a figure which shows the structure of the Y driver in the same electro-optical apparatus. It is a figure which shows operation | movement of the shift register in the Y driver. It is a figure which shows the structure of X driver in the same electro-optical apparatus. FIG. 11 is a diagram illustrating a display operation of the first display area in the same electro-optical device. FIG. 11 is a diagram illustrating a display operation of the first display area in the same electro-optical device. FIG. 10 is a diagram showing a display operation of a second display area in the same electro-optical device. FIG. 10 is a diagram showing a display operation of a second display area in the same electro-optical device. FIG. 6 is a diagram illustrating an operation in a partial display mode in the same electro-optical device. It is a figure which shows the principal part structure of the display panel which concerns on the application example of this invention. It is a figure which shows the structure of the mobile telephone to which the electro-optical apparatus which concerns on embodiment is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 30 ... Y driver, 40 ... X driver, 50 ... Demultiplexer,
DESCRIPTION OF SYMBOLS 100 ... 1st display area, 105 ... Liquid crystal, 108 ... 1st common electrode, 110 ... Subpixel, 11
2 ... scanning line, 114 ... data line, 116 ... TFT, 118 ... pixel electrode, 140 ... liquid crystal capacitor, 200 ... second display area, 208 ... second common electrode, 210 ... pixel, 212 ... row selection line,
214 ... bit line, 215 ... inverted bit line, 218 ... pixel electrode, 220 ... memory circuit, 2
30 ... selection circuit, 240 ... liquid crystal capacity, 1200 ... mobile phone

Claims (10)

The first display area is provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines, each of which corresponds to a level corresponding to a data signal supplied to the data line when the scanning line is selected. A plurality of first pixels that form a key;
The second display area is provided corresponding to the intersection of a plurality of row selection lines and a plurality of bit lines corresponding to a part of the plurality of data lines, each having a memory circuit for holding one bit. And when the one-bit logic level held in the memory circuit is one, it is turned on,
A plurality of second pixels that are turned off when the logic level is the other;
A scanning line driving circuit for selecting the scanning line and the row selection line, wherein a predetermined first
A scanning line driving circuit that selects at least the plurality of scanning lines when in the display mode and does not select at least the plurality of scanning lines when in the predetermined second display mode;
In the case of the first display mode, a data signal corresponding to the gradation of the pixel corresponding to the selected scanning line is output to the data line,
In the second display mode, a data line driving circuit for outputting a data signal designating on display or off display of the pixel corresponding to the selected row selection line to the data line corresponding to the bit line;
An electro-optical device comprising: The data line driving circuit includes:
A D / A conversion circuit for converting data specifying the gradation of the pixel corresponding to the selected scanning line into a voltage corresponding to the gradation;
The electro-optical device according to claim 1, wherein in the second display mode, the conversion operation by the D / A conversion circuit is stopped. A light source for irradiating the second display area with light;
The electro-optical device according to claim 1, wherein irradiation with the light source is stopped in the second display mode. The first pixel has a switching element that is turned on when a logic level when the scanning line is selected is one or the other,
The memory circuit in the second pixel holds the logic level of the data signal supplied to the bit line when the logic level when the row selection line is selected is one or the other.
A logic amplitude that is a difference between one and the other of the logic levels of the scanning line is larger than a logic amplitude that is a difference between one and the other of the logic levels of the row selection line,
The electro-optical device according to claim 1. The second pixel is
When the one-bit logic level held in the memory circuit is one, the off signal having the same logic as the common signal is selected, and when the one-bit logic level held is the other, the off-state is selected. A selection circuit that selects an ON signal that is in a logically inverted relationship with the signal;
A pixel electrode to which an on signal or an off signal selected by the selection circuit is applied;
The electro-optical device according to claim 4, wherein the pixel electrode is opposed to a common electrode to which a common signal having the same logic as the off signal is applied. The common signal, the on signal, and the off signal have a low amplitude width that is the same as the logical amplitude of the row selection line.
The electro-optical device according to claim 5. The scanning line driving circuit selects a row selection line corresponding to a second pixel in which 1-bit data held in the memory circuit is rewritten in the second display mode;
The electro-optical device according to claim 1. The plurality of data lines are blocked every two or more predetermined number of columns,
The bit lines correspond to one column of data lines belonging to each block,
The data line driving circuit includes:
In the first display mode, a predetermined number of data lines belonging to each block are sequentially selected, while in the second display mode, among the predetermined number of data lines belonging to each block, the bit lines are selected. A demultiplexer for selecting a corresponding data line;
The electro-optical device according to claim 1. The first display area is provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines, each of which corresponds to a level corresponding to a data signal supplied to the data line when the scanning line is selected. A plurality of first pixels that form a key;
A second display area is provided corresponding to the intersection of a plurality of row selection lines and a plurality of bit lines, each having a memory circuit that holds 1 bit, and 1 bit held in the memory circuit A plurality of second pixels that are turned on when one of the logic levels is on, and turned off when the logic level is the other,
A decoder provided in a part of the plurality of data lines and supplying a logic signal supplied to the data line to a bit line of a specified column that is a part of the plurality of bit lines; ,
A scanning line driving circuit for selecting the scanning line and the row selection line, wherein a predetermined first
A scanning line driving circuit that selects at least the plurality of scanning lines when in the display mode and does not select at least the plurality of scanning lines when in the predetermined second display mode;
In the case of the first display mode, a data signal corresponding to the gradation of the pixel corresponding to the selected scanning line is output to the data line,
In the second display mode, a data line driving circuit for outputting a data signal designating on display or off display of a pixel corresponding to the selected row selection line to the data line provided with the decoder;
An electro-optical device comprising: An electronic apparatus comprising the electro-optical device according to claim 1.

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