KR101777868B1 - Liquid crystal display and low power driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a low-power driving method thereof, and more particularly, to a liquid crystal display device and a low-power driving method thereof, in which only a data line existing in a screen block in which a standby mode image is displayed, ; Supplying a gate pulse only to gate lines existing in a screen block in which the standby mode image is displayed, among the screen blocks divided on the screen of the liquid crystal display panel in the standby mode; And a step of lighting only the light source for the area in which the standby mode image is displayed among the light sources of the backlight unit in the standby mode and turning off the other light sources, And changing the position of the data line to which the data voltage of the standby mode image is supplied.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display (LCD)

The present invention relates to a liquid crystal display device and a low-power driving method thereof.

Various flat panel displays (FPDs) have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes (CRTs). Such a flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) And a light emitting device (Electroluminescence Device).

An LCD used as a display device of a mobile information terminal must be low-power driven in a standby mode. The standby mode is also known as a DLP (Dimmed Low Power) mode. In the LCD of a mobile information terminal, approximately seven LEDs (Light Emitting Diodes) are used as a light source of a backlight unit (BLU).

In general, the LCD of a mobile information terminal has a target luminance of about 500 nit at a normal drive, and in this case, it is driven with a current of about 20 mA and a voltage of about 3.2 V. In the normal drive mode, the power consumption of the backlight unit is about 448 mW.

The standby mode power consumption of the mobile information terminal LCD is aimed at 20mW. However, it is difficult to reduce the power consumption of the driving circuit for driving the data lines and the gate lines of the LCD in the standby mode, and the power consumption of the backlight unit can not be significantly lowered merely by reducing the current of the LED (Light Emitting Diode) . Therefore, it is difficult for the current LCD of the mobile information terminal to reduce the power consumption to below the target value in the standby mode. Due to the power consumption problem in the standby mode, mobile information terminals such as smart phones are being driven with minimum power without displaying any data on the LCD screen in the standby mode.

The present invention provides a liquid crystal display capable of lowering power consumption in a standby mode and a low power driving method thereof.

The liquid crystal display of the present invention includes a liquid crystal display device including data lines to which a data voltage is supplied, gate lines that are crossed with the data lines and supplied with gate pulses synchronized with the data voltages, Display panel; A backlight unit for emitting light of the liquid crystal display panel; A timing control and source driving circuit for supplying a data voltage of the standby mode image only to data lines existing in a screen block in which a standby mode image is displayed among the data lines of the liquid crystal display panel; A gate driving circuit for supplying the gate pulse only to gate lines existing in a screen block in which the standby mode image is displayed, among the screen blocks divided in the screen of the liquid crystal display panel in the standby mode; And a light source driving circuit for turning on only the light source of the standby mode image in which the standby mode image is displayed and for turning off the other light sources from the light sources of the backlight unit in the standby mode, Mode image by changing the display position of the standby mode image at predetermined time intervals to change the data lines to which the data voltage of the standby mode image is supplied.

The method comprising: supplying a data voltage of the standby mode image only to data lines existing in a screen block in which a standby mode image is displayed among data lines of the liquid crystal display panel; Supplying the gate pulse only to gate lines existing in a screen block in which the standby mode image is displayed, among the screen blocks divided in the screen of the liquid crystal display panel in the standby mode; And a step of turning on only a light source that is responsible for a region in which the standby mode image is displayed among the light sources of the backlight unit in the standby mode and turning off the other light sources, Changing the display position to change the data lines to which the data voltage of the standby mode image is supplied.

The present invention selectively drives one or a plurality of light sources from among a plurality of light sources, sequentially illuminates a plurality of light sources, thereby maintaining the lifetime of the light sources at the same level and moving the display position of the standby mode image. As a result, the present invention can display the standby mode image on the LCD screen and minimize the power consumption of the LCD driving circuit and the backlight. Further, according to the present invention, only one of the light sources is turned on in the standby mode, and the lighting source is periodically changed, thereby preventing screen unevenness due to the difference in life time of the light sources depending on the usage time and shifting the standby mode image, have.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
2A to 2C are diagrams illustrating a standby mode operation in the liquid crystal display device according to the embodiment of the present invention.
3 is a detailed circuit diagram of the GIP circuit shown in FIG.
4 is a waveform diagram showing clock signals input to the GIP circuit shown in FIG.
5 is a waveform diagram showing input / output signals of the first GIP circuit.
6 is a view illustrating a parallel connection structure of the light source driving circuit and light sources shown in FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Referring to FIG. 1, a stereoscopic image display apparatus according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, a display panel driving circuit, a light source 310, and a light source driving circuit 300.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 100 includes pixels arranged in a matrix form by an intersection structure of the data lines DL and the gate lines GL. The TFT array substrate of the liquid crystal display panel 100 includes data lines, gate lines intersecting with data lines, TFTs formed at intersections of data lines and gate lines, pixel electrodes of liquid crystal cells, Storage capacitors (Cst), and the like. The liquid crystal of the pixels is driven by the electric field between the common electrode and the pixel electrode connected to the TFT. The color filter array substrate of the liquid crystal display panel 100 includes a black matrix, a color filter, a common electrode, and the like. An alignment film is formed on each of the upper glass substrate and the lower glass substrate to attach a polarizing film and to set a pre-tilt angle of the liquid crystal.

The liquid crystal display of the present invention can be applied to a vertical electric field driving system such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode or a horizontal electric field driving system such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Can be implemented.

The display panel driving circuit includes a timing control and source driving IC 110, a gate driving circuit, and the like.

The timing control and source driving IC 110 converts digital video data input from the host system 200 into positive / negative data voltages and supplies the data voltages to the data lines DL. In the mobile information terminal, the host system 200 may be a main board of a phone system. The timing control and source driver IC 110 generates a gate timing control signal for controlling the operation timing of the gate drive circuit so that a gate pulse synchronized with the data voltage can be output from the gate drive circuit. The gate timing control signal includes a start pulse (VST) and clock signals (CLK). The timing control and source driver IC 110 supplies the light source control circuit 300 with light source control data for controlling the lighting timing and brightness of the light sources 310 to control the light source driving circuit 300.

The gate driving circuit includes a GIP circuit 120 formed directly on a substrate of the liquid crystal display panel 100 by a GIP (Gate In Panel) process. The GIP circuit 120 includes a shift register that outputs a gate pulse (or a scan pulse) synchronized with a data voltage in response to a start pulse VST and clock signals CLK.

The light source driving circuit 300 controls each of the light sources 310 to turn on and off under the control of the timing control and the source driving IC 110, and adjusts the brightness thereof. Each of the light sources 310 may be implemented as an LED.

In the normal driving mode, the host system 200 transmits a normal driving mode switching command to the timing control and source driving IC 110. [ The timing control and source driver IC 110 displays the positive / negative data voltages input from the host system 200 on the data lines DL in response to the normal drive mode switching command. The GIP circuit 120 sequentially supplies a gate pulse synchronized with the data voltage to all the gate lines GL in the normal driving mode. The light source driving circuit 300 turns on all the light sources 310 in the normal driving mode and adjusts the brightness of the light sources 310 according to the timing control and the dimming value input from the source driving IC 110 do. The timing control and source driver IC 110 determines the dimming value according to the analysis result of the input image and adjusts the brightness of the light sources 310 according to the pulse width modulation (PWM) according to the dimming value.

In the standby mode, the host system 200 transmits a standby mode switching command to the timing control and source driving IC 110. [ The timing control and source driver IC 110 partially drives the GIP circuit 120 in the standby mode in response to the standby mode switching command and also controls the light source 310 to turn on any one of the light sources 310, Is changed according to a preset timing sequence to minimize power consumption. In addition, the timing control and source driver IC 110 responds to a standby mode switching command to output data in which data voltages in a screen block in which a standby mode image is displayed in a standby mode, that is, Supplies only the data voltages to the lines and not the other data lines.

In the standby mode, the host system 200 can supply the timing control and source driving IC 110 with data (hereinafter referred to as "standby mode image") preset in the standby mode image. The timing control and source driver IC 110 supplies the data voltage of the standby mode image input from the host system 200 to the data lines DL existing in the backlight lighting region in the standby mode, . Thus, the timing control and source driver IC 110 supplies the data voltages of the standby mode image to only some of the data lines. The timing control and source driver IC 110 may supply only the standby mode image data set in the internal memory to the data lines DL existing in the backlight lighting region when the standby mode image is not inputted from the host system 200 have.

In the standby mode, the GIP circuit 120 outputs a gate pulse only to gate lines for selecting pixels to which a standby mode image is written, and does not output gate pulses to other gate lines. For this purpose, the GIP circuit 120 may be divided into a plurality of screen blocks divided on the display screen so that gate pulses can be supplied only to the gate lines GL existing in the area where the standby mode image is displayed. In the standby mode, the divided GIP circuit 120 shares the start pulse VST as shown in FIGS. 3 and 4, and the clock signals CLK can be separately supplied.

2A to 2C are diagrams illustrating a standby mode operation in the liquid crystal display device according to the embodiment of the present invention.

2A to 2C, the standby mode image data may be set to a minimum amount of data indicating a date, a time, and the like, but is not limited thereto. For example, the standby mode image data may be set with various data such as a user name, a motto, today's fortune, or the like, which is preset or selected by the user.

The timing control and source driver IC 110 supplies the data voltage of the standby mode image only to the data lines that are responsible for the area in which the standby mode image is displayed. The timing control and source driver IC 110 lights only one light source 310 that illuminates the area of the light sources 310 so that the area where the standby mode image is displayed is lit. In the standby mode, only one light source 310 is lit, so that the power consumption of the backlight unit is minimized. In order to increase the recognition rate of the standby mode image and prevent the afterimage of the liquid crystal, the timing control and source driver IC 110 shifts the standby mode image at predetermined time intervals on the screen as shown in FIGS. 2A to 2C, The other light source 310 which lights up the previously illuminated light source 310 to illuminate the shifted standby mode image screen is turned on.

The display screen of the liquid crystal display panel 100 is dividedly driven into a plurality of screens A to E as shown in Figs. 2A to 2C in the standby mode. The GIP circuit 120 includes a first GIP circuit for sequentially supplying gate pulses to the gate lines GL present on the screen A in the standby mode, a gate driver for sequentially applying gate pulses to the gate lines GL existing on the screen B, A third GIP circuit for sequentially supplying gate pulses to the gate lines GL present on the screen C, and a second GIP circuit for sequentially supplying gate pulses to the gate lines GL existing on the screen D And a fifth GIP circuit for sequentially supplying gate pulses to the gate lines GL present on the screen E. [

In FIGS. 2A to 2C, it is assumed that the light sources 310 are arranged in the order of the first light source, the second light source, and the seventh light source from the left.

As shown in FIG. 2A, the timing control and source driver IC 110 supplies the data voltages to the pixels included in the left portion of the screen C region through the data lines DL existing in the left portion of the screen C region in the standby mode Standby mode image data can be written. In the standby mode of FIG. 2A, only the second light source 310 that illuminates the left part of the screen C is turned on and the other light sources are turned off. In the standby mode of FIG. 2A, only the third GIP circuit generates an output under the control of the timing control and source driving IC 110, and gate pulses are sequentially supplied to the gate lines existing in the screen C region.

As shown in FIG. 2B, the timing control and source driver IC 110 supplies the data voltage to the pixels included in the central portion of the screen C region through the data lines DL existing in the central portion of the screen C region in the standby mode Standby mode image data can be written. In the standby mode of FIG. 2B, only the fourth light source 310 that illuminates the center portion of the screen C is turned on and the other light sources are turned off. In the standby mode of FIG. 2B, only the third GIP circuit generates an output under the control of the timing control and the source driver IC 110, and gate pulses are sequentially supplied to the gate lines existing in the screen C region.

2C, the timing control and source driver IC 110 supplies the data voltage to the pixels included in the central portion of the screen C region through the data lines DL existing in the right portion of the screen C region in the standby mode Standby mode image data can be written. In the standby mode of FIG. 2C, only the sixth light source 310 for illuminating the right portion of the screen C is turned on and the other light sources are turned off. In the standby mode of FIG. 2C, only the third GIP circuit generates an output under the control of the timing control and source driving IC 110, and gate pulses are sequentially supplied to the gate lines existing in the screen C region.

The number of light sources 310 is not limited to one. For example, the light sources 310 may be lit one by one or two or six at a time, as shown in FIGS. 2A to 2C.

The standby mode image is not limited to the shift direction as shown in Figs. 2A to 2C. The standby mode image can be shifted left, right, up and down directions of the screen. Therefore, the driving timing of the first to fifth GIP circuits divided by the GIP circuit 120 can be changed in synchronization with the shift timing of the standby mode image.

3 is a circuit diagram showing the GIP circuit 120 in detail. 4 is a waveform diagram showing clock signals (A to E ') input to the GIP circuit 120. As shown in FIG.

) 노드의 전압에 응답하여 출력단자의 전압을 하강시키는 제1 및 제2 풀다운 트랜지스터(T2, T3), 및 Q 노드와 Q bar 노드의 전압을 제어하는 스위치 제어회로(도시하지 않음)를 포함한다. Referring to Figures 3 and 4, the shift register of the GIP circuit 120 includes stages that are connected in a dependent fashion. Each of the stages includes a pull-up transistor (T1), Q bar (

Down transistors T2 and T3 for lowering the voltage of the output terminal in response to the voltage of the node Q, and a switch control circuit (not shown) for controlling the voltages of the Q node and the Q bar node .

In each of the first to fifth GIP circuits divided by the GIP circuit 120, the start pulse VST is input to the start pulse input terminal of the first stage. In the first to fifth GIP circuits, the output terminal (or carry signal) of the previous stage, for example, the n-2 stage, is input to the start pulse input terminal of the n-th stage (n is a positive integer of 2 or more). The output of the next stage is input to the reset terminal of the stages. For example, the output of the (n + 2) -th stage is input to the reset terminal of the n-th stage. Either one of the clock signals (A-E ') is input to the clock signal input terminal of the stage in each of the first to fifth GIP circuits.

In each of the stages, the gate electrode of the pull-up transistor T1 is connected to the Q node, and the source electrode is connected to the gate line through the output terminal of the stage. One of the clock signals A to E 'is supplied to the drain electrode of the pull-up transistor T1. In each of the stages, the gate electrode of the first and second pull down transistors T2 and T3 is connected to the Q bar node, and the drain electrode is connected to the gate line through the output terminal of the stage. (VSS or GND) is supplied to the source electrodes of the first and second pull-down transistors T2 and T3.

The Q node is charged when the start pulse or the output of the previous stage is input to the start pulse input terminal of the stage to turn on the pull-up transistor T1. The pull-up transistor Tl is connected to the gate line GL when the voltage of the node Q rises sufficiently above its own write voltage and the clock signal AE 'inputted to its drain terminal is a high logic voltage. And raises the output terminal voltage to the gate high voltage (VGH). The Qbar node is charged when the output of the next stage is input to the reset terminal of the stage to turn on the pull down transistors T2 and T3. The pull down transistors T2 and T3 drop the output terminal voltage of the stage connected to the gate line GL to the gate low voltage VGL when the voltage of the Q bar node sufficiently rises above its own Moon voltage. Thus, each of the stages outputs a gate pulse to the gate line that swings between the gate high voltage VGH and the gate low voltage VGL when the clock signal AE 'is input.

The clock signals (A-E ') input to the GIP circuit 120 are separated from the first to fifth GIP circuits in order to drive the screen in the standby mode. The first GIP circuit sequentially supplies gate pulses to the gate lines GL existing in the screen A in response to the clock signal A pair (A, A '). The second GIP circuit sequentially supplies gate pulses to the gate lines GL existing in the screen B in response to the pair of clock signal B (B, B '). The third GIP circuit sequentially supplies gate pulses to the gate lines GL existing on the screen C in response to the clock signal C pair (C, C '). The fourth GIP circuit sequentially supplies the gate pulses to the gate lines GL existing in the screen D in response to the clock signal D pair (D, D '). The fifth GIP circuit sequentially supplies the gate pulses to the gate lines GL existing in the screen E in response to the clock signal E pair (E, E ').

In the normal drive mode, the timing control and source driver IC 110 generates all of the clock signals AE '. Accordingly, the GIP circuit 120 sequentially supplies gate pulses to the gate lines GL of the entire screen in the normal mode.

The timing control and source driver IC 110 generates only a part of the clock signals in order to drive only a part of the GIP circuit in charge of the screen area in which the standby mode image is displayed in the standby mode. In the case of FIGS. 2A to 2C, the timing control and source driver IC 110 outputs the clock signal C pair (C, C ') and the remaining clock signals A-A', B-B ' , E-E '). Therefore, in the case of FIGS. 2A to 2C, only the third GIP circuit in charge of the screen C in the GIP circuit 120 outputs the gate pulse and the first, second, fourth and fifth GIP circuits generate the output none.

The timing control and source driver IC 110 generates the clock signal A pair (A-A ') during the scanning period of the screen A to drive the first GIP circuit. The clock signal A 'is delayed in phase by 180 ° relative to the clock signal A and is generated in the opposite phase of the clock signal A. The timing control and source driver IC 110 generates a pair of clock signals B (B-B ') during the scanning period of the screen B to drive the second GIP circuit. The clock signal B 'is delayed in phase by 180 ° relative to the clock signal B and is generated in the reverse phase of the clock signal B. The timing control and source driver IC 110 generates a pair of clock signals C (C-C ') during the scanning period of the screen C to drive the third GIP circuit. The clock signal C 'is delayed in phase by 180 ° relative to the clock signal C and is generated in the reverse phase of the clock signal C. The timing control and source driver IC 110 generates a clock signal D pair (D-D ') during the scanning period of the screen D to drive the fourth GIP circuit. The clock signal D 'is delayed in phase by 180 ° relative to the clock signal D and is generated in the opposite phase of the clock signal D. The timing control and source driver IC 110 generates a clock signal E pair (E-E ') during the scanning period of the screen E to drive the fifth GIP circuit. The clock signal E 'is delayed in phase by 180 ° relative to the clock signal E and is generated in the opposite phase of the clock signal E. The timing control and source driver IC 110 receives the clock signal A pair A-A ', the clock signal B pair B-B', the clock signal C pair C-C ', the clock signal D And outputs the clock signals A-E 'in the order of the pair (D-D') and the pair of clock signals E (E-E '). Each of the clock signals A-E 'is supplied to a clock signal input terminal of the GIP circuit through a separate wiring. The timing control and source driver IC 110 are connected to a pair of clock signal A (A-A '), a pair of clock signals B (B-B'), a pair of clock signals C (C-C ' Only the clock signal pair of some GIP circuits responsible for the screen block in which the standby mode image is displayed among the clock signal E-D 'and the clock signal E pair E-E' is output.

In the standby mode, an example in which the screen is divided into five blocks and the clock signals are divided into five pairs so that the GIP circuit 120 is dividedly driven in five has been described, but the present invention is not limited thereto. For example, in the standby mode, the screen is divided into N blocks (N is a positive integer equal to or larger than 2) blocks, and the clock signals are divided into N pairs so that the GIP circuit 120 can be dividedly driven into N blocks.

5 is a waveform diagram showing input / output signals of the first GIP circuit for driving the gate lines of the screen A. In FIG.

5, the first GIP circuit sequentially shifts the gate pulses G1 to G3 to the gate lines existing on the screen A by shifting the start pulse VST for each pair of clock signal A (A-A ') do.

6 is a view showing a parallel connection structure of the light source driving circuit 300 and the light sources 310 shown in FIG.

Referring to FIG. 6, the host system supplies image data to the timing control and source driver IC 110, and supplies the light source control circuit (C _BL ) synchronized with the image data to the light source driving circuit 300.

The light source driving circuit 300 is connected to the light sources 310 in parallel. The light source driving circuit 300 applies the light source driving voltage to the anode of the light sources under the control of the host system 200 in the normal driving mode and connects the cathode of all the light sources 310 to the ground voltage source GND, 310). In contrast, the light source driving circuit 300 applies a light source driving voltage to the anode of all the light sources 310 under the control of the host system 200 in the stand-by mode and supplies the cathode of one or more of the light sources 310, And connected to a voltage source (GND) to light only some light sources. In the standby mode, the light source 310 that was previously turned on at predetermined time intervals is turned off as shown in FIGS. 2A to 2C, and the other light source 310 is turned on in synchronization with the shift timing of the standby mode image.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

100: liquid crystal display panel 110: timing control and source driving IC
120: GIP circuit 200:
310: Light source

Claims (9)

A liquid crystal display panel including data lines supplied with a data voltage, gate lines crossing the data lines and supplied with gate pulses synchronized with the data voltages, and liquid crystal cells arranged in a matrix form;
A backlight unit for emitting light of the liquid crystal display panel;
A timing control and source driving circuit for supplying a data voltage of the standby mode image only to data lines existing in a screen block in which a standby mode image is displayed among the data lines of the liquid crystal display panel;
A gate driving circuit for supplying the gate pulse only to gate lines existing in a screen block in which the standby mode image is displayed, among the screen blocks divided in the screen of the liquid crystal display panel in the standby mode; And
And a light source driving circuit for lighting only the light source of the light source of the backlight unit and for turning off the other light sources in the standby mode, wherein the timing control and the source driving circuit are operated in the standby mode And changing the display position of the standby mode image at predetermined time intervals to change the data lines supplied with the data voltage of the standby mode image.
The method according to claim 1,
Wherein the gate driving circuit sequentially supplies the gate pulses to all the gate lines formed on the screen of the liquid crystal display panel in the normal driving mode,
Wherein the light source driving circuit lights all the light sources of the backlight unit in the normal driving mode.
The method according to claim 1,
In the liquid crystal display panel,
In the standby mode, a screen is divided into N blocks (N is a positive integer equal to or larger than 2)
The gate drive circuit includes:
And N GIP circuits that share the start pulse and are divided and driven by receiving N pairs of clock signal pairs,
The timing control and the source driving circuit may include:
And supplying the start pulse and the clock signal pairs to the gate driving circuit. In the standby mode, a clock signal pair input to a GIP circuit connected to gate lines in a screen block in which the standby mode image is displayed, To the liquid crystal display panel.
The method according to claim 1,
The light source driving circuit includes:
Wherein the light source previously turned on in the standby mode is turned off and another light source is turned on in synchronization with the display position change timing of the standby mode image.
5. The method of claim 4,
The gate drive circuit includes:
Wherein when the display position of the standby mode image is changed, the gate pulse is supplied to gate lines existing in another screen block in which the standby mode image is displayed.
A liquid crystal display panel including data lines to which data voltages are supplied, gate lines crossing the data lines and supplied with gate pulses synchronized with the data voltages, and liquid crystal cells arranged in a matrix form, A low-power driving method of a liquid crystal display device including a backlight unit for irradiating light of a panel,
Supplying a data voltage of the standby mode image only to data lines existing in a screen block in which a standby mode image is displayed among data lines of the liquid crystal display panel;
Supplying the gate pulse only to gate lines existing in a screen block in which the standby mode image is displayed, among the screen blocks divided in the screen of the liquid crystal display panel in the standby mode; And
And displaying the standby mode image at a predetermined time interval in the standby mode, and lighting only the light source of the standby mode in which the standby mode image is displayed, And changing data lines to which the data voltage of the standby mode image is supplied by changing the position of the data lines.
The method according to claim 6,
Sequentially supplying the gate pulses to all the gate lines formed on the screen of the liquid crystal display panel in the normal driving mode; And
And lighting all the light sources of the backlight unit in the normal driving mode.
The method according to claim 6,
Further comprising the step of turning off the light source that was previously turned on in the standby mode and lighting another light source in synchronization with the display position change timing of the standby mode image.
9. The method of claim 8,
Further comprising the step of supplying the gate pulse to gate lines existing in another screen block in which the standby mode image is displayed when the display position of the standby mode image is changed .

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