KR101829460B1 - Liquid Crystal Display Device and Driving Method thereof - Google Patents

Abstract

Embodiments of the present invention may include: data lines wired in a first direction; Gate lines wired in a second direction to intersect the data lines; Subpixels defined by data lines and gate lines; And common voltage lines arranged in the second direction adjacent to the gate lines and having first and second common voltage lines arranged alternately for each gate line, wherein the first common voltage supplied to the first common voltage line The second common voltage supplied to the second common voltage line has a different voltage level and the supply point of time of the first common voltage and the second common voltage are different from each other.

Description

[0001] The present invention relates to a liquid crystal display device and a driving method thereof,

An embodiment of the present invention relates to a liquid crystal display and a driving method thereof.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, a flat panel display (FPD) such as a liquid crystal display (LCD), an organic light emitting diode (OLED), and a plasma display panel (PDP) Usage is increasing. Among them, liquid crystal display devices capable of realizing high resolution and capable of not only miniaturization but also enlargement are widely used.

The liquid crystal display includes a transistor substrate formed with transistors, storage capacitors, pixel electrodes, and the like, and a liquid crystal layer disposed between the color filter substrate and the color filter substrate on which the color filter and the black matrix are formed. The liquid crystal display displays images in such a manner that light incident from the backlight unit is emitted by adjusting the arrangement direction of the electric field liquid crystal layer formed on the pixel electrode, the transistor substrate, or the common electrode formed on the color filter substrate.

The liquid crystal display device functions as a voltage for driving the liquid crystal, the difference between the data voltage supplied from the data driver and the common voltage supplied from the power supply. Conventionally, a common voltage of the same level is supplied to a liquid crystal panel, and a liquid crystal cell is driven in a column inversion manner by alternately supplying a data voltage lower than a common voltage and a data voltage higher than a common voltage.

However, in the version driving method of the conventional column, the same common voltage is applied to the panel, and the data voltage and the data voltage, which are lower and lower than the common voltage, are alternately charged and discharged in units of columns. In the version driving method of the conventional column, the range of the data voltage when charging the positive voltage is higher than the voltage range when charging the negative voltage. Since the power consumption, which is power consumption, increases in proportion to the square of the voltage, the higher the voltage, the higher the power consumption.

In contrast, the conventional line-in version driving method charges one line of the panel with the same positive polarity and charges the next line with the negative polarity. Therefore, in the conventional line-inversion driving method, since the amplitude of the voltage for realizing a bright screen is large and the charging polarity is changed for each line, the frequency depending on the voltage fluctuation is also very large.

As described above, there is a problem that power consumption increases as the number of gate lines increases as the number of gate lines increases. This is because the power consumption is increased because a constant common voltage is used. Therefore, a method for improving the power consumption is required in the version driving method and the line inversion driving method, which are the conventional columns.

According to an embodiment of the present invention for solving the problems of the background art described above, since the swing range of the data voltage can be reduced by the common voltage having the positive polarity and the negative polarity, which are alternately inputted periodically, And a method of driving the liquid crystal display device.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device including data lines arranged in a first direction; Gate lines wired in a second direction to intersect the data lines; Subpixels defined by data lines and gate lines; And common voltage lines arranged in the second direction adjacent to the gate lines and having first and second common voltage lines arranged alternately for each gate line, wherein the first common voltage supplied to the first common voltage line The second common voltage supplied to the second common voltage line has a different voltage level and the supply point of time of the first common voltage and the second common voltage are different from each other.

The time point when the first common voltage is supplied may precede the time point when the second common voltage is supplied and the second common voltage may be synchronized with the gate signal supplied to the gate line wired to the corresponding line.

The first common voltage alternately swings in the order of the negative polarity and the positive polarity level, the second common voltage alternately swings in the order of the positive polarity level and the negative polarity level, and the first and second common voltages are alternately swung have.

The first common voltage alternately swings in the order of the negative polarity level and the positive polarity level with reference to the reference voltage level, and the second common voltage may alternately swing in the order of the positive polarity level and the negative polarity level with reference to the reference voltage level.

A positive polarity level and a positive polarity level of the first common voltage and a positive polarity level and a negative polarity level of the second common voltage are the same as those of the two gate signals supplied to the gate line wired to the corresponding line and the gate line wired to the next line And then maintained at the reference voltage level.

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In the subpixel, the pixel electrode and the common electrode may be formed in the thin film transistor substrate.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display, comprising: supplying a data signal to data lines wired in a first direction; A gate signal supplying step of supplying gate signals to gate lines wired in a second direction so as to intersect the data lines; A first common voltage having different voltage levels in the common voltage lines including first and second common voltage lines arranged in the second direction adjacent to the gate lines and alternately arranged in each gate line, And a common voltage supplying step of supplying a common voltage with different supply time points of the first common voltage and the second common voltage.

In the common voltage supply step, the first common voltage may be supplied before the second common voltage is supplied, and the second common voltage may be synchronized with the gate signal supplied to the gate line wired to the corresponding line.

In the common voltage supply step, the first common voltage is alternately swung in the order of the negative polarity and the positive polarity, and the second common voltage is alternately swung in the order of the positive polarity level and the negative polarity. So as to swing alternately.

In the common voltage supply step, the first common voltage is alternately swung in the order of the negative polarity level and the positive polarity level with reference to the reference voltage level, and the second common voltage is alternately switched between the positive polarity level and the negative polarity level You can swing.

A positive polarity level and a positive polarity level of the first common voltage and a positive polarity level and a negative polarity level of the second common voltage are the same as those of the two gate signals supplied to the gate line wired to the corresponding line and the gate line wired to the next line And then maintained at the reference voltage level.

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Embodiments of the present invention provide a liquid crystal display device and a driving method thereof that can reduce the swing range of a data voltage by a common voltage of a positive polarity and a negative polarity that are alternately input at regular intervals, . In addition, the embodiment of the present invention has the effect of improving the display quality by suppressing the change of the pixel voltage according to the common voltage change after charging since the common voltage is simultaneously input in synchronization with the gate signal in addition to the data voltage.

1 is a block diagram of a liquid crystal display device according to a first embodiment of the present invention;
2 is a configuration diagram of a liquid crystal panel according to a first embodiment of the present invention;
FIG. 3 is a waveform diagram of a signal applied to the sub-pixel shown in FIG. 2 according to the first embodiment of the present invention; FIG.
FIGS. 4 and 5 are diagrams showing charge states by a pixel by a pixel voltage and a common voltage; FIG.
6 is a configuration diagram of a liquid crystal panel according to a second embodiment of the present invention;
FIG. 7 is a waveform diagram of a signal applied to the sub-pixel shown in FIG. 6 according to the second embodiment of the present invention; FIG.
FIG. 8 is a waveform diagram of a signal applied to the sub-pixel shown in FIG. 6 according to the third embodiment of the present invention; FIG.
9 is a diagram for explaining power consumption of a data driver according to a driving method;
10 is a table of power consumption simulation results of panels according to the conventional driving method and the driving method of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

≪ Embodiment 1 >

1 is a block diagram of a liquid crystal display device according to a first embodiment of the present invention.

1, the liquid crystal display according to the first embodiment of the present invention includes a timing control unit TCN, a power supply unit PWR, a common voltage driving unit VcomG, a data driving unit DDRV, a gate driving unit SDRV, , A liquid crystal panel (PNL), and a backlight unit (BLU).

The timing control unit TCN receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable, and a data signal DATA from the outside. The timing controller TCN controls the operation of the data driver DDRV and the gate driver SDRV using a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, Timing. The timing control unit TCN can determine the frame period by counting the data enable signal DE in one horizontal period so that the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync supplied from the outside can be omitted. Typical control signals generated by the timing controller TCN include a gate timing control signal GDC for controlling the operation timing of the gate driver SDRV and a data timing control signal for controlling the operation timing of the data driver DDRV DDC). The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE. The gate start pulse GSP is supplied to a gate drive IC (Integrated Circuit) generating the first gate signal. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The data timing control signal DDC includes source start pulses (Source, Start Pulse, SSP), Source Sampling Clock (SSC), Source Output Enable (SOE), and the like. The source start pulse SSP controls the data sampling start timing of the data driver DDRV. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driver DDRV based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver DDRV. On the other hand, the source start pulse SSP supplied to the data driver DDRV may be omitted depending on the data transfer method.

The power supply unit PWR adjusts the voltage Vin supplied from the system board to generate a driving voltage and supplies the generated driving voltage to the timing control unit TCN, the data driving unit DDRV, the gate driving unit SDRV, and the liquid crystal panel PNL. Or more. The power supply unit PWR generates the gamma voltages GMA0 to GMAn and supplies the generated data to the data driver DDRV and the liquid crystal panel PNL.

The common voltage driver VcomG generates a first common voltage and a second common voltage swinging at different voltage levels and supplies them to the common voltage lines. The common voltage driver VcomG is formed on the liquid crystal panel PNL or outside the liquid crystal panel PNL.

The liquid crystal panel (PNL) is a device for displaying an image. The liquid crystal panel (PNL) includes a liquid crystal layer positioned between a thin film transistor substrate (hereinafter abbreviated as TFT substrate) and a color filter substrate. Data lines, gate lines, common voltage lines, TFTs, storage capacitors, and the like are formed on the TFT substrate, and black matrices, color filters, and the like are formed on the color filter substrate. A polarizing plate is attached to the TFT substrate of the liquid crystal panel (PNL) and the color filter substrate, and an alignment film for setting a pre-tilt angle of the liquid crystal is formed. The liquid crystal panel (PNL) includes sub-pixels defined by data lines and gate lines crossing each other. One subpixel includes a TFT driven by a gate signal supplied through a gate line, a storage capacitor for storing a data signal supplied through a data line as a data voltage, a pixel electrode through which a voltage stored in the storage capacitor is transferred, And a liquid crystal cell driven by a voltage applied to the common electrode and the pixel electrode and the common electrode to which the common voltage is supplied. The liquid crystal panel PNL may be driven by an IPS (In Plane Switching) mode or an FFS (Fringe Field Switching) mode to display an image based on light provided from the backlight unit BLU.

The backlight unit (BLU) provides light to the liquid crystal panel (PNL). The backlight unit BLU includes a light source circuit portion including a direct current power source, light emitting portions, transistors and a drive control portion, and an optical mechanism including a cover bottom, a light guide plate, and an optical sheet. The backlight unit (BLU) may be variously configured as an edge type, a dual type, a direct type, and the like. In the edge type, the light emitting diodes are arranged in a line (or string) shape on one side of the liquid crystal panel PNL. In the dual type, light emitting diodes are arranged in a line (or string) form on both sides of a liquid crystal panel (PNL). In the direct type, light emitting diodes are arranged in a block or matrix form in the lower part of the liquid crystal panel (PNL).

The gate driver SDRV is responsive to the gate timing control signal GDC supplied from the timing controller TCN to switch the gate driver control voltage GDC in accordance with the swing width of the gate drive voltage at which the TFTs of the subpixels SP included in the liquid crystal panel PNL are operable And sequentially generates the gate signal while shifting the level of the signal. The gate driver SDRV supplies the gate signal generated through the gate lines GL to the sub-pixels SP included in the liquid crystal panel PNL.

The data driver DDRV samples and latches the data signal DATA supplied from the timing control unit TCN in response to the data timing control signal DDC supplied from the timing control unit TCN and converts the sampled data signal into data of a parallel data system . The data driver DDRV converts the data signal DATA into a gamma reference voltage when converting into data of a parallel data system. The data driver DDRV supplies the data signal DATA converted through the data lines DL to the sub-pixels SP included in the liquid crystal panel PNL.

Hereinafter, the liquid crystal display device according to the first embodiment of the present invention will be described in more detail.

FIG. 2 is a configuration diagram of a liquid crystal panel according to a first embodiment of the present invention. FIG. 3 is a waveform diagram of a signal applied to the subpixel shown in FIG. 2 according to the first embodiment of the present invention, FIG. 5 is a diagram for showing a charge state by a pixel by a pixel voltage and a common voltage. FIG.

As shown in Fig. 2, data lines D [i] to D [l] wired in the first direction are formed on the liquid crystal panel PNL. Further, gate lines G [i] to G [j] wired in the second direction are formed so as to intersect with the data lines D [i] to D [l]. Further, subpixels (SPo, SPe) defined by the data lines D [i] to D [l] and the gate lines G [i] to G [j] are formed. Also, a pair of first and second common voltage lines Vcom [i1] and Vcom [i2] are arranged for each gate line so as to be in parallel with the gate lines G [i] to G [j] Common voltage lines Vcom [i1] to Vcom [j2] for transferring the common voltage of the level.

Here, a pair of first and second common voltage lines Vcom [i1] and Vcom [i2] are assigned to the I-th gate lines G [i] And a pair of first and second common voltage lines Vcom [j1] and Vcom [j2] are arranged in the first and second gate lines G [j] But they are vertically spaced with respect to the subpixels located in the Jth row (jth ROW).

According to the first embodiment, one of the pair of first and second common voltage lines Vcom [i1] and Vcom [i2] is connected to the odd subpixels SPo and the other is connected to the even subpixels (SPe). Since the pair of first and second common voltage lines Vcom [i1] and Vcom [i2] are vertically spaced from each other with respect to the subpixels, common voltages of different voltage levels are transferred to one gate line The voltage lines are arranged together.
For example, the second common voltage line Vcom [i2] located in the same column as the I-th gate line G [i] is connected to the even-numbered subpixels SPe located in the Ith row (ith ROW) While the first common voltage line Vcom [j2] adjacent thereto is connected to the odd subpixels SPo located at the jth row jth ROW.

Accordingly, the subpixels SPo and SPe receive a common voltage through a common voltage line supplying different voltages even though they are located in the same column. Here, Vcom and Pixel are schematics of a common electrode and a pixel electrode included in the subpixels SPo and SPe, respectively. This is because the pixel electrode and the common electrode are formed in the IPS mode or the FFS mode, But the structure is not limited thereto.

As shown in FIGS. 2 and 3, the pair of first and second common voltage lines Vcom [i1] and Vcom [i2] are connected to the I-th gate line G [i The first common voltage VCOM [i1] and the second common voltage VCOM [i2] of different voltage levels are transferred in synchronization with the gate signal Vgate G [i] The first common voltage VCOM [i1] and the second common voltage VCOM [i2] are swung to positive (+) and negative (-) levels. Here, Vsync is a vertical synchronization signal.

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The first common voltage VCOM [i1] and the second common voltage VCOM [i2] swing to the positive (+) and negative (-) levels and alternate in the frame period. Therefore, the first common voltage Vcom [i1] is synchronized with the I-th gate signal Vgate G [i] during the Nth frame (Frame [n] The first common voltage line Vcom [i1] is synchronized with the I-th gate signal Vgate G [i] during the (N + 1) The first common voltage VCOM [i1] of negative polarity is applied. Similarly, a second common voltage (-) of negative polarity (-) is applied to the second common voltage line Vcom [i2] in synchronization with the I-th gate signal Vgate G [i] The second common voltage line Vcom [i2] is synchronized with the gate signal to the I-th gate signal Vgate G [i] during the (N + 1) the second common voltage VCOM [i2] of positive polarity is applied to the first common voltage VC2 [i2].

3, the first and second common voltages VCOM [i1] and VCOM [i2] swing in the positive polarity (+) and the negative polarity (-), Signal Vgate G [i] at the same time. On the other hand, if the common voltage is swung frame by frame without being synchronized with the gate signal, the following problems may occur.

The voltage of the pixel is maintained at the floating voltage state of Vp1 when the gate signal is turned on and charged to the value of Vp1 and then the gate signal is turned off and when the common voltage is changed, And changes to the voltage Vp1 'of the new pixel along with the change of the common voltage. Since the pixel electrode has a parasitic capacitance with the data line and the gate line in addition to the common electrode Vcom, the pixel electrode has a finer width than that of the common electrode. Therefore, this difference in voltage may be represented by a difference in luminance. In addition, the sustain period of Vp1 'of the voltage changed due to the sustain period of Vp1 of the pixel voltage charged by the on of the gate line and the voltage change of the common electrode has a different value depending on all the gate lines . This may be a factor for varying the luminance per gate line.

However, as in the first embodiment, if the common voltage is applied in synchronism with the gate signal in addition to the data voltage, the above problem does not occur.

Hereinafter, a driving method according to the first embodiment of the present invention will be described.

A data signal supply step of supplying data signals to the data lines D [i] to D [l] wired in the first direction is performed. A gate signal supplying step of supplying gate signals to the gate lines G [i] to G [j] wired in the second direction so as to intersect the data lines D [i] to D [ . Common voltage lines (Vcom [i1], Vcom [i2]) in which a pair of first and second common voltage lines Vcom [i1] and Vcom [i2] are arranged for each gate line so as to be parallel to the gate lines G [i] The first common voltage VCOM [i1] and the second common voltage VCOM [i2] swing at positive (+) and negative (-) levels are supplied to Vcom [i1] to Vcom [ A common voltage supply step is performed.

In the common voltage supply step, the first common voltage VCOM [i1] and the second common voltage VCOM [i2] are supplied in synchronization with the gate signal supplied to the gate line wired to the corresponding line. In the common voltage supply step, the first common voltage VCOM [i1] and the second common voltage VCOM [i2] are swung to the positive (+) and negative (-) levels and alternated frame by frame. In the common voltage supplying step, the first common voltage VCOM [i1] is supplied to the odd subpixels SPo located in the Ith row (ith ROW) and the second common voltage VCOM [i2] Is supplied to the even-numbered subpixel SPe located in the ith row (ith ROW).

It is assumed that a data voltage swinging from 0 V to 5 V according to a gray level is supplied to the pixel electrode and becomes a common voltage swinging at 5 V and 0 V to the common electrode Vcom in the manner described above If a full white is displayed on the screen, the charging aspect as shown in FIGS. 4 and 5 is shown. In FIGS. 4 and 5, only the charge states of the odd-numbered sub-pixels are shown.

Since the data voltage and the common voltage supplied to the pixel electrode and the common electrode Vcom are always input in synchronization with the gate signal as shown in FIG. 5, the charging time of the pixel electrode Pixel is supplied to each gate line In synchronization with the gate signal.

As a comparative example, a conventional column inversion driving method uses a common voltage of 5V, a positive (+) data voltage of 5 to 10V, and a negative data voltage of 0 to 5V. On the other hand, in the driving method of the first embodiment, the common voltage swings alternately in the two common voltages of the positive polarity (+) and the negative polarity (-). Therefore, the data voltage can be set to 0 to 5 V in both the positive polarity (+) and the negative polarity (-), so that the power consumption can be reduced more than in the conventional driving method.

As described above, according to the first embodiment of the present invention, since the swing range of the data voltage can be reduced by the common voltage of the positive polarity and the negative polarity, which are alternately input at regular intervals, the liquid crystal display device and the driving method thereof . In addition, since the first embodiment of the present invention simultaneously inputs the data voltage and the common voltage in synchronization with the gate signal, there is an effect that the display quality can be improved by suppressing the change of the pixel voltage according to the common voltage change after being charged .

≪ Embodiment 2 >

FIG. 6 is a configuration diagram of a liquid crystal panel according to a second embodiment of the present invention, and FIG. 7 is a waveform diagram of a signal applied to the subpixel shown in FIG. 6 according to the second embodiment of the present invention.

As shown in Fig. 6, data lines D [i] to D [l] wired in the first direction are formed on the liquid crystal panel PNL. Gate lines G [i] to G [l] wired in the second direction are formed so as to intersect the data lines D [i] to D [l]. Further, subpixels (SPo, SPe) defined by the data lines D [i] to D [l] and the gate lines G [i] to G [l] are formed. The first and second common voltage lines Vcom (i) to G [i] are wired in the second direction adjacent to the gate lines G [i] to G [ (i, k), Vcom [j, l] are disposed and common voltage lines Vcom [i, k], Vcom [j, l] for transmitting common voltages of different levels are included.

Here, the first common voltage line Vcom [i, k] is disposed in the i-th and k-th gate lines G [i, k] , l] are arranged in the second common voltage line Vcom [j, l]. The supply point of time of the first common voltage supplied to the first common voltage line Vcom [i, k] and the supply point of time of the second common voltage supplied to the second common voltage line Vcom [j, l] Respectively.

According to the second embodiment, the first common voltage line Vcom [i] located in the same column as the I th gate line G [i] is connected to the odd subpixels SPo ) And the odd subpixels (SPo) of the Jth column (jth ROW). The second common voltage line Vcom [j] located in the same column as the Jth gate line G [j] is connected to the even-numbered subpixels SPe of the Jth row jth ROW and the (kth ROW) even-numbered subpixels (SPe).

Accordingly, the subpixels SPo and SPe receive a common voltage through a common voltage line supplying different voltages even though they are located in the same column. Here, Vcom and Pixel are only illustrations of the common electrode and the pixel electrode included in the sub-pixels SPo and SPe, respectively, but their structures are not limited thereto. Here, Vcom and Pixel are schematics of a common electrode and a pixel electrode included in the subpixels SPo and SPe, respectively. This is because the pixel electrode and the common electrode are formed in the IPS mode or the FFS mode, But the structure is not limited thereto.

In the second embodiment, the first common voltage line Vcom [i] located in the same column as the I-th gate line G [i] is connected to the even-numbered sub-pixels SPe as well as the above- The second common voltage line Vcom [j] located in the same column as the J th gate line G [j] may be connected to the odd subpixels SPo.

6 and 7, the first common voltage line Vcom [i] and the second common voltage line Vcom [j] have different first common voltage VCOM [i] And delivers the second common voltage VCOM [j]. Similarly, although not shown in Fig. 7, the first common voltage line Vcom [k] and the second common voltage line Vcom [l] are connected to the first common voltage VCOM [i] (VCOM [k]) corresponding to the first common voltage VCOM [k] and the second common voltage VCOM [j]. The first common voltage VCOM [i] swings alternately in the order of the negative (-) level and the positive (+) level. The second common voltage VCOM [j] And the polarity (-) level. Here, Vsync is a vertical synchronization signal.

The first common voltage VCOM [i] swings alternately in the order of the negative (-) level and positive (+) level for each frame, and the second common voltage VCOM [j] ) Level and the negative (-) level in this order. Therefore, the second common voltage Vcom [j] is applied to the second common voltage line Vcom [j] in synchronization with the Jth gate signal Vgate G [j] during the Nth frame (Frame [n] The second common voltage line Vcom [j] is synchronized with the Jth gate signal Vgate G [j] during the (N + 1) The second common voltage VCOM [j] having a negative (-) level is applied. Similarly, the first common voltage VCOM [i] of negative polarity (-) level is applied to the first common voltage line Vcom [i] synchronously with the I-th gate signal during the Nth frame (Frame [n] (+) Level is applied to the first common voltage line (Vcom [i]) in synchronization with the gate signal to the I-th gate signal during the (N + 1) The common voltage VCOM [i] is applied.

Here, the first common voltage line Vcom [i] is a line located at the previous stage than the second common voltage line Vcom [j]. The supply point of the first common voltage VCOM [i] supplied to the first common voltage line Vcom [i] is the second common voltage VCOM [i] supplied to the second common voltage line Vcom [j] [j]). As described above, by varying the timing at which the common voltage is supplied, the output load of the common voltage driver VcomG can be reduced, so that the power consumption can be reduced.

7, the first common voltage VCOM [i] and the second common voltage VCOM [j] are at the negative (-) level and the positive (+) level or the positive (+ ) Level and the negative (-) level, and are input at different points of time in synchronization with the gate signal supplied to the corresponding line.

Hereinafter, a driving method according to a second embodiment of the present invention will be described.

A data signal supply step of supplying data signals to the data lines D [i] to D [l] wired in the first direction is performed. A gate signal supplying step of supplying gate signals to the gate lines G [i] to G [j] wired in the second direction so as to intersect the data lines D [i] to D [ . The first and second common voltage lines W1 and G [j], which are arranged in the second direction adjacent to the gate lines G [i] to G [j] and alternately arranged for the gate lines G [i] The first common voltage VCOM [i] having different voltage levels in the common voltage lines Vcom [i] and Vcom [j] including the common voltages Vcom [i] and Vcom [j] A common voltage supply step of supplying the voltage VCOM [j] with different supply timings of the first common voltage VCOM [i] and the second common voltage VCOM [j] is performed.

In the common voltage supply step, the first common voltage VCOM [i] is supplied so as to be ahead of the time when the second common voltage VCOM [j] is supplied and the second common voltage VCOM [j] In synchronization with the gate signal supplied to the gate line wired to the gate line. At this time, the first common voltage VCOM [i] may also be supplied in synchronization with the gate signal supplied to the gate line wired to the corresponding line.

In the common voltage supply step, the first common voltage VCOM [i] is alternately swung in the negative (-) level and the positive (+) level order and the second common voltage VCOM [j] ) Level and the negative polarity (-) level. Then, the first and second common voltages VCOM [i] and VCOM [j] are swung alternately for each frame.

However, in the common voltage supply step, the first common voltage VCOM [i] is connected to the upper subpixel of the ith row (ith ROW) and the lower subpixel of the jth column (jth ROW) located on the odd line To be supplied to the first common voltage line Vcom [i]. The second common voltage VCOM [j] is connected to the second common voltage line connected to the upper sub-pixel of the Ith row (ith ROW) and the lower sub-pixel of the kth column (kth ROW) Vcom [j]).

Therefore, in the driving method of the second embodiment, the common voltage swings alternately in frame units of two common voltages of the positive (+) level and the negative (-) level. Therefore, the data voltage can be set to 0 to 5 V both in the positive polarity (+) and in the negative polarity (-), and the power consumption can be reduced more than in the conventional driving method.

The second embodiment of the present invention can reduce the swing range of the data voltage by the common voltage of the positive polarity and the negative polarity, which are alternately input at regular intervals, so that the power consumption can be greatly reduced. . In addition, the second embodiment of the present invention has the effect of improving the display quality by suppressing the change of the pixel voltage according to the common voltage change after charging since the common voltage is inputted simultaneously with the gate voltage in addition to the data voltage . In addition, since the voltage variation period of the common voltage is made on a frame-by-frame basis according to the second embodiment of the present invention, the voltage variation period of the data line is drastically reduced, and the power consumption can be greatly reduced.

≪ Third Embodiment >

FIG. 8 is a waveform diagram of a signal applied to the sub-pixel shown in FIG. 6 according to the third embodiment of the present invention.

The third embodiment of FIG. 8 also uses a sub-pixel circuit configuration as described in the configuration diagram of the liquid crystal panel according to the second embodiment of FIG.

Accordingly, the data lines D [i] to D [l] wired in the first direction are formed on the liquid crystal panel PNL. Gate lines G [i] to G [l] wired in the second direction are formed so as to intersect the data lines D [i] to D [l]. Further, subpixels (SPo, SPe) defined by the data lines D [i] to D [l] and the gate lines G [i] to G [l] are formed. The first and second common voltage lines Vcom (i) to G [i] are wired in the second direction adjacent to the gate lines G [i] to G [ (i, k), Vcom [j, l] are disposed and common voltage lines Vcom [i, k], Vcom [j, l] for transmitting common voltages of different levels are included.

The first common voltage line Vcom [i] positioned in the same column as the I th gate line G [i] is connected to the odd subpixels SPo and the J th column jth ROW) of odd sub-pixels SPo. The second common voltage line Vcom [j] located in the same column as the Jth gate line G [j] is connected to the even-numbered subpixels SPe of the Jth row jth ROW and the (kth ROW) even-numbered subpixels (SPe).

Accordingly, the subpixels SPo and SPe receive a common voltage through a common voltage line supplying different voltages even though they are located in the same column. Here, Vcom and Pixel are schematics of a common electrode and a pixel electrode included in the subpixels SPo and SPe, respectively. This is because the pixel electrode and the common electrode are formed in the IPS mode or the FFS mode, But the structure is not limited thereto.

6 and 8, the first common voltage line Vcom [i] and the second common voltage line Vcom [j] have different first common voltage VCOM [i] And delivers the second common voltage VCOM [j]. Similarly, although not shown in FIG. 8, the first common voltage line Vcom [k] and the second common voltage line Vcom [l] are connected to the first common voltage VCOM [i] (VCOM [k]) corresponding to the first common voltage VCOM [k] and the second common voltage VCOM [j]. The first common voltage VCOM [i] alternately swings in the order of the negative (-) level (V_low) and the positive (+) level (V_high) with reference to the reference voltage level Va. The second common voltage VCOM [j] alternately swings in the positive (+) level (V_high) and the negative (-) level (V_low) with reference to the reference voltage level Va. Here, Vsync is a vertical synchronization signal.

In the second embodiment, the voltage swings alternately at different voltage levels (negative polarity and positive polarity) of the first common voltage VCOM [i] and the second common voltage VCOM [j] for each frame. The third common voltage VCOM [i] is different from the first common voltage VCOM [i] in voltage levels (negative polarity and positive polarity) of the second common voltage VCOM [ . There is a difference in that two gate signals supplied to the gate line wired to the corresponding line and the gate line wired to the next line are supplied until the supplied gate signal is maintained at the reference voltage level Va. This will be described in more detail as an example of the second common voltage VCOM [j] as follows.

The second common voltage VCOM [j] is supplied while maintaining the reference voltage level Va for the Nth frame (Frame [n]). When the gate signal Vgate G [j] is supplied to the corresponding gate line G [j], the gate signal Vgate G [j] is supplied in positive polarity (+) level (V_high). At this time, the second common voltage VCOM [j] of the positive (+) level (V_high) is maintained until the gate signal (Vgate G [k]) of the next gate line G [k] is supplied. Then, when the gate signal Vgate G [l] of the next gate line G [l] is supplied, it is maintained at the reference voltage level Va.

Thereafter, the second common voltage VCOM [j] is supplied while maintaining the reference voltage level Va during the (N + 1) -th frame (Frame [n + 1]). When the gate signal Vgate G [j] is supplied to the gate line G [j], the second common voltage VCOM [j] is synchronized with the negative (-) level (V-low) . At this time, the second common voltage VCOM [j] of the negative (-) level (V-low) is maintained until the gate signal (Vgate G [k]) of the next gate line G [k] do. When the gate signal Vgate G [l] of the next gate line G [l] is supplied, the second common voltage VCOM [j] is maintained at the reference voltage level Va again. That is, as described above, the second common voltage VCOM [j] includes two gate signals Vgate G [j] and Vgate G [j] supplied to the gate line wired to the corresponding line and the gate line wired to the next line, (+) level (V_high) or a negative (-) level (V-low) until the point of time when the voltage Vs is supplied. Then, when the gate signal Vgate G [l] supplied to the gate line wired to the next line is supplied, the second common voltage VCOM [j] is maintained at the reference voltage level Va again.

Similarly, the first common voltage VCOM [i] maintains the reference voltage level Va during the Nth frame (Frame [n]), and when the gate signal is supplied to the corresponding gate line, Level (V-low). Thereafter, the first common voltage VCOM [i] maintains the reference voltage level Va during the (N + 1) th frame (Frame [n + 1]) and, when a gate signal is supplied to the corresponding gate line, (+) Level (V_high).

On the other hand, as described above, after the sub pixel is charged, the charged sub pixel is in a floating state. At this time, even if the common voltage is changed, the charged subpixel maintains the same brightness because the difference between the pixel voltage and the common voltage hardly changes. This means that even if the common voltage changes after charging is completed, it has little effect. The common voltage supplied to the corresponding line maintains a positive (+) level or a negative (-) level (V-low) until the time when two gate signals are supplied. This is because each common voltage line must maintain a common voltage supplied to the upper and lower subpixels.

Here, the first common voltage line Vcom [i] is a line located at the previous stage than the second common voltage line Vcom [j]. The supply point of the first common voltage VCOM [i] supplied to the first common voltage line Vcom [i] is the second common voltage VCOM [i] supplied to the second common voltage line Vcom [j] [j]). As described above, by varying the timing at which the common voltage is supplied, the output load of the common voltage driver VcomG can be reduced, so that the power consumption can be reduced.

8, the first common voltage VCOM [i] and the second common voltage VCOM [j] are set to the negative (-) level and the positive (+) level or the positive (+ ) Level and the negative (-) level, and are input at different points of time in synchronization with the gate signal supplied to the corresponding line. At this time, they maintain the reference voltage level Va and are supplied at the negative (-) or positive (+) level in synchronization with the gate signal supplied to the corresponding line, respectively. Thereby maintaining the reference voltage level Va.

Hereinafter, a driving method according to a third embodiment of the present invention will be described.

A data signal supply step of supplying data signals to the data lines D [i] to D [l] wired in the first direction is performed. A gate signal supplying step of supplying gate signals to the gate lines G [i] to G [j] wired in the second direction so as to intersect the data lines D [i] to D [ . The first and second common voltage lines W1 and G [j], which are arranged in the second direction adjacent to the gate lines G [i] to G [j] and alternately arranged for the gate lines G [i] The first common voltage VCOM [i] having different voltage levels in the common voltage lines Vcom [i] and Vcom [j] including the common voltages Vcom [i] and Vcom [j] A common voltage supply step of supplying the voltage VCOM [j] with different supply timings of the first common voltage VCOM [i] and the second common voltage VCOM [j] is performed.

In the common voltage supply step, the first common voltage VCOM [i] is supplied so as to be ahead of the time when the second common voltage VCOM [j] is supplied and the second common voltage VCOM [j] In synchronization with the gate signal supplied to the gate line wired to the gate line. At this time, the first common voltage VCOM [i] may also be supplied in synchronization with the gate signal supplied to the gate line wired to the corresponding line.

In the common voltage supply step, the first common voltage VCOM [i] and the second common voltage VCOM [j] are set to the negative (-) level and the positive (+ And the positive (+) and negative (-) levels. At this time, the voltage polarities of the first common voltage VCOM [i] and the second common voltage VCOM [j] are the same as those of the first common voltage VCOM [i] And is maintained at the reference voltage level again.

In the common voltage supply step, the first common voltage VCOM [i] is applied to the odd subpixel SPo of the Ith row (ith ROW) and the odd subpixel SPo of the Jth column (jth ROW) To be connected to the first common voltage line Vcom [i]. The second common voltage VCOM [j] is connected to the second common voltage line SPe connected to the even subpixel SPe of the jth row jth ROW and the even subpixel SPe of the kth column kth ROW, (Vcom [j]).

Therefore, in the driving method of the third embodiment, the common voltage is alternately swung by making the two common voltages of the positive (+) and negative (-) levels based on the reference voltage level Va. Therefore, the data voltage can be set to 0 to 5 V both in the positive polarity (+) and in the negative polarity (-), and the power consumption can be reduced more than in the conventional driving method.

As described above, according to the third embodiment of the present invention, since the swing range of the data voltage can be reduced by the common voltage having the positive polarity and the negative polarity, which are alternately input at regular intervals, the liquid crystal display device and the driving method thereof . In addition, the third embodiment of the present invention has the effect of improving the display quality by suppressing the change of the pixel voltage according to the common voltage change after charging since the common voltage is input simultaneously with the gate voltage in addition to the data voltage . In the third embodiment of the present invention, since the voltage variation of the common voltage is made up of three gate signal periods, the voltage variation period of the data line is drastically reduced, and the power consumption can be greatly reduced. The third embodiment of the present invention is also applicable to a method of using a black matrix having a narrow width at a boundary portion of a subpixel because the common electrodes of adjacent subpixels maintain the same reference voltage level for most of the time, It is possible to cut off the power.

Hereinafter, the power consumption simulation results of the panel according to the driving method, the power consumption, the conventional driving method, and the driving method of the present invention according to the embodiments of the present invention will be described.

FIG. 9 is a diagram for explaining the power consumption of the data driver according to the driving method, and FIG. 10 is a table of power consumption simulation results of the panel according to the conventional driving method and the driving method of the present invention.

9 is for estimating the power consumed when charging / discharging the liquid crystal panel PNL through the data driver DDRV. It is assumed that the capacitor C repeatedly charges and discharges at the frequency f by the voltage output "Vp" of the data driver DDRV and the output Vp is generated from the input voltage Vs of the data driver DDRV. Then, the amount of charge Q supplied to drive the capacitor C whose load is Vs during one cycle becomes Q = C * Vp. Converting this to power (P) yields P = Q * Vs * f, which is again expressed as C * Vs * Vp * f. This is different from the power consumption P '= C * (Vp) ² * f calculated when the load-in capacitor C is driven by Vp of the ideal voltage source. The reason for this difference is that the power efficiency at which the data driver DDRV generates the Vp output from the input voltage Vs is not 100%.

Table 1 below is a power consumption comparison chart for comparing the driving method of the present invention with the driving method of the conventional line.

Conventional line version driving method The drive system of the present invention Liquid crystal panel 69.6mW 1.8mW Peripheral circuit portion 11mW 14mW The data driver 30mW ~ 30mW Total power consumption 110.6mW 45.8mW

In Table 1 and FIG. 10, the specification of the panel used for comparing the driving method of the conventional line and the driving method of the present invention is as follows. 960 * 640 * RGB based on LTPS, a sub pixel size of 78 mu m * 78 mu m, and an organic insulating film thickness of 3 mu m. And the color displayed on the liquid crystal panel (PNL) is a white pattern.

As can be seen from Table 1 and FIG. 10, in the conventional line-inversion driving method, power loss occurring in the liquid crystal panel is large because one line is charged with the same positive polarity and the next line is charged with negative polarity. Therefore, as seen from the sum of the power consumption in Table 1, the power consumption, that is, the power consumption, is high in the version driving method of the conventional line.

On the other hand, according to the driving method of the present invention, even if the same line is charged, the power loss occurring in the liquid crystal panel is greatly improved because the charging occurs in the positive polarity, the negative polarity, and the positive polarity. Therefore, as shown in Table 1, the driving method of the present invention shows that the power loss, that is, the power consumption is significantly improved as compared with the conventional method.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

TCN: Timing control unit PWR: Power supply unit
DDRV: Data driver SDRV: Gate driver
PNL: liquid crystal panel BLU: backlight unit
GL: Gate lines DL: Data lines
SPo: odd-numbered subpixel SPe: even-numbered subpixel
Vcom: common electrode Pixel: pixel electrode

Claims (14)

Data lines wired in a first direction;
Gate lines wired in a second direction to intersect the data lines;
Subpixels defined by the data lines and the gate lines; And
And common voltage lines arranged in the second direction and having a pair of first and second common voltage lines arranged up and down with respect to the subpixels,
Wherein a first common voltage supplied to the first common voltage line and a second common voltage supplied to the second common voltage line have different voltage levels,
The first common voltage line is coupled to the even subpixels of the I th column and the second common voltage line is coupled to the odd subpixels of the I th column,
A second common voltage line for supplying the second common voltage to the I th column and a second common voltage line for supplying a second common voltage to the J th column after the I th column, And the first common voltage line to be supplied is arranged together. Data lines wired in a first direction;
Gate lines wired in a second direction to intersect the data lines;
Subpixels defined by the data lines and the gate lines; And
And common voltage lines having a first common voltage line for supplying a first common voltage and a second common voltage line for supplying a second common voltage having a voltage level different from the first common voltage,
Wherein the first and second common voltage lines are alternately arranged for each gate line and are wired one by one in the second direction to form a pair with one of the gate lines,
The first common voltage line is connected to the odd subpixels of the I th column and the odd subpixels of the J th column located after the I th column,
And the second common voltage line is connected to even-numbered subpixels in the (J) -th column and to even-numbered subpixels in a (K) -th column following the jth column. 3. The method according to claim 1 or 2,
The first common voltage alternately swings in the order of the negative polarity and the positive polarity,
The second common voltage alternately swings in the order of the positive polarity level and the negative polarity level,
And the first and second common voltages swing alternately for each frame. 3. The method of claim 2,
The first common voltage alternately swings in the order of the negative polarity and the positive polarity in the order of the reference voltage level,
The second common voltage alternately swings in order of the positive polarity level and the negative polarity level with reference to the reference voltage level,
And the first and second common voltages swing alternately for each frame. 3. The method of claim 2,
A positive polarity level and a negative polarity level of the first common voltage and a positive polarity level and a negative polarity level of the second common voltage,
Wherein the gate signal is supplied to a gate line supplied to a corresponding line and a gate signal supplied to a gate line connected to the next line, delete The method according to claim 1,
The sub-
A pixel electrode and a common electrode are formed on a thin film transistor substrate. A plurality of data lines arranged in a first direction, gate lines arranged in a second direction intersecting the data lines, subpixels defined by the data lines and gate lines, And a second common voltage line supplying a second common voltage having a voltage level different from that of the first common voltage, wherein the first and second common voltage lines And one of the gate lines is wired one by one in the second direction and the first common voltage line is connected to the odd subpixels in the Ith column and the odd subpixels in the And the second common voltage line is connected to even-numbered subpixels in the (J) -th column and to even-numbered subpixels in the (K) A method of driving a connected liquid crystal display device,
A data signal supply step of supplying data signals to the data lines;
A gate signal supply step of supplying gate signals to the gate lines; And
And a common voltage supply step of supplying the common voltage between the first common voltage and the second common voltage. 9. The method of claim 8,
In the common voltage supply step
Supplying the first common voltage such that the first common voltage is higher than a time point when the second common voltage is supplied,
And the second common voltage is synchronized with a gate signal supplied to a gate line wired to a corresponding line. 9. The method of claim 8,
In the common voltage supply step
The first common voltage is alternately swung in the order of the negative polarity and the positive polarity,
Alternately swing the second common voltage in the order of the positive polarity level and the negative polarity level,
Wherein the first and second common voltages are alternated for each frame. 9. The method of claim 8,
In the common voltage supply step
The first common voltage is alternately swung in the order of the negative polarity and the positive polarity in the order of the reference voltage level,
And alternately swings the second common voltage in the order of the positive polarity level and the negative polarity level with reference to the reference voltage level. 12. The method of claim 11,
Wherein the negative polarity level of the first common voltage and the positive polarity level and the positive polarity level of the second common voltage and the negative polarity level of the second common voltage
Wherein the gate signal is supplied to a gate line connected to a corresponding line and a gate line supplied to a gate line connected to a next line, and then maintained at the reference voltage level. delete 3. The method of claim 2,
Wherein the supply point of time of the first common voltage is different from the supply point of time of the second common voltage.

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