KR102290615B1 - Display Device - Google Patents

Abstract

The liquid crystal display of the present invention includes a pixel group including a plurality of pixels arranged along a horizontal line direction, a power module generating a common voltage to be provided to the pixels, a vertical common line receiving a common voltage from the power module, and a vertical common line and a horizontal common line connected to the line and providing a common voltage to one pixel group. In the pixel group, the number of positive sub-pixels and the number of negative sub-pixels are the same.

Description

Liquid crystal display device {Display Device}

The present invention relates to a liquid crystal display device.

An active matrix driving type liquid crystal display uses a thin film transistor (hereinafter referred to as "TFT") as a switching element to display a moving picture. This liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), so it is not only applied to display devices in portable information devices, office devices, computers, etc.

Pixels of the liquid crystal display device include a thin film transistor connected to a data line and a gate line crossing each other, and connected to the crossing part. The thin film transistor supplies a data voltage supplied through the data line to the pixel electrode of the liquid crystal cell in response to a gate pulse from the gate line. The liquid crystal cell is rotated by an electric field generated according to a voltage difference between the voltage of the pixel electrode and the common voltage Vcom applied to the common electrode to adjust the amount of light passing through the polarizing plate. The storage capacitor is connected to the pixel electrode of the liquid crystal cell to maintain the voltage of the liquid crystal cell.

A ripple phenomenon may occur in the common voltage Vcom applied to the common electrode due to electrical coupling with the pixel electrode. The ripple phenomenon of the common voltage Vcom is proportional to the amount of change of the data voltage with time. Therefore, in the inversion method of driving while changing the polarity of the data voltage, when the polarity of the data voltage is changed, the fluctuation range of the data voltage is large, so that the ripple of the common voltage Vcom becomes severe. As such, the ripple phenomenon of the common voltage Vcom causes a line-dim phenomenon along the horizontal direction, thereby degrading the display quality.

An object of the present invention is to provide a liquid crystal display device for improving a horizontal dim phenomenon due to a ripple phenomenon of a common voltage.

A liquid crystal display device of the present invention includes a pixel group including a plurality of pixels arranged along a horizontal line direction, a power module generating a common voltage to be provided to the pixels, a vertical common line receiving a common voltage from the power module, and a vertical common and a horizontal common line connected to the line and providing a common voltage to one pixel group. In the pixel group, the number of positive sub-pixels and the number of negative sub-pixels are the same.

In the present invention, a horizontal line is divided into pixel groups, and a common voltage is individually provided to each pixel group so that a ripple generated in the common voltage does not affect adjacent pixel groups. Accordingly, it is possible to improve the horizontal dim phenomenon due to the ripple of the common voltage.

1 is a view showing the configuration of a liquid crystal display device of the present invention.
2 is a diagram illustrating a connection structure between a pixel group and common lines;
3 is a view for explaining a method of setting a pixel group according to an exemplary embodiment;
FIG. 4 is a view showing the pixel structure shown in FIG. 3;
FIG. 5 is a diagram illustrating a lower common line in the pixel shown in FIG. 4;
FIG. 6 is a diagram illustrating an upper common line in the pixel shown in FIG. 4;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a view showing a liquid crystal display device according to the present invention.

Referring to FIG. 1 , the liquid crystal display of the present invention includes a liquid crystal panel 100 , a timing controller 210 , a power module 220 , a gate driver 230 , and a data driver 240 .

The liquid crystal panel 100 includes a thin film transistor array substrate on which a thin film transistor array is formed and a color filter substrate on which a color filter is formed, and a liquid crystal layer is formed between the thin film transistor array substrate and the color filter substrate. Also, in the liquid crystal panel 100 , in the thin film transistor array substrate, a region in which pixels P are arranged is defined as a pixel array region 100A.

The timing controller 210 receives digital video data (RGB) from an external host (not shown), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a main clock A timing signal such as (CLK) is received. The timing controller 210 transmits digital video data RGB to the source drive ICs 240 . The timing controller 210 includes a source timing control signal for controlling the operation timing of the data driver 240 using the timing signals Vsync, Hsync, DE, and CLK, and a source timing control signal for controlling the operation timing of the gate driver 230 . A gate timing control signal GCLK is generated.

The power module 220 receives the power voltage VCC and outputs a gate high voltage VGH, a gate low voltage VGL, a high potential voltage VDD, and a common voltage Vcom. The gate high voltage VGH is a high level voltage of the scan pulse supplied to the gate line GL, and the gate low voltage VGL is a low level voltage of the scan pulse supplied to the gate line GL. The common voltage Vcom may be a voltage level within the range from the low potential voltage to the high potential voltage VDD, for example, the common voltage may have a potential HVDD between the low potential voltage and the high potential voltage VDD. .

The GIP-type gate driver 230 includes a level shifter 231 and a shift register 233 mounted on the PCB 200 .

The level shifter 231 receives driving voltages such as the gate high voltage VGH and the gate low voltage VGL, and receives the start signal ST and the gate clock signal GCLK from the timing controller 210, A start pulse VST and a clock signal CLK swinging between the voltage VGH and the gate low voltage VGL are output. The clock signals CLK output from the level shifter 26 are sequentially shifted in phase and transmitted to the shift register 233 formed in the display panel 100 . The shift register 233 is connected to the gate line GL of the display panel 100 . The shift register 233 includes a plurality of cascadingly connected stages. The shift register 233 shifts the start pulse VST input from the level shifter 231 according to the clock signal CLK and sequentially supplies the gate pulses to the gate lines GL.

The data driver 240 receives digital video data RGB from the timing controller 210 . The data driver 240 converts digital video data RGB into positive/negative analog data voltages in response to a source timing control signal from the timing controller 210 , and then synchronizes the data voltages with the gate pulses on the display panel It is supplied to the data lines DL1 to DLn of (100).

2 is a schematic diagram showing a connection structure of a common line and a common electrode in the liquid crystal panel 100 according to the present invention.

Referring to FIG. 2 , the connection structure of the pixel group PG, the vertical common line VCVL, and the horizontal common line VCHL is as follows. The pixels arranged in one horizontal line are divided into first to kth pixel groups PG1 to PG[k]. The first pixel group PG1_1 to PG1_m includes a plurality of sub-pixels.

The common line includes vertical common lines VCVL1 to VCVL[k] and horizontal common lines VCHL1 to VCHL[k]. Pixel groups formed in the same column share the vertical common line VCVL. For example, the first pixel groups PG1_1 to PG1_m are connected to the first vertical common line VCVL1. Each of the vertical common lines VCVL1 to VCVL[k] may include one or more common lines formed in a vertical direction. For example, the first vertical common line VCVL1 may be formed for each boundary surface of the sub-pixels included in the first pixel groups PG1_1 to PG1_m. The first vertical common line VCVL1 is connected to the horizontal common line VCHL1 formed in the horizontal line direction.

The first to kth horizontal common lines VCHL1 to VCHL[k] are connected to only one pixel group through the common electrodes 12 , 22 , and 24 . For example, the first horizontal common line VCHL1 positioned on the first horizontal line is connected only to pixels belonging to the first pixel group PG1_1 , and the second horizontal common line VCHL2 is connected to the second pixel group PG2_1 . connected only to pixels. Accordingly, even if a ripple phenomenon of the common voltage occurring in the pixels belonging to each pixel group PG occurs, the other pixel groups PG in the horizontal direction are not affected. Although the pixel groups PG are connected to other pixel groups PG in the vertical direction through the vertical common line VCVL, the pixel groups PG formed in different horizontal lines receive gate pulses at different timings. not affected by

In addition, each pixel group PG is set to have the same number of positive sub-pixels and negative sub-pixels in order to minimize the influence of ripples generated therein. Also, among the sub-pixels belonging to each pixel group PG, the number of positive-polarity color pixels and negative-polarity color pixels is set to be the same for each color pixel. For example, positive red pixels and negative red pixels are set to the same number, respectively, positive green pixels and negative green pixels are set to have the same number, and positive blue pixels and negative blue pixels are the same set in number.

3 is a diagram illustrating an example of setting a pixel group. The pixel array shown in FIG. 3 represents a liquid crystal panel having a double rate driving (DRD) structure. In a liquid crystal panel having a DRD structure, two gate lines are formed corresponding to one horizontal line, and one data line is alternately connected to pixels formed in odd columns and even columns.

A method of setting a pixel group will be described with reference to FIGS. 2 and 3 . In the first horizontal line corresponding to the first and second gate lines GL1 and GL2 , red, green, and blue sub-pixels are repeatedly formed in order. Since one pixel group includes an even number of sub-pixels of the same color, the first pixel group PG1_1 to PG1_m must include at least six sub-pixels. However, as shown in FIG. 3 , in the liquid crystal panel of the DRD structure, two pixels adjacent to the data line DL are provided with data voltages of the same polarity, so that the horizontal 2-dot driving is performed. Accordingly, six sub-pixels from the first red pixel R1 to the second blue pixel B2 have two negative sub-pixels when there are four positive sub-pixels. Accordingly, in the liquid crystal panel illustrated in FIG. 3 , a total of 12 sub-pixels from the first red pixel R1 to the fourth blue pixel B4 are set as the first pixel group PG1.

FIG. 4 is a diagram illustrating structures of a first red pixel R1 and a first green pixel G1 in the DRD type liquid crystal panel shown in FIG. 3 .

Referring to FIG. 4 , the first red pixel R1 and the first green pixel G1 receive a data voltage through the first data line D1 . The first gate line GL1 is connected to the first green pixel G1 through the second transistor T2 , and the second gate line GL2 is connected to the first red pixel G1 through the first transistor T1 . is connected with The first vertical common line VCVL is formed in a region where the data line DL is not formed among the boundary regions of the pixels. The first vertical common line VCVL1 may be formed using the same data metal layer as the data line DL.

The first horizontal common line VCHL1 is formed below the first gate line GL1 and above the second gate line GL2 , respectively. One or more common electrodes 24 are branched from the first horizontal common line VCHL1 . The common electrode 24 may be formed to cross the pixel electrode 1 . The first horizontal common line VCHL may be formed using the same gate metal layer as the gate lines GL1 and GL2 , or may be formed using the same pixel electrode metal layer as the pixel electrode 1 . As described above, the first vertical common line VCVL1 and the first horizontal common line VCHL1 formed using different metal layers may be connected to each other through the contact hole CNT1 .

The first horizontal common line VCHL1 and the adjacent second horizontal common line VCHL2 are not connected to each other in order to prevent the ripple of the common voltage from being transmitted. Referring to FIGS. 5 and 6 , the structure of a horizontal common line between adjacent pixel groups is as follows. As shown in FIGS. 5 and 6 , the horizontal common lines VCHL may include a lower horizontal common line VCHL_B and an upper horizontal common line VCHL_T.

5 is a diagram illustrating the structure of the lower horizontal common line VCHL_B.

The lower horizontal common line VCHL_B of FIG. 5 is formed using a gate metal layer forming the gate line GL on the base substrate.

The first lower horizontal common line VCHL1_B is formed as a pair in parallel with the gate lines GL1 and GL2 at upper and lower portions, respectively. Each of the first lower horizontal common lines VCHL1_B is formed between the first gate line GL1 and the pixel region and between the second gate line GL2 and the pixel region. In the vertical boundary area of the pixels, a vertical boundary common line 12 connecting the first lower horizontal common line VCHL1_B formed respectively above and below the pixel is formed. Due to this structure, in the first pixel block PG1 , common lines surrounding the boundary area of each pixel form a mesh structure.

Also, since the first lower horizontal common line VCHL1_B and the second lower horizontal common line VCHL2_B do not contact each other, the first pixel block PG1 and the second pixel block PG2 are not directly connected.

6 is a view showing the structure of the upper horizontal common line.

Like the lower horizontal common line VCHL_B, the upper horizontal common line VCHL_T shown in FIG. 6 has a mesh structure surrounding the boundary area of the pixels. The first upper horizontal common line VCHL1_T is not directly connected to the second upper horizontal common line VCHL2_T. That is, the first pixel block PG1 and the second pixel block PG2 are each individually supplied with a common voltage, and accordingly, even if a ripple of the common voltage Vcom occurs in each pixel block PG, they are adjacent to each other. It does not affect the pixel blocks that are

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (5)

a pixel group formed by being divided into a plurality along one horizontal line direction, each pixel group including a plurality of pixels;
a power module generating a common voltage to be provided to the pixels;
a vertical common line receiving a common voltage from the power module; and
and a horizontal common line connecting the vertical common line and one pixel group among the plurality of pixel groups and providing a common voltage to pixels belonging to the one pixel group;
In the one pixel group, the number of positive sub-pixels and the number of negative sub-pixels are set to be the same.
The method of claim 1,
In the pixel group, the sub-pixels for any color are set to have the same number of sub-pixels having a positive polarity and sub-pixels having a negative polarity.
The method of claim 1,
The horizontal common line is disposed above and below the pixels, respectively,
A boundary region between pixels in the one pixel group further includes a vertical boundary common line connecting the horizontal common lines,
The horizontal common line and the vertical boundary common line formed in the one pixel group form a mesh structure.
4. The method of claim 3,
The horizontal common line and the vertical boundary common line are positioned in at least one of a gate metal layer and a pixel electrode metal layer.
The method of claim 1,
The vertical common line is located in the data metal layer, and the vertical common line is connected to the horizontal common line through a contact hole.

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