KR101901339B1 - liquid crystal display device - Google Patents

Abstract

The present invention is characterized in that a plurality of vertical common wirings extending in the column direction are formed in the display region, and a plurality of vertical common wirings extending in the row direction are formed in the non-display region, A liquid crystal panel formed on the substrate; And a data driving circuit for supplying a data voltage to the liquid crystal panel, wherein the lower common wiring is formed in the same layer as the plurality of vertical common wirings and connected to each other.

Description

[0001] The present invention relates to a liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device that efficiently disperses static electricity generated during a liquid crystal panel manufacturing process.

2. Description of the Related Art [0002] With the development of an information society, demands for a display device for displaying images have been increasing in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as an organic light emitting diode (OLED) have been utilized.

Here, the liquid crystal display device can be downsized, and is widely used in portable information devices and computers. In such a liquid crystal display device, a data voltage is applied to the pixel electrode, a common voltage is applied to the common electrode, and the liquid crystal is driven by the voltage difference.

Hereinafter, common wiring for transmitting a common voltage to the common electrode of each corresponding pixel will be described with reference to FIG.

Fig. 1 is a view schematically showing a common wiring formed in the conventional liquid crystal display device 10. Fig.

As shown in Fig. 1, in order to apply a common voltage to the common electrode, a plurality of vertical common wirings (CLV) are formed. The vertical common wiring CLV is connected to an upper end of the liquid crystal panel 20, that is, a horizontal common wiring CLH formed on the data driving circuit (not shown), and receives a common voltage. Further, the vertical common wiring CLV is connected to the ground voltage GND formed at the lower portion of the liquid crystal panel 20.

In this vertical common wiring (CLV), static electricity accumulates during the fabrication process. Specifically, in the thin film transistor forming step, the protective layer deposition and etching processes can use plasma. In this case, (For example, data wiring or common wiring). At this time, if the static electricity accumulated in the vertical common wiring CLV is not discharged, there is a problem that the data wiring (not shown) and the vertical common wiring CLV are short-circuited.

As a workaround to prevent this, the vertical common wiring (CLV) is formed in the liquid crystal panel 20, and the static electricity prevention circuit 21 is formed at the lower end of the vertical common wiring (CLV). However, this does not efficiently improve the short circuit problem of the vertical common wiring (CLV) generated during the manufacturing process.

Further, since the static electricity prevention circuit 21 has to be further added, the manufacturing process becomes complicated and the production cost increases.

There is a problem in providing a liquid crystal display device that effectively dissipates static electricity generated during a liquid crystal panel manufacturing process and prevents short circuits of vertical common wirings by connecting the lower ends of the vertical common wirings to each other in the same layer as the outer common wirings.

In order to achieve the above-mentioned object, the present invention is characterized in that the display region is divided into a display region and a non-display region, and a plurality of vertical common wirings extending in the column direction are formed in the display region, A liquid crystal panel in which an outline common wiring including a lower common wiring extending is formed; And a data driving circuit for supplying a data voltage to the liquid crystal panel, wherein the lower common wiring is formed in the same layer as the plurality of vertical common wirings and connected to each other.

And the lower common wiring is formed on the side opposite to the data driving circuit.

The lower common wiring and the plurality of vertical common wirings are formed on the gate insulating film.

A protective layer is formed on the lower common wiring and the plurality of vertical common wirings.

The lower common wiring and the plurality of vertical common wirings are formed in the same layer as the layer in which the source electrode and the drain electrode are formed.

A method of manufacturing a liquid crystal display device in which a lower common wiring and a plurality of vertical common wirings are formed on a glass substrate, the method comprising: forming a gate insulating film on the glass substrate; And a protective layer is formed on the lower common wiring and the plurality of vertical common wirings.

The lower common wiring is formed on the opposite side of the data driving circuit.

The lower common wiring and the plurality of vertical common wirings are formed in the same layer as the layer in which the source electrode and the drain electrode are formed.

The vertical common wiring and the lower common wiring are connected to each other in the same layer to effectively distribute the static electricity generated during the manufacturing process of the liquid crystal panel to prevent the short circuit between the vertical common wiring and the data wiring.

There is no need to form an additional antistatic circuit at the lower end of the vertical common wiring, which can increase the efficiency of the manufacturing process and reduce the production cost.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view schematically showing a liquid crystal display device in which a common wiring line is formed; Fig.
2 is a cross-sectional view schematically showing a liquid crystal display device according to an embodiment of the present invention.
3 is an equivalent circuit diagram of a sub-pixel according to an embodiment of the present invention.
4 is a cross-sectional view schematically showing a part of a liquid crystal panel according to an embodiment of the present invention.
5 is a cross-sectional view schematically illustrating a sub-pixel according to an embodiment of the present invention.
6 is a cross-sectional view taken along the line IV-IV in Fig. 5;
7 is a cross-sectional view schematically showing a liquid crystal display device having a common wiring according to an embodiment of the present invention.
8 is a sectional view taken along the line V-V in Fig.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a schematic diagram of a liquid crystal display according to an embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of a subpixel according to an embodiment of the present invention.

As shown in the figure, a liquid crystal display 100 according to an embodiment of the present invention includes a liquid crystal panel 200, a driving circuit 700, and a backlight 800.

First, the liquid crystal panel 200 may be divided into a display area DA and a non-display area NDA. The display area DA may be a region where the image is displayed, for example, a portion excluding the outer edge of the liquid crystal panel 200. [ On the other hand, the non-display area NDA is an area where no image is displayed, and can be, for example, the outer edge of the liquid crystal panel 200. [

In the display area DA of the liquid crystal panel 200, a large number of first and second gate wirings GL11 to GLn1 and GL12 to GLn2 extend in the first direction, for example, in the row direction. A plurality of data lines DL extend in a second direction that crosses the first direction, for example, in the column direction.

Here, a plurality of first and second gate lines GL11 to GLn1 and GL12 to GLn2 and a plurality of data lines DL intersect each other to define a plurality of sub-pixels SP arranged in a matrix form do. That is, one subpixel SP is defined as one first gate line GL11 to GLn1, one second gate line GL12 to GLn2, and one data line DL. The sub-pixel SP may include, for example, an R sub-pixel that emits red, a G sub-pixel that emits green, and a B sub-pixel that emits blue. The corresponding R, G, and B image data are input to each of the R, G, and B subpixels SP. Here, neighboring R, G, and B subpixels SP constitute one pixel.

Referring to FIG. 3, each sub-pixel SP includes a thin film transistor T, a liquid crystal capacitor Clc, and a storage capacitor Cst.

The thin film transistor T is formed at the intersection of the first gate lines GL11 to GLn1 or the second gate lines GL12 to GLn2 and the data line DL. A pixel electrode (not shown) is connected to the thin film transistor T. On the other hand, a common electrode (not shown) is formed corresponding to the pixel electrode. When a data voltage is applied to the pixel electrode and a common voltage Vcom is applied to the common electrode, an electric field is formed between them to drive the liquid crystal. The pixel electrode, the common electrode, and the liquid crystal located between these electrodes constitute a liquid crystal capacitor Clc. Each sub-pixel SP further includes a storage capacitor Cst, which serves to store the data voltage applied to the pixel electrode until the next frame.

Referring again to FIG. 2, in the display area DA of the liquid crystal panel 200, a plurality of vertical common wirings VCL extend in parallel with a plurality of data wirings DL. At this time, a plurality of vertical common wirings (VCL) are formed, for example, for each of two neighboring sub-pixels SP in the row direction.

The outer common line (ACL) is formed in the non-display area (NDA) of the liquid crystal panel (200). Specifically, the outer common wiring (ACL) is composed of two horizontal wirings extending in the row direction and two vertical wirings extending in the column direction, and the respective horizontal and vertical wirings are connected to each other to form a closed structure. That is, the outer common line ACL is formed along the four sides in the non-display area NDA of the liquid crystal panel 200. [

Here, the horizontal wiring of the outer common wiring (ACL) extending in the row direction is connected to the vertical common wiring (VCL). Specifically, one end of the vertical common wiring (VCL) is connected to the outer common wiring (ACL) extending in the row direction and located at the upper portion of the liquid crystal panel 200, and the other end of the vertical common wiring And is connected to the outer common line (ACL) located under the liquid crystal panel (200).

The vertical wiring of the outer common wiring (ACL) extending in the column direction receives the common voltage (Vcom) from the common voltage supply circuit (600). Thus, the common voltage Vcom is transmitted to the corresponding sub-pixels SP through the outer common line ACL and the vertical common line VCL located at the upper portion of the liquid crystal panel 200.

The backlight 800 functions to supply light to the liquid crystal panel 200. A cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), a light emitting diode (LED), or the like may be used as the light source of the backlight 800. [

The driving circuit D may include a timing controller 300, a gate driving circuit 400, a data driving circuit 500, and a common voltage supply circuit 600.

Here, the timing controller 300 receives image data (RGB), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (CLK), and a data enable signal And a control signal TCS such as a control signal DE. Meanwhile, although not shown, such signals may be input through an interface configured in the timing controller 300.

The timing controller 300 generates a gate control signal GCS for controlling the gate drive circuit 400 and a data control signal DCS for controlling the data drive circuit 500 using the input control signal TCS, ).

The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE.

The data control signal DCS includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE) signal, a polarity signal (POL) . ≪ / RTI >

In addition, the timing controller 300 receives image data RGB from an external system, aligns the image data, and transmits the image data to the data driving circuit 500.

The gate driving circuit 400 sequentially scans a plurality of first and second gate lines GL11 to GLn1 and GL12 to GLn2 in response to a gate control signal GCS supplied from the timing controller 300, )do. For example, a plurality of first and second gate lines GL11 to GLn1 and GL12 to GLn2 are sequentially selected for every frame, and a gate high voltage is output to the selected gate line GL. More specifically, for example, after selecting the first first gate wiring GL11 to output a gate high voltage, the first gate wiring GL12 is selected to output a gate high voltage. Then, after the second first gate line GL21 is selected, the second gate line GL22 is selected. Similarly, the third gate wiring GL13 is sequentially selected from the third gate wiring GL13 to the nth second gate wiring GLn2, and the gate high voltage is output. By the gate high voltage, the thin film transistor T positioned on the corresponding row line is turned on. Meanwhile, a gate low voltage which is a turn off voltage is supplied to the first and second gate lines GL11 to GLn1 and GL12 to GLn2 until the next frame scan, and the thin film transistor (T in Fig. 3) Off state.

The data driving circuit 500 supplies the data voltages to the plurality of data lines DL in response to the data control signal DCS and the video data RGB supplied from the timing controller 300. [ That is, using the gamma voltage, a data voltage corresponding to the image data (RGB) is generated, and the generated data voltage is output to the data line DL.

Hereinafter, the display area DA of the liquid crystal panel 200 according to the embodiment of the present invention will be described in more detail with reference to FIG.

4 shows a display area DA of a liquid crystal panel 200 according to an embodiment of the present invention. In the display area DA, two first and second gate lines GL11 to GL22, A part of the liquid crystal panel 200 in which the common lines VCL1 and VLC2 and the data lines DL1 and DL2 are formed is shown as an example.

First, as shown in FIG. 4, the first R sub-pixel R1 and the G sub-pixel G1 adjacent to each other are arranged such that the first first gate wiring GL11 and the first second gate wiring GL12 are connected to the first And is defined to intersect the data line DL1.

At this time, the thin film transistor T of the first R sub-pixel R1 is connected to the left side of the first data line DL1 to be connected to the pixel electrode Ep of the first R sub-pixel R1, The thin film transistor T of the sub-pixel G1 is connected to the right of the first data line DL1 and is connected to the pixel electrode Ep of the first G sub-pixel G1.

The first B sub-pixel B1 is connected to the second R sub-pixel R and the first gate wiring GL11 and the first gate wiring GL12 are connected to the second data wiring DL2, .

At this time, the thin film transistor T of the first B sub-pixel B1 is connected to the left side of the second data line DL2 to be connected to the pixel electrode Ep of the first B sub-pixel B1, The thin film transistor T of the sub pixel R is connected to the right side of the second data line DL2 and connected to the pixel electrode Ep of the neighboring R sub pixel R.

Similarly, in the neighboring second R sub-pixel R2 and the G sub-pixel G2, the second first gate wiring GL21 and the second second gate wiring GL22 intersect with the first data wiring DL1 Is defined.

At this time, the thin film transistor T of the second R sub-pixel R2 is connected to the left side of the first data line DL1, the thin film transistor T of the second G sub-pixel G2 is connected to the first data line DL DL1).

The second B sub-pixel B2 includes the second R'-subpixel R 'and the second first gate line GL21 and the second second gate line GL22 together with the second data line DL2 ). ≪ / RTI >

At this time, the thin film transistor T of the second B sub-pixel B2 is connected to the left side of the second data line DL2 and the thin film transistor T of the neighboring R 'sub-pixel R' And is connected to the right side of the wiring DL2.

That is, one sub-pixel SP is defined, for example, by intersecting two gate lines and one data line. Specifically, the data line is formed between two neighboring sub-pixels SP in the row direction, and two sub-pixels SP adjacent in the row direction share one data line. At this time, the thin film transistors T of the neighboring subpixels SP are alternately connected to the left and right sides of the data lines and are connected to the corresponding pixel electrodes Ep.

At this time, the first vertical common wiring VCL1 and the second vertical common wiring VLC2 extend in parallel with the first and second data lines DL1 and DL2, and a common voltage (not shown) is applied to each corresponding common electrode (Vcom in Fig. 2). Here, the first vertical common wiring VCL1 and the second vertical common wiring VCL2 are formed by two sub-pixels SP adjacent in the row direction (for example, the first R sub-pixel R1 and the first G sub- Pixel G1 or the second R sub-pixel R2 and the second G sub-pixel G2).

Specifically, for example, when a gate high voltage is output to the first first gate line GL11, the thin film transistor T of the first R sub-pixel R1 and the first B sub-pixel B1 is turned on . Thus, the common voltage (Vcom in Fig. 2) is applied to the corresponding common electrode through the first vertical common wiring VCL1 and the second vertical common wiring VCL2.

That is, the vertical common wiring is formed in parallel with the data line for each of the two neighboring sub-pixels SP in the row direction, and transmits a common voltage (Vcom in Fig. 2) to the common electrode of the corresponding sub-pixel SP . As a result, the vertical common wiring and the data wiring are alternately arranged.

Hereinafter, the structure of the sub-pixel SP according to the embodiment of the present invention will be described with reference to FIGS. 5 and 6. FIG.

FIG. 5 is a view showing an example of a sub-pixel SP operated in the AH IPS (Advanced High Performance In-Plane Switching) driving mode, and FIG. 6 is a cross- Sectional view taken along the line IV-IV of Fig.

5, the first gate line GL11 and the first second gate line GL12 intersect with the first data line DL1 in the liquid crystal panel 200, (R1) and a G sub-pixel (G1) are defined. That is, the first data line DL1 is formed between the first R sub-pixel R1 and the first G sub-pixel G1 neighboring in the row direction. Hereinafter, for convenience of description, the ordinal standard yarn is omitted.

A thin film transistor T is formed in the intersection region of the first gate wiring GL11 or the second gate wiring GL12 and the first data wiring DL1. At this time, the thin film transistor T of the R sub-pixel R1 is formed at the lower left of the first data line DL1. Specifically, the thin film transistor T is formed at the intersection region of the second gate line GL12 and the first data line DL1 As shown in FIG. On the other hand, the thin film transistor T of the G sub-pixel G1 is formed on the upper right side of the first data line DL1. Specifically, the thin film transistor T is formed in the intersection region of the first gate line GL11 and the first data line DL1 As shown in FIG.

The thin film transistor T includes a gate electrode 201, a semiconductor layer (SC in FIG. 6), an ohmic contact layer (OC in FIG. 6), and a source electrode 202 and a drain electrode 203.

The gate electrode 201 is connected to the first or second gate line GL11 or GL12 and the semiconductor layer SC of FIG. 6 and the ohmic contact layer OC of FIG. 6 are formed on the gate electrode 201 ) Are formed in this order.

A source electrode 202 and a drain electrode 203 are formed on the ohmic contact layer (OC in FIG. 6). The source electrode 202 is connected to the first data line DL1 and the drain electrode 203 is formed to correspond to the source electrode 202 with the gate electrode 201 interposed therebetween. The electrode 203 is formed to overlap with both sides of the semiconductor layer (SC in Fig. 6) via the ohmic contact layer (OC in Fig. 6).

Pixel electrodes Ep are formed on the R sub-pixel R1 and the G sub-pixel G1, respectively. The pixel electrode Ep is formed by applying a data voltage from the first data line DL1 through the thin film transistor T and the thin film transistor Tl through the first contact hole CH1 formed in the gate insulating film (GI in Fig. 6) T of the source electrode 224.

The common electrode Ec is formed in each of the R sub-pixel R1 and the G sub-pixel G1. Here, the R sub-pixel R1 and the G sub-pixel G1 partially overlap with the corresponding first or second vertical common lines VCL1 and VCL2, respectively. The common electrode Ec of each of the R sub-pixel R1 and the G sub-pixel G1 is electrically connected to the corresponding first or second vertical common wiring VCL1 or VCL2 through the second contact hole CH2 Respectively. Specifically, for example, the common electrode Ec of the R sub-pixel R1 is partially overlapped with the first vertical common wiring VCL1, and the first vertical common wiring VCL1 and the second vertical common wiring VCL2 are overlapped with each other via the second contact hole CH2. And is electrically connected. The G sub-pixel G1 is partially overlapped with the second vertical common wiring VCL2 and is electrically connected to the second vertical common wiring VCL2 through the second contact hole CH2.

Referring to FIG. 6, a gate insulating film GI is formed on a glass substrate GLASS, and a second vertical common wiring VCL2 is formed on a gate insulating film GI. A protection layer PAS is formed on the second vertical common wiring VLC2 and the common electrode Ec is electrically connected to the second vertical common wiring VCL2 through the second contact hole CH2.

The R sub-pixel R1 and the G sub-pixel G1 are driven by a potential difference between the common electrode Ec and the pixel electrode Ep opposing each other in the horizontal direction.

That is, in the embodiment of the present invention, one sub-pixel R1 and one sub-pixel G1 adjacent to each other in the row direction share one data line DL1, and two sub-pixels R1 and G1 neighboring in the row direction By forming the vertical common lines VCL1 and VCL2, the aperture ratio of the liquid crystal panel 200 can be improved.

Hereinafter, the vertical common wiring and the outer common wiring according to the embodiment of the present invention will be described in more detail with reference to FIGS. 7 and 8. FIG.

Fig. 7 is a plan view of a liquid crystal panel in which a vertical common wiring and an outer common wiring are formed, and Fig. 8 is a sectional view taken along the line V-V in Fig.

As shown in FIG. 7, the liquid crystal panel 200 can be divided into a display area DA and a non-display area NDA.

In the display area DA of the liquid crystal panel 200, a plurality of vertical common wirings VCL extend in the column direction. At this time, a plurality of vertical common wirings (VCL) are formed, for example, for each of two sub-pixels (SP in Fig. 2) neighboring in the row direction.

The outer common line (ACL) is formed in the non-display area (NDA) of the liquid crystal panel (200). Specifically, the outer common wiring (ACL) is composed of two sides extending in the row direction and two sides extending in the column direction, and the respective sides are connected to each other to form a closed structure. That is, the outer common line ACL is formed along the four sides in the non-display area NDA of the liquid crystal panel 200. [

Here, the vertical wirings of the outer common wirings ACL extending in the column direction are supplied with the common voltage (Vcom in Fig. 2) from the common voltage supply circuit (600 in Fig. 2). Thus, the common voltage Vcom is transmitted to the corresponding sub-pixels SP through the outer common line ACL and the vertical common line VCL located at the upper portion of the liquid crystal panel 200.

The lateral wirings of the outer common wirings (ACL) extending in the row direction are connected to the vertical common wirings (VCL). Specifically, one end of the vertical common wiring (VCL) is connected to the outer common wiring (ACL) extending in the row direction and located at the upper portion of the liquid crystal panel 200, and the other end of the vertical common wiring And is connected to the outer common line (ACL) located under the liquid crystal panel (200).

At this time, the outer common line (ACL) may be formed to have a larger width than, for example, the vertical common wiring (VCL). This is to effectively apply the common voltage (Vcom in Fig. 2) to the corresponding common electrode by reducing the resistance of the outer common wiring ACL and the vertical common wiring VCL. It is preferable that the vertical common wiring line VCL is formed to have a smaller width than the data line (DL in FIG. 2) to prevent the lowering of the aperture ratio of the liquid crystal panel 200.

Although not shown, for example, the data lines (DL in Fig. 2) and the lateral wirings of the outer common wiring line ACL cross each other. At this time, the data wiring (DL in Fig. 2) and the horizontal wiring are formed in the same layer, and the data wiring (DL in Fig. 2) adjacent to the horizontal wiring is disconnected, (DL in FIG. 2) and the horizontal wiring are prevented by creating jumping holes at the ends of the data lines DL. Concretely, the data line (DL in Fig. 2) is disconnected corresponding to the intersection of the horizontal wiring and the data wiring (DL in Fig. 2). Two jumping holes adjacent to the horizontal wiring and between the horizontal wiring are formed at the end of the data line (DL in Fig. 2) adjacent to the horizontal wiring. Further, a metal pattern is formed on another layer in which the horizontal wiring is not formed, and the data wiring (DL in Fig. 2) and the metal pattern are connected by using the jumping holes, To prevent connection.

8, the outer common wiring ACL and the vertical common wiring VCL (not shown) formed on the opposite side of the data driving circuit (500 in Fig. 2) among the horizontal wirings of the outer common wiring ACL extending in the row direction, ).

First, the outer common wiring line ACL located on the opposite side of the data driving circuit (500 in Fig. 2) of the lateral wiring of the outer common wiring (ACL) extending in the row direction, that is, the lower side of the liquid crystal panel 200, May be formed in the same layer as the vertical common wiring (VCL). Hereinafter, for convenience of explanation, the outer common line (ACL) located under the liquid crystal panel 200 is referred to as a lower common line (SCL).

More specifically, the vertical common wiring VCL and the lower common wiring SCL are formed in the same layer as the data wiring (DL in FIG. 2).

That is, the vertical common wiring VCL and the lower common wiring SCL are formed and connected in the same layer. For example, the vertical common wiring VCL and the lower common wiring SCL may be connected in a layer where the source electrode (202 in FIG. 6) and the drain electrode (203 in FIG. 6) are formed.

Thereby, the following effects are obtained.

First, by forming a common wiring in the liquid crystal panel including a wide outer common wiring and a vertical common wiring, the load of the common wiring can be reduced. Thus, it is possible to prevent distortion of the common voltage transmitted to each sub-pixel.

In addition, an outline common wiring is formed by including a lower common wiring below the liquid crystal panel, and the lower common wiring is connected to the same layer as the vertical common wiring to disperse the static electricity generated during the manufacturing process of the liquid crystal panel. More specifically, in the step of forming the thin film transistor, plasma may be used for the protective layer deposition and etching process. In this case, static electricity is accumulated in a metal wiring (for example, a data wiring or a common wiring) . At this time, static electricity accumulated in the vertical common wiring is dispersed through the lower common wiring to prevent short-circuiting between the common wiring and the data wiring.

In addition, since the vertical common wiring and the lower common wiring are connected to each other in the same layer and the static electricity is dispersed during the manufacturing process, it is not necessary to form another static electricity prevention circuit at the lower end of the common wiring after completing the common wiring, And the production cost can be reduced.

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

100: liquid crystal display device 200: liquid crystal panel
300: timing controller 400: gate driving circuit
500: Data driving circuit 600: Common voltage supply driving circuit
VCL: Vertical common wiring ACL: Outer common wiring
SCL: Lower common wiring

Claims (10)

A plurality of vertical common wirings extending in the column direction are formed in the display region, and as the outer common wirings formed in the non-display region in a closed structure along four sides thereof, the display region is divided into a display region and a non- The outer common wiring including the upper common wiring and the lower common wiring extending in the row direction and the left common wiring and the right common wiring extending in the column direction are formed and the substrate having the pixel electrode and the common electrode formed in each sub- A liquid crystal panel;
And a data driving circuit for supplying a data voltage to the liquid crystal panel,
The lower common wiring is formed in the same layer as the plurality of vertical common wirings and connected to each other,
The common electrode of the sub-pixel is connected to the vertical common wiring corresponding to the sub-pixel through the contact hole,
The substrate includes a data line extending in the column direction and connected to each of two sub-pixels of each row line arranged on both sides, a first gate wiring connected to one of the two sub-pixels of each row line, A second gate wiring connected to the other is formed,
Wherein the vertical common wiring is alternately arranged in units of the data wiring and one of the sub-pixels
Liquid crystal display device.
The method according to claim 1,
And the lower common wiring is formed on the side opposite to the data driving circuit
Liquid crystal display device.
3. The method of claim 2,
Wherein the lower common wiring and the plurality of vertical common wirings
The gate insulating film
Liquid crystal display device.
The method of claim 3,
Wherein a protective layer is formed on the lower common wiring and the plurality of vertical common wirings
Liquid crystal display device.
5. The method of claim 4,
The lower common wiring and the plurality of vertical common wirings are formed in the same layer as the layer in which the source electrode and the drain electrode are formed
Liquid crystal display device.
A method of manufacturing a liquid crystal display device in which an outline common wiring including a lower common wiring and a plurality of vertical common wirings are formed on a substrate divided into a display area and a non-display area,
Forming a gate insulating film on the substrate,
The lower common wiring and the plurality of vertical common wirings are connected to each other over the gate insulating film,
Forming a protective layer on the lower common wiring and the plurality of vertical common wirings,
Wherein the vertical common wiring extends in the column direction in the display region,
The outer common wiring includes an upper common wiring extending in the row direction and a left common wiring and a right common wiring extending in the column direction and formed in a closed structure along four sides of the non- ,
A pixel electrode and a common electrode are formed in each sub-pixel of the display region,
The common electrode is connected to the vertical common wiring corresponding to the sub-pixel through a contact hole,
The substrate includes a data line extending in the column direction and connected to each of two sub-pixels of each row line arranged on both sides, a first gate wiring connected to one of the two sub-pixels of each row line, A second gate wiring connected to the other is formed,
Wherein the vertical common wiring is alternately arranged in units of the data wiring and one of the sub-pixels
A method of manufacturing a liquid crystal display device.
The method according to claim 6,
The lower common wiring is formed on the opposite side of the data driving circuit
A method of manufacturing a liquid crystal display device.
The method according to claim 6,
The lower common wiring and the plurality of vertical common wirings are formed in the same layer as the layer in which the source electrode and the drain electrode are formed
A method of manufacturing a liquid crystal display device. delete delete

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