JP5368125B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and more particularly to a liquid crystal display device driven by a thin film transistor.

  2. Description of the Related Art Generally, a video display device is a device that processes video information input from the outside and displays a video that can be perceived by the eyes, and includes a liquid crystal display (LCD), a plasma display panel, For example, a display device using an organic light emitting diode (PLED) or an organic light emitting diode (OLED). Among such video display devices, a liquid crystal display device has high resolution and excellent image quality, and is widely used in notebook computers, computers, and televisions.

  The liquid crystal display device includes a pixel electrode, two substrates including a common electrode, and a liquid crystal layer sandwiched between the substrates. The liquid crystal display device displays a desired image by applying a predetermined voltage to the pixel electrode and the common electrode of the electric field forming electrode to change the alignment of the liquid crystal molecules to control the polarization direction of the incident light.

  Among such liquid crystal display devices, a vertically aligned (VA) type liquid crystal display device in which major axes of liquid crystal molecules are aligned perpendicular to the upper and lower display plates in a state where an electric field is not applied is a contrast device. It is attracting attention because it has a large ratio and it is easy to realize a wide reference viewing angle. Here, the reference viewing angle means a viewing angle having a contrast ratio of 1:10 or an inter-tone luminance inversion limit angle.

  The vertical alignment type liquid crystal display device controls the alignment direction of liquid crystal molecules by forming openings or protrusions in the electric field generating electrode so as to have wide side visibility. However, the opening or protrusion formed in the electric field generating electrode has a problem of reducing the aperture ratio of the pixel.

  In addition, the conventional vertical alignment type liquid crystal display device has a problem that the side visibility is lower than the front visibility. For example, in the case of a PVA (patterned vertically aligned) liquid crystal display device with an incision, the image becomes brighter toward the side, and in extreme cases, there is no luminance difference between high gradations and the image is blurred. It may be visible.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a display device that is advantageous in securing the aperture ratio of a pixel while improving side visibility.

  Note that the object of the present invention is not limited to the above, and other objects will be apparent to those skilled in the art from the following.

In order to achieve the above object, a liquid crystal display according to an embodiment of the present invention includes a first gate line, a second gate line, a data line intersecting the first gate line and the second gate line, and a first gate line. And a plurality of pixels connected to the second gate line and the data line and arranged in a matrix, each of the pixels having a first pixel electrode, a first gate line, a data line, and a first pixel electrode. The first thin film transistor connected to the first pixel, the second pixel electrode, the first gate line, the data line, the second thin film transistor connected to the second pixel electrode, the sustain electrode, and the first pixel electrode overlapping with the charge. the distribution capacitor formed, and the coupling electrodes formed on the sustain electrode, a first gate line, and a third thin film transistor connected to the sustain electrodes, and the coupling electrode, the second gate line, coupling electrode, and Second pixel electrode And a fourth thin film transistor connected.

  Specific matters of other embodiments are shown in the following detailed description and drawings.

  According to the liquid crystal display device of the present invention, after dividing one pixel electrode into a pair of sub-pixel electrodes, a difference is generated in the pixel voltage of each sub-pixel electrode by charge sharing, thereby allowing side visibility. Can be increased. Further, by connecting a switching element to one end of the charge distribution capacitor that causes charge distribution, the difference in pixel voltage between the pair of subpixel electrodes is increased, and the side visibility can be further improved.

  Furthermore, the aperture ratio of the pixel can be increased by forming a coupling electrode, which is one electrode of the charge distribution capacitor, on the sustain electrode line made of an opaque metal.

1 is a block diagram illustrating a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a perspective view schematically showing a pixel portion of the liquid crystal display device according to the embodiment of the present invention shown in FIG. 1. 1 is an equivalent circuit diagram of a liquid crystal display device according to a first embodiment of the present invention. 1 is a plan view of a liquid crystal display device according to a first embodiment of the present invention. FIG. 5 is a cross-sectional view of the first storage capacitor Cst_H and the second storage capacitor Cst_L according to the first embodiment of the present invention along the line V-V ′ shown in FIG. 4. FIG. 5 is a cross-sectional view of the liquid crystal display device according to the first embodiment of the present invention along the line VI-VI ′ shown in FIG. 4. FIG. 5 is an equivalent circuit diagram of a liquid crystal display device according to a second embodiment of the present invention. It is a top view of the liquid crystal display device by the 2nd Embodiment of this invention. FIG. 9 is a cross-sectional view of a liquid crystal display device according to a second embodiment of the present invention taken along line IX-IX ′ shown in FIG. 8. FIG. 9 is a cross-sectional view of a liquid crystal display device according to a second embodiment of the present invention taken along line X-X ′ shown in FIG. 8.

  Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and this embodiment makes the disclosure of the present invention complete, and those having ordinary knowledge in the technical field to which the present invention belongs fall within the scope of the invention. Is provided to provide a thorough understanding of the invention, and the invention should be defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

  An element is “connected to” or “coupled to” another element when it is directly connected or coupled to another element or in the middle All cases where an element is interposed are included. On the other hand, "directly connected to" or "directly coupled to" one element indicates that no other element is interposed in the middle. “And / or” includes each and every combination of one or more of the items mentioned.

  For example, the first, second, etc. may be used to describe various elements, components and / or sections, although these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first element, the first component, or the first section in the following may be the second element, the second component, or the second section within the technical idea of the present invention.

  The terminology used herein is for the purpose of describing embodiments of the invention and is not intended to limit the invention. In this specification, the singular forms include plural forms unless otherwise specified. Also, as used herein, “comprises” and / or “comprising” refers to a component, step, operation, and / or element being referred to is one or more other components, steps, operations And / or does not exclude the presence or addition of elements.

  Unless otherwise defined, all terms used herein (including technical and scientific terms) are used in the meaning commonly understood by those having ordinary skill in the art to which this invention belongs. Is done. Also, terms defined in commonly used dictionaries are not ideally or over-interpreted unless specifically defined herein.

  Hereinafter, a liquid crystal display device will be described as an example of a display device. However, the present invention is not limited to this, and a display device using a plasma display panel (PDP) or an organic light emitting diode (OLED). The present invention may be applied to all display devices.

  Hereinafter, a liquid crystal display device according to a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is a perspective view schematically showing a pixel portion of the liquid crystal display device according to the embodiment of the present invention shown in FIG.

  As shown in FIG. 1, the liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel assembly 300, a gate driver 400, a data driver 500, a gray voltage generator 800, and a signal controller 600.

  When viewed from the equivalent circuit, the liquid crystal display panel assembly 300 includes a plurality of signal lines and a plurality of pixels PX connected to the signal lines and arranged in a matrix. On the other hand, when viewed from the structure shown in FIG. 2, the liquid crystal display panel assembly 300 includes the lower display panel 100 and the upper display panel 200 facing each other, and the liquid crystal layer 3 sandwiched therebetween.

The signal lines include a plurality of gate lines G _{1 to} G _n for transmitting gate signals (also referred to as “scanning signals”), a plurality of data lines D _{1 to} D _m for transmitting data voltages, and storage electrode lines (not shown). Z). The gate lines G _{1 to} G _n and the storage electrode lines extend in the row direction and are substantially parallel to each other, and the data lines D _{1 to} D _m extend in the column direction and are substantially parallel to each other.

Each pixel PX includes a pair of sub-pixels, and each of the pair of sub-pixels includes liquid crystal capacitors Clca and Clcb. At least one of the two sub-pixels includes gate lines G _{1 to} G _n , data lines D _{1 to} D _m , and switching elements (not shown) connected to the liquid crystal capacitors Clca and Clcb.

  The liquid crystal capacitor Clca / Clcb has a sub-pixel electrode PEa / PEb of the lower display panel 100 and a common electrode CE of the upper display panel 200 as two terminals, and a liquid crystal layer between the sub-pixel electrode PEa / PEb and the common electrode CE. 3 functions as a dielectric. The pair of subpixel electrodes PEa / PEb are separated from each other and form one pixel electrode PE. The common electrode CE is formed on the entire surface of the upper display panel 200 and receives a common voltage Vcom. The liquid crystal layer 3 has a negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 are aligned so that the major axis is perpendicular to the surfaces of the two display panels 100 and 200 in the absence of an electric field. May be. Unlike FIG. 2, the common electrode CE may be provided on the lower display panel 100, and at this time, at least one of the two electrodes PE and CE may be linear or rod-shaped.

  On the other hand, in order to realize color display, each pixel PX uniquely represents one of the primary colors (primary color) (space division), or each pixel PX alternately represents the basic color according to time. (Time division) so that the desired color is recognized by the spatial and temporal summation of these basic colors. Examples of basic colors include three primary colors such as red, green, and blue. FIG. 2 shows that each pixel PX includes a color filter CF representing one of the basic colors in the area of the upper display panel 200 as an example of space division. Unlike FIG. 2, the color filter CF may be formed on or below the sub-pixel electrodes PEa and PEb of the lower display panel 100.

  At least one polarizer (not shown) for polarizing light may be attached to the outer surface of the liquid crystal display panel assembly 300.

  Referring to FIG. 1 again, the gray voltage generator 800 generates a whole gray voltage or a limited number of gray voltages (hereinafter referred to as “reference gray voltages”) related to the transmittance of the pixel PX. The (reference) gradation voltage may include one having a positive value and one having a negative value with respect to the common voltage Vcom.

The gate driver 400 is connected to the gate lines G _{1 to} G _n of the liquid crystal display panel assembly 300 and applies a gate signal formed by a combination of the gate-on voltage Von and the gate-off voltage Voff to the gate lines G _{1 to} G _n .

Data driver 500 is connected to the data lines _D 1 to D _m of the liquid crystal display panel assembly 300, selects a gray voltage from the gray voltage generator 800, the data lines _D 1 to D _m it as a data voltage Apply to. However, when the gray voltage generator 800 does not provide all gray voltages, but provides only a limited number of reference gray voltages, the data driver 500 divides the reference gray voltages to obtain desired data. Generate voltage.

  The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400 and 500 and the gray voltage generator 800 may be directly mounted on the liquid crystal display panel assembly 300 in the form of one or more integrated circuit chips, or may be a flexible printed circuit film (flexible). Mounted on a printed circuit film (not shown) and attached to the liquid crystal display panel assembly 300 in the form of a tape carrier package (TCP), or on a separate printed circuit board (not shown) It may be attached to. In contrast, the driving devices 400 and 500 may be integrated in the liquid crystal display panel assembly 300 together with the signal lines G _{1 to} G _n , D _{1 to} D _{m, the} thin film transistor switching element Q, and the like. In addition, the driving devices 400 and 500, the signal control unit 600, and the grayscale voltage generation unit 800 can be integrated on a single chip. It may be on the outside.

  FIG. 3 is an equivalent circuit diagram of one pixel in the liquid crystal display device according to the first embodiment of the present invention, and FIG. 4 is a layout diagram showing an example of a thin film transistor array panel of a liquid crystal display device having an equivalent circuit similar to FIG. It is.

3 and 4, the liquid crystal display according to the first embodiment of the present invention includes a plurality of gate lines G _i and G _{i + 1} that transmit scanning signals to a plurality of thin film transistors (TFTs). A plurality of data lines D _j and D _{j + 1} that cross the gate lines G _i and G _{i + 1} and transmit a data voltage to the thin film transistor, and a plurality of pixels connected to the gate lines G _i and G _{i + 1} and the data lines. Including.

  Each pixel includes a first subpixel SP1 and a second subpixel SP2. The first subpixel SP1 includes a first thin film transistor TFT1, a first liquid crystal capacitor Clc_H, and a first storage capacitor Cst_H. The second subpixel SP2 includes a second thin film transistor TFT2, a second liquid crystal capacitor Clc_L, and a second storage capacitor Cst_L.

The first thin film transistor TFT1 includes a gate electrode 113 connected to the gate lines G _i and 111, a source electrode 131 connected to the data lines D _j and 130, and a drain electrode 135 connected to the first pixel electrode 161 through the contact hole 173. And the first semiconductor layer 141. The first pixel electrode 161 forms the first liquid crystal capacitor Clc_H together with the common electrode CE (see FIG. 2) formed on the upper display panel 200, and the first electrode together with the sustain electrodes Com and 120 extending in parallel with the gate lines G _i and G _{i + 1} . One storage capacitor Cst_H is formed.

The second thin film transistor TFT2 includes a gate electrode 113 connected to the gate lines G _i and 111, a source electrode 132 connected to the source electrode 131, a drain electrode 136 connected to the second pixel electrode 162 through the contact hole 174, and a second electrode. 2 semiconductor layers 142. The second pixel electrode 162 forms a second liquid crystal capacitor Clc_L together with the common electrode CE, and forms a second storage capacitor Cst_L together with the sustain electrode 120.

  The first storage capacitor Cst_H is formed between the first auxiliary electrode 152 and the sustain electrode 120, and the second storage capacitor Cst_L is formed between the second auxiliary electrode 151 and the sustain electrode 120. The first auxiliary electrode 152 is connected to the first pixel electrode 161 through the contact hole 172, and the second auxiliary electrode 151 is connected to the second pixel electrode 162 through the contact hole 171.

Each pixel further includes a third thin film transistor TFT3, a fourth thin film transistor TFT4, and a charge distribution capacitor Cboost. The third thin film transistor TFT3 includes a gate electrode 113 connected to the gate lines G _i and 111, a source electrode 133, a drain electrode 137, and a third semiconductor layer 143. The source electrode 133 is connected to the coupling electrode 153 that overlaps the first pixel electrode 161 to form the charge distribution capacitor Cboost, and the drain electrode 137 is connected to the sustain electrode 120.

Fourth thin film transistor TFT4 includes gate lines _{G i + 1} and connected to the gate electrode 114 of the next stage adjacent to the gate line _{G i,} a source electrode 134, drain electrode 138, and a fourth semiconductor layer 144. The source electrode 134 is connected to the coupling electrode 153, and the drain electrode 138 is connected to the second pixel electrode 162 through the contact hole 177.

  The first to fourth semiconductor layers 141, 142, 143, and 144 may be formed of one of amorphous silicon, polycrystalline silicon, or single crystal silicon.

  The data voltage charged in the first liquid crystal capacitor Clc_H and the second liquid crystal capacitor Clc_L controls the alignment direction of the liquid crystal molecules between the first pixel electrode 161 and the second pixel electrode 162 and the common electrode CE. In addition, the first storage capacitor Cst_H and the second storage capacitor Cst_L serve to maintain voltages charged in the first liquid crystal capacitor Clc_H and the second liquid crystal capacitor Clc_L during one frame. The sustain electrode 120 may be applied with a fixed voltage such as the common voltage Vcom.

  The charge distribution capacitor Cboost is formed of a coupling electrode 153 formed on the sustain electrode 120, a first pixel electrode 161, and a protective layer (not shown). The liquid crystal display according to the first embodiment of the present invention increases the aperture ratio by forming the coupling electrode 153 on the sustain electrode 120 made of an opaque metal such as a metal layer forming a gate electrode.

  The charge distribution capacitor Cboost and the third thin film transistor TFT3 enhance the side visibility of the liquid crystal display device by decreasing the voltage charged in the second liquid crystal capacitor Clc_L and increasing the voltage charged in the first liquid crystal capacitor Clc_H. To do.

  When a gate-on voltage is applied to the first gate line 111, the first thin film transistor to the third thin film transistor TFT1 to TFT3 are turned on simultaneously, and the same data voltage is applied to the first pixel electrode 161 and the second pixel electrode 162, and the cup A common voltage Vcom is applied to the ring electrode 153. Further, the charge distribution capacitor Cboost is charged with a voltage corresponding to the voltage difference between the first pixel electrode 161 and the coupling electrode 153.

  Thereafter, when a gate-off voltage is applied to the first gate line 111, the first subpixel SP1 and the second subpixel SP2 are electrically separated from each other.

  At the same time, when a gate-on voltage is applied to the second gate line 112, the fourth thin film transistor TFT4 is turned on, the second pixel electrode 162 and the coupling electrode 153 are connected, and the second pixel electrode 162 and the coupling electrode are connected. The voltage at 153 is the same. Accordingly, the first pixel electrode 161 and the second pixel electrode 162 having the same voltage have different voltages.

  Hereinafter, a change in voltage generated in the first pixel electrode 161 and the second pixel electrode 162 based on the charge conservation law will be described in more detail.

  Referring to FIG. 3, the first node N1 is a node between the output terminal of the first thin film transistor TFT1 and the charge distribution capacitor Cboost, and the second node N2 is between the output terminal of the second thin film transistor TFT2 and the fourth thin film transistor TFT4. The third node N3 is a node between the charge distribution capacitor Cboost and the output terminal of the fourth thin film transistor TFT4.

When the gate-on voltage is applied through the first gate line _{G i,} the data voltage Vd is applied to the first node N1 and the second node N2 via the first thin film transistor TFT1 and the second thin film transistor TFT 2. Then, the common voltage Vcom is applied to the third node N3 through the third thin film transistor TFT3. For convenience of explanation, when the common voltage Vcom is assumed to be 0V, Vd is applied to the first node N1 and the second node N2, and 0V is applied to the third node N3.

According to the charge conservation law, the charge amount Qh charged in the first liquid crystal capacitor Clc_H and the first storage capacitor Cst_H, the charge amount Ql charged in the second liquid crystal capacitor Clc_L and the second storage capacitor Cst_L, and the charge distribution capacitor Cboost are charged. The charged amount Qb is as shown in [Formula 1] below.
(Here, Ch = Clc_H + Cst_H, Cl = Clc_L + Cst_L, Cb is the capacitance of the charge distribution capacitor.)

Next, the gate-off voltage is applied to the first gate line _{G i,} the gate-on voltage is applied to the second gate line _{G i + 1,} the first thin film transistor to third TFT TFT1~TFT3 becomes off state, the fourth thin film transistor The TFT 4 is turned on.

The charge amount Qh ′ of the first liquid crystal capacitor Clc_H and the first storage capacitor Cst_H, the charge amount Ql ′ of the second liquid crystal capacitor Clc_L and the second storage capacitor Cst_L, and the charge amount Qb ′ of the charge distribution capacitor Cboost are used as a charge conservation law. Based on the following [Equation 2].
(Here, V1 is a voltage applied to the first node N1, and V2 is a voltage applied to the second node N2.)

Since the total charge amount charged in the first liquid crystal capacitor Clc_H, the first storage capacitor Cst_H, and the charge distribution capacitor Cboost connected to the first node N1 is stored, the following [Equation 3] is obtained.

Further, since the total charge amount charged in the second liquid crystal capacitor Clc_L, the second storage capacitor Cst_L, and the charge distribution capacitor Cboost connected to the third node N3 is also stored, the following [Equation 4] is obtained. .

According to Equations 1 to 4, voltages V1 and V2 of the first node N1 and the third node N3 are as shown in [Formula 5] below.

  When the data voltage Vd is a positive voltage greater than the common voltage Vcom, the pixel voltage V1 of the first subpixel SP1 rises above the data voltage Vd, and the pixel voltage V2 of the second subpixel SP2 falls below the data voltage Vd. The opposite is true when the data voltage Vd is a negative voltage smaller than the common voltage Vcom. Therefore, the absolute value of the pixel voltage V1 of the first subpixel SP1 is always larger than the absolute value of the pixel voltage V2 of the second subpixel SP2.

  As described above, when the pixel voltages V1 and V2 of the first subpixel SP1 and the second subpixel SP2 located in one pixel have different values, the side visibility can be improved. That is, a pair of gradation voltages having different gamma curves obtained from one video information is stored in the first subpixel SP1 and the second subpixel SP2, and the first subpixel SP1 and the second subpixel SP2 The gamma curve of one pixel is a gamma curve obtained by combining these. When determining a pair of gray voltage sets, the front-side composite gamma curve should be close to the front-side reference gamma curve, and the side-side composite gamma curve should be closest to the front-side reference gamma curve. Thereby, side visibility can be improved.

  FIG. 5 is a cross-sectional view of the first storage capacitor Cst_H and the second storage capacitor Cst_L along the line V-V ′ shown in FIG. 4.

  The sustain electrode 120 is formed on the lower substrate with the same metal as the gate lines 111 and 112. The first auxiliary electrode 152 and the second auxiliary electrode 151 are made of the same metal as the data line 130 and are formed to be insulated from the sustain electrode 120 with the gate insulating film GI interposed therebetween. The gate insulating film GI is formed of silicon nitride (SiNx) or silicon oxide (SiOx).

  The coupling electrode 153 is also formed of the same metal as the data line 130 on the gate insulating film GI. The protective film is formed on the first auxiliary electrode 152, the second auxiliary electrode 151, and the coupling electrode 153, and is formed of silicon nitride (SiNx) or silicon oxide (SiOx).

  A first contact hole 172 and a second contact hole 171 are formed in the protective film, whereby the first pixel electrode 161 and the second pixel electrode 162 are connected to the first auxiliary electrode 152 and the second auxiliary electrode 151.

  The first storage capacitor Cst_H includes the first auxiliary electrode 152, the sustain electrode 120, and the gate insulating film GI, and the second storage capacitor Cst_L includes the second auxiliary electrode 151, the sustain electrode 120, and the gate insulating film GI. Is done.

  The first storage capacitor Cst_H and the second storage capacitor Cst_L are formed by omitting the first auxiliary electrode 151 and the second auxiliary electrode 152 and interposing the first pixel electrode 161, the second pixel electrode 162, and the sustain electrode 120, respectively. May be.

  The first pixel electrode 161 and the second pixel electrode 162 are formed on the protective layer and may be formed of indium tin oxide (ITO) or indium zinc oxide (IZO).

  The charge distribution capacitor Cboost is formed between the first pixel electrode 161 and the coupling electrode 153 formed on the sustain electrode 120.

  FIG. 6 shows a connection structure between the drain electrode 137 and the sustain electrode 120 of the third thin film transistor TFT3.

  The drain electrode 137 of the third thin film transistor TFT3 formed in the same layer as the data metal line and the sustain electrode 120 formed in the same layer as the gate metal line are electrically connected to each other by the connection electrode 163. The connection electrode 163 is formed on the protective film including the third contact hole 175 and the fourth contact hole 176. The connection electrode 163 is connected to the drain electrode 137 and the sustain electrode 120 of the third thin film transistor TFT3 through the third contact hole 175 and the fourth contact hole 176. The connection electrode 163 may be formed using the same material as the first pixel electrode 161 and the second pixel electrode 162.

  Next, a liquid crystal display device according to a second embodiment of the present invention will be described in detail with reference to FIGS.

The liquid crystal display according to the second embodiment of the present invention includes a plurality of gate lines G _i and G _{i + 1} that transmit scanning signals to a plurality of thin film transistors, and a plurality of data lines D that transmit video signals across the gate lines. _j , D _{j + 1} and a plurality of pixels connected to the adjacent gate lines G _i , G _{i + 1} and the plurality of data lines D _j , D _{j + 1} .

  Each pixel includes a first subpixel SP1 and a second subpixel SP2. The first subpixel includes a first thin film transistor TFT1 and a first liquid crystal capacitor Clc_H, and the second subpixel includes a second thin film transistor TFT2, a second liquid crystal capacitor Clc_L, and a storage capacitor Cst_L.

  Compared with the first embodiment of the present invention, the liquid crystal display device according to the second embodiment of the present invention increases the voltage difference between the first sub-pixel SP1 and the second sub-pixel SP2 to improve the side visibility. For further improvement, the first storage capacitor Cst_H is omitted.

Referring to the following [Equation 6] calculated based on the law of conservation of charge, when the total charge amount Ch of the first subpixel SP1 decreases, the voltage of the first node N1 increases and the voltage of the third node N3 increases. Can be seen to decrease. That is, the omission of the first storage capacitor Cst_H increases the voltage difference between the first subpixel SP1 and the second subpixel SP2, thereby improving the side visibility.

  The sustain electrode 120 includes a first portion 121 located below the second pixel electrode 162 and a second portion 122 narrower than the first portion 121 and located below the first pixel electrode 161. The first portion 121 of the sustain electrode 120 overlaps with the second pixel electrode 162 to form a second storage capacitor Cst_L. The second portion 122 of the sustain electrode 120 also overlaps with the first pixel electrode 161 to form a storage capacitor. However, since the size thereof is smaller than that of the second storage capacitor Cst_L, it can be ignored. (Exaggerated in the drawing.)

The first TFT TFT1 includes a gate electrode 113 connected to the gate line _{G i,} a source electrode 131 connected to the data line _{D j,} the contact hole 173 by the drain electrode 135 is connected to the first pixel electrode 161, and the first A semiconductor layer 141 is included. The first pixel electrode 161 forms a first liquid crystal capacitor Clc_H together with the common electrode CE formed on the upper display panel 200. The second thin film transistor TFT2 includes a gate electrode 113 connected to the gate line _{G i,} a source electrode 131 connected to the source electrode 131, drain electrode 136 is connected to the second pixel electrode 162 through a contact hole 174, and the second semiconductor Layer 142 is included. The second pixel electrode 162 forms the second liquid crystal capacitor Clc_L together with the common electrode CE formed on the upper substrate 200, and forms the sustain electrodes Com and 120 and the second storage capacitor Cst_L.

  The second storage capacitor Cst_L may be formed between the auxiliary electrode 154 and the sustain electrodes Com and 120 in order to increase the charge capacity. At this time, the auxiliary electrode 154 is connected to the second pixel electrode 162 through the contact hole 178 and is formed on the first portion of the sustain electrode 120.

  Each pixel further includes a third thin film transistor TFT3, a fourth thin film transistor TFT4, and a charge distribution capacitor Cboost.

The third thin film transistor TFT3 includes a gate electrode 113 connected to the gate lines G _i and 111, a source electrode 133, a drain electrode 137, and a third semiconductor layer 143. The source electrode 133 is connected to the connection electrode 163 that overlaps with the first pixel electrode 161 and forms the charge distribution capacitor Cboost.

The fourth thin film transistor TFT4 includes a gate electrode 114, a source electrode 134, a drain electrode 138 and a fourth semiconductor layer 144 connected to the gate line Gi _{+ 1} . The source electrode 134 is connected to the coupling electrode 153, and the drain electrode 138 is connected to the second pixel electrode 162 through the contact hole 177.

  The first to fourth semiconductor layers 141, 142, 143, and 144 may be formed of amorphous silicon, polycrystalline silicon, or single crystal silicon.

  The charge distribution capacitor Cboost is formed of a coupling electrode 153, a first pixel electrode 161, and a protective layer. By forming the coupling electrode 153 on the sustain electrode 120 made of an opaque metal, the aperture ratio of the pixel can be increased.

  The charge distribution capacitor Cboost and the third thin film transistor TFT3 decrease the voltage charged in the second liquid crystal capacitor Clc_L and increase the voltage charged in the first liquid crystal capacitor Clc_H, thereby enhancing the side visibility of the liquid crystal display device.

  When a gate-on voltage is applied to the first gate line 111, the first to third thin film transistors TFT1 to TFT3 are simultaneously turned on, and the same data voltage is applied to the first pixel electrode 161 and the second pixel electrode 162, and coupling is performed. A common voltage Vcom is applied to the electrode 153. Further, the charge distribution capacitor Cboost is charged with a voltage corresponding to a voltage difference between the first pixel electrode 161 and the coupling electrode 153.

  Thereafter, when a gate-off voltage is applied to the first gate line 111, the first subpixel SP1 and the second subpixel SP2 are electrically separated from each other.

  At the same time, when a gate-on voltage is applied to the second gate line 112, the fourth thin film transistor TFT4 is turned on and the charge voltages of the second pixel electrode 162 and the coupling electrode 153 become the same. Accordingly, the first pixel electrode 161 and the second pixel electrode 162 having the same voltage have different voltages.

  As described above, in the liquid crystal display device according to the second embodiment of the present invention, the storage capacitor of the first subpixel SP1 is omitted, and thereby the difference between the voltage of the first subpixel SP1 and the voltage of the second subpixel SP2. The side visibility is further improved by further increasing.

  If necessary, the storage capacitor of the second subpixel SP2 can be reduced to further increase the difference between the voltage of the first subpixel SP1 and the voltage of the second subpixel SP2 in order to improve the side visibility.

  FIG. 9 is a cross-sectional view of the second storage capacitor Cst_L and the charge distribution capacitor Cboost along the line IX-IX ′ in FIG. 8.

  The sustain electrode 120 is formed in the same layer as the gate metal line, and the auxiliary electrode 154 is formed in the same layer as the data metal line. The sustain electrode 120 and the auxiliary electrode 154 are insulated from each other by the gate insulating film GI. The gate insulating film GI is formed of silicon nitride (SiNx) or silicon oxide (SiOx).

  The coupling electrode 153 is formed on the gate insulating film GI and includes a data metal layer.

  The second pixel electrode 162 is connected to the auxiliary electrode 154 through a contact hole 178 formed in the protective film.

  The second storage capacitor Cst_L includes the auxiliary electrode 154, the sustain electrode 120, and the gate insulating film GI.

  The first pixel electrode 161 and the second pixel electrode 162 are formed on the protective film, and are formed of transparent indium tin oxide (ITO) or indium zinc oxide (IZO).

  The charge distribution capacitor Cboost is formed by a coupling electrode 153 formed on the first pixel electrode 161 and the sustain electrode 120.

  FIG. 10 shows a connection structure between the drain electrode 137 and the sustain electrode 120 of the third thin film transistor TFT3 and is almost the same as FIG.

  In the liquid crystal display device according to the second embodiment as well as the liquid crystal display device according to the first embodiment of the present invention, the drain electrode of the third thin film transistor TFT3 in the same layer as the data metal line is connected to the gate metal line through the connection electrode 163. It is connected to the sustain electrode 120 of the same layer. The connection electrode 163 is formed on the protective film including the third contact hole 175 and the fourth contact hole 176. The drain electrode and the sustain electrode 120 of the third thin film transistor TFT 3 are connected to the connection electrode 163 through the third contact hole 175 and the fourth contact hole 176. The connection electrode 163 is made of the same transparent metal as the first pixel electrode 161 and the second pixel electrode 162.

  The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention modifies the technical idea and the essential features of those who have ordinary knowledge in the technical field to which the present invention belongs. It can be understood that the present invention can be implemented in other specific forms. Accordingly, the above-described embodiments are illustrative and not limiting.

3 Liquid crystal layer 100 Lower display panel 111, 112 Gate line 120 Sustain electrode 130 Data line 141-144 Semiconductor layer 151 Second auxiliary electrode 152 First auxiliary electrode 153 Coupling electrode 161 First pixel electrode 162 Second pixel electrode 163 Coupling electrode 171 to 177 Contact hole

Claims (9)

A first gate line and a second gate line;
A data line intersecting the first gate line and the second gate line;
A plurality of pixels connected to the first gate line, the second gate line and the data line and arranged in a matrix;
Each of the pixels
A first pixel electrode;
A first thin film transistor connected to the first gate line, the data line, and the first pixel electrode;
A second pixel electrode;
A second thin film transistor connected to the first gate line, the data line, and the second pixel electrode;
A sustain electrode;
Forming a charge distribution capacitor overlapping the first pixel electrode, and a coupling electrode formed on the sustain electrode;
A third thin film transistor connected to the first gate line , the sustain electrode , and the coupling electrode ;
Before Stories second gate line, the coupling electrode, and a fourth thin film transistor connected to the second pixel electrode,
A display device comprising: Before SL fourth thin film transistor, a display device according to claim 1, characterized in that it comprises a source electrode connected to the coupling electrode, and a drain electrode connected to the second pixel electrode. Wherein the drain electrode of the third thin film transistor, a display device according to claim 2, characterized in that connected to the sustain electrode through the connection electrodes.   The display device according to claim 3, wherein the drain electrode and the sustain electrode of the third thin film transistor are formed of different metals in different layers.   The display device according to claim 3, wherein the connection electrode overlaps with an incision portion of the pixel electrode. The display of claim 1, wherein the sustain electrode overlaps with the first pixel electrode to form a first storage capacitor, and overlaps with the second pixel electrode to form a second storage capacitor. apparatus. A first auxiliary electrode forming the sustain electrode and the first storage capacitor and connected to the first pixel electrode through a first contact hole;
The display device according to claim 6 , further comprising: a second auxiliary electrode that forms the sustain electrode and the second storage capacitor and is connected to the second pixel electrode through a second contact hole. The sustain electrode is
A first portion forming a second storage capacitor overlapping the second pixel electrode;
The overlaps the first pixel electrode forming a first storage capacitor, the display device according to claim 1, characterized in that a narrow second portion, width than the first portion. An auxiliary electrode that overlaps with the first portion of the sustain electrode to form the second storage capacitor;
Before Kiho display device according to claim 8 assistant electrode, characterized in that connected to the second pixel electrode via a contact hole.