KR101660979B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of improving a contrast ratio of a display image.

This liquid crystal display device includes a liquid crystal display panel; A backlight unit including a plurality of light source blocks for emitting light to the liquid crystal display panel; A backlight control circuit for determining a dimming value for each block for controlling the light source blocks and generating a light source data signal corresponding to the light source scan signal and the dimming value for each block, And a backlight driving circuit including a plurality of light source drivers for generating a driving current to be supplied to each of the light source blocks.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device capable of improving a contrast ratio of a display image.

BACKGROUND ART [0002] Liquid crystal display devices are becoming increasingly widespread due to features such as light weight, thinness, and low power consumption driving. This liquid crystal display device is used as a portable computer such as a notebook PC, an office automation device, an audio / video device, and an indoor / outdoor advertisement display device. A liquid crystal display device displays an image using a thin film transistor (hereinafter referred to as "TFT") as a switching element. A transmissive liquid crystal display device that occupies most of the liquid crystal display device displays an image by controlling an electric field applied to the liquid crystal layer to modulate light incident from the backlight unit.

The image quality of the liquid crystal display device depends on the contrast characteristics. In order to improve the contrast characteristic, a local dimming method of locally adjusting the brightness of the backlight according to an image has been proposed. The local dimming method divides the backlight into multiple blocks and adjusts the dimming value for each block to increase the backlight luminance of the bright block, while reducing the backlight luminance of the dark block.

In order to realize such a local dimming method, a light source control integrated circuit for driving backlight light sources in block units is required. Since one light source block is driven per one channel, the light source driving integrated circuit must have the number of channels corresponding to the number of light source blocks. The number of light source blocks is increasingly increasing in accordance with tendency toward large-sized and high resolution, and accordingly, a large number of light source control integrated circuits are required. For example, 32 light source control integrated circuits having 16 channels are required corresponding to 512 light source blocks.

In recent years, various attempts have been made to reduce the number of light source control integrated circuits, but these methods have the side effect of failing to stably supply driving current to the light source blocks.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a liquid crystal display device capable of reducing the number of light source control integrated circuits for driving backlight light sources in block units.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal display panel; A backlight unit including a plurality of light source blocks for emitting light to the liquid crystal display panel; A backlight control circuit for determining a dimming value for each block for controlling the light source blocks and generating a light source data signal corresponding to the light source scan signal and the dimming value for each block, And a backlight driving circuit including a plurality of light source drivers for generating a driving current to be supplied to each of the light source blocks.

The light source driving units are connected to the row signal lines to which the light source scan signals are sequentially applied and the column signal lines to which the light source data signals are applied to form a matrix.

Each of the light source driving units includes a current mirror unit including first and second mirror elements and a capacitor to generate the driving current corresponding to a control current; A first selector for selectively outputting a logic power voltage and a ground voltage in response to the light source scan signal; A second selector for selectively outputting a reference voltage and a ground voltage in response to the light source data signal; A first switch element responsive to an output of the first selector and a third switch element switched in response to an output of the second selector to turn on and off the first and second mirror elements, A switching unit for controlling a turn-off operation; And a current generator including a buffer and a resistance element for generating the control current.

Wherein the first mirror element has a gate electrode connected to a first node, a source electrode connected to an input terminal of a logic power supply voltage, a drain electrode connected to the first node, One end of the capacitor is connected to the input terminal of the logic power supply voltage, the other end of the capacitor is connected to the other end of the capacitor, Wherein the second mirror element forms a current mirror with the first mirror element, a gate electrode is connected to the second node, a source electrode is connected to an input terminal of the logic power voltage, and one of the light source blocks Drain electrodes are connected.

Wherein the first switch element has a gate electrode connected to the output terminal of the first selector, a source electrode connected to the first node, and a drain electrode connected to the second node; The second switch element has a gate electrode connected to the output terminal of the first selector, a source electrode connected to the first node, and a drain electrode connected to the third node; The third switch element has a gate electrode connected to the output terminal of the second selector, a drain electrode connected to the third node, and a source electrode connected to the fourth node.

The buffer has a first input terminal (+) connected to the output terminal of the second selector, a second input terminal (-) connected to the fourth node, an output terminal connected to the gate electrode of the third switch element ; And the resistance element is connected between the fourth node and the input terminal of the ground voltage.

Wherein the first and second mirror elements and the first and second switch elements are implemented as a P-type MOSFET; The third switch element is implemented as an N-type MOSFET.

Wherein the backlight control circuit comprises: a dimming value determining unit for determining a dimming value for each block based on an analysis result of input digital video data; A light source scan controller for generating the light source scan signal swinging between a high logic level and a low logic level at regular intervals; A light source data control unit for generating the light source data signal swinging between a high logic level and a low logic level at regular intervals; And a driving voltage supply unit for adjusting the input voltage to generate the logic power supply voltage and the reference voltage.

A lighting duty of the light source blocks is determined by the light source data signal; As the high logic level width of the light source data signal is widened within one period, the time for applying the driving current to the light source blocks becomes longer.

The liquid crystal display device according to the present invention may be configured such that when the light sources of the backlight are driven block by block for local dimming, the light source driving units of the matrix type correspond to the light source blocks one-to- The number of the light source control integrated circuits can be greatly reduced compared to the conventional one by selecting the light source driver in synchronization.

Further, the liquid crystal display according to the present invention may be configured such that each light source driving unit includes the current mirror unit, the switching unit, the selecting unit, and the current generating unit, and the connection configuration of the switching unit is appropriately selected, The driving current can be stably supplied to the light source blocks even if the gate potential of the light source blocks is increased.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 1 to 6. FIG.

1 shows a liquid crystal display according to an embodiment of the present invention.

1, a liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, a backlight control circuit 14, A backlight driving circuit 15, and a backlight unit 16. [

The liquid crystal display panel 10 includes two glass substrates and a liquid crystal layer formed therebetween. A plurality of data lines DL and a plurality of gate lines GL are intersected with each other on a lower glass substrate of the liquid crystal display panel 10. [ The liquid crystal cells Clc are arranged in a matrix form in the liquid crystal display panel 10 by the intersection structure of the data lines DL and the gate lines GL. Each of the liquid crystal cells Clc includes a TFT, a pixel electrode 1 connected to the TFT, and a storage capacitor Cst. On the upper glass substrate of the liquid crystal display panel 10, a black matrix, a color filter, a common electrode 2, and the like are formed. The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for forming a pre-tilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

The timing controller 11 arranges the digital video data RGB input from the system board on which the external video source is mounted according to the resolution of the liquid crystal display panel 10 and supplies the digital video data RGB to the data driving circuit 12.

The timing controller 11 generates timing control signals for controlling the operation timings of the data driving circuit 12 and the gate driving circuit 13 based on the timing signals Vsync, Hsync, DE, DCLK from the system board DDC, GDC). The timing controller 11 inserts an interpolation frame between the frames of the input video signal input at a frame frequency of 60 Hz and multiplies the data timing control signal DDC and the gate timing control signal GDC to obtain 60 × N The operation of the data driving circuit 12 and the gate driving circuit 13 can be controlled with a frame frequency of Hz or more.

The data driving circuit 12 latches the digital video data RGB in response to the data timing control signal DDC and outputs the latched data to the positive / negative polarity analog data And then supplies the data to the data lines DL. To this end, the data driving circuit 12 includes a shift register for temporarily sampling the clock signal, a register for temporarily storing the digital image data (RGB), a buffer for storing data for one line in response to the clock signal from the shift register, For selecting a positive / negative gamma voltage under reference to a gamma reference voltage corresponding to a digital data value from a latch and a latch for simultaneously outputting data of a line and a negative data voltage, A multiplexer for selecting a data line DL to which a positive polarity / negative polarity data voltage is supplied, and an output buffer connected between the multiplexer and the data line DL.

The gate drive circuit 13 sequentially outputs gate pulses in response to the gate timing control signal GDC and supplies the gate pulses to the gate lines GL to select a horizontal line to which the data voltage is to be applied. To this end, the gate drive circuit 13 includes a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving the TFT of the liquid crystal cell, and an output buffer.

The backlight control circuit 14 determines the block-by-block dimming value Ldim for controlling the light sources of the backlight unit 16 on a block-by-block basis based on the analysis result of the input digital video data RGB, And the light source data signal Ldata according to the block-specific dimming value Ldim. Then, an input power source is adjusted to generate driving voltages Vcc and Vref necessary for driving the light sources.

The backlight driving circuit 15 drives the light sources block by unit using the light source scan signal Lscan, the light source data signal Ldata, and the driving voltages Vcc and Vref input from the backlight control circuit 14. [ The backlight driving circuit 15 includes a plurality of light source drivers corresponding one-to-one to the light source blocks.

The backlight unit 16 includes a plurality of light sources, and divides the surface light source irradiated on the liquid crystal display panel 10 into blocks in the form of a matrix. The light sources may be realized by point light sources such as a light emitting diode (LED). As shown in FIG. 2, the light sources may be driven in a block unit (LS11 to LSnm) in the form of a matrix, and the light sources may be connected in series to each other in a string form. The backlight unit 16 may be implemented as either a direct type or an edge type. The direct-type backlight unit 16 has a structure in which a plurality of optical sheets and a diffusion plate are stacked under the liquid crystal display panel 10, and a plurality of light sources are disposed under the diffusion plate. The edge type backlight unit 16 has a structure in which a plurality of optical sheets and a light guide plate are stacked below a liquid crystal display panel 10 and a plurality of light sources are disposed on a side surface of the light guide plate.

3 shows the configuration of the backlight control circuit 14. In FIG.

3, the backlight control circuit 14 includes a dimming value determiner 141, a light source scan controller 142, a light source data controller 143, and a driving voltage supplier 144.

The dimming value determiner 141 analyzes the input digital video data RGB in the light source block units LS11 to LSnm in Fig. 2 to derive a representative value for each block. The representative value per block can be obtained by deriving the maximum gradation value among the RGB values of the pixels in each block and dividing the sum of the maximum values by the number of pixels included in the block. The dimming value determining unit 141 maps the representative value for each block to a preset dimming curve to determine a dimming value Ldim for each block. The dimming curve can be implemented as a look-up table. The dimming value Ldim for each block can be determined to be high in a block having a high representative value of data and low in a block having a low representative value.

The light source scan control unit 142 generates the light source scan signal Lscan. The light source scan signal Lscan is a signal swinging between the high logic level H2 and the low logic level L2 at regular intervals as shown in FIG. 4. The light source driving units LD11 to LDnm are connected And are sequentially applied to the row signal lines 151A.

The light source data controller 143 generates the light source data signal Ldata according to the dimming value Ldim for each block. The light source data signal Ldata is a signal swinging between a high logic level H1 and a low logic level L1 at regular intervals as shown in FIG. 4. The light source data signal Ldata is a signal to which the light source drivers LD11 to LDnm are connected And applied to the column signal lines 151B. The lighting duty of the light source blocks LS11 to LSnm is determined by the light source data signal Ldata. That is, as the width of the high logic level (H1) of the light source data signal Ldata increases within a period, the time for applying the driving current to the light source blocks LS11 to LSnm becomes longer, ) Increases.

The light source scan control unit 142 and the light source data control unit 143 may be implemented in the form of an integrated circuit and correspond to a conventional light source control integrated circuit. The light source data signal Ldata may be applied in synchronization with the light source scan signal Lscan. For example, the (i, j) th light source driver LDij for applying the driving current to the (i, j) th light source block LSij is supplied with the i th light source data signal Ldata Is applied. When the light source data signal Ldata and the light source scan signal Lscan are synchronized with each other and the corresponding light source driving unit is selected, the number of the light source scan control unit 142 and the light source data control unit 143 is compared with the number of the conventional light source control integrated circuits Can be greatly reduced. For example, while the conventional 16-channel light source control integrated circuit requires 32, the 16-channel light source scan control unit 142 and the 16-channel light source data control unit 143 are required to correspond to 512 light source blocks. It becomes sufficient.

The driving voltage supply unit 144 adjusts an input voltage Vin applied from the outside to generate a logic power supply voltage Vcc and a reference voltage Vref necessary for driving the light source blocks LS11 to LSnm.

Fig. 5 shows a connection configuration of the light source driver units LD11 to LDnm constituting the backlight driver circuit 15. Fig.

5, the light source drivers LD11 to LDnm are connected to the row signal lines 151A and the column signal lines 151B to form a matrix. The light source driving units LD11 to LDnm are connected to the light source blocks LS11 to LSnm on a one-to-one basis, respectively.

The light source driver units LD11 to LDnm are activated in response to the light source scan signal Lscan applied from the row signal lines 151A and then the light source driver units LD11 to LDnm are activated in response to the light source scan signal Lscan applied from the row signal lines 151A, And supplies the driving current Id to the light source blocks LS11 to LSnm in response to the signal Ldata.

6 shows a detailed configuration of the (i, j) th light source driver LDij for applying a driving current to the (i, j) th light source block LSij.

6, the light source driver LDij includes first and second mirror elements MT1 and MT2 forming a current mirror unit, a capacitor C, first to third switch elements ST1 to ST3 forming a switching unit, ), First and second selectors MUX1 and MUX2, and a buffer BUF and a resistance element R forming a current generator.

The current mirror portion includes first and second mirror elements MT1 and MT2 and a capacitor C to generate a driving current corresponding to the control current Ix. The first and second mirror elements MT1 and MT2 may be implemented as a P-type MOSFET.

The first mirror element MT1 is turned on by the activating operation of the switching part to set the source-gate voltage Vsg corresponding to the control current Ix. In the first mirror element MT1, a gate electrode G is connected to the first node N1, a source electrode S is connected to the input terminal of the logic power supply voltage Vcc, And the electrode D is connected. The gate electrode G and the drain electrode D of the first mirror element MT1 are shorted together to stably operate the first mirror element MT1 in a saturation state.

The capacitor C stores the source-gate voltage Vsg of the first mirror element MT1 in the activation operation of the switching part. In the capacitor C, one electrode is connected to the input terminal of the logic power supply voltage Vcc, and the other electrode is connected to the second node N2.

The second mirror element MT2 forms a current mirror with the first mirror element MT1 and is turned on by the source-gate voltage Vsg of the first mirror element MT1 stored in the capacitor C, (Id) substantially equal to the drive current Ix. Then, the driving current Id is supplied to the light source block LSij. The second mirror element MT2 has the gate electrode G connected to the second node N2, the source electrode S connected to the input terminal of the logic power supply voltage Vcc, (D) is connected.

The switching unit includes first and second switching devices ST1 and ST2 that are switched in response to the output of the first selector MUX1 and a third switching device ST3 that is switched in response to the output of the second selector MUX2. To turn on / off the first and second mirror elements MT1 and MT2. The first and second switch elements ST1 and ST2 may be implemented as a P-type MOSFET and the third switch element ST3 may be implemented as an N-type MOSFET.

The first switch element ST1 switches the electrical connection between the first node N1 and the second node N2 in response to the output of the first selector MUX1. The first switch element ST1 has a gate electrode G connected to the output terminal of the first selector MUX1, a source electrode S connected to the first node N1, a drain connected to the second node N2, And the electrode D is connected.

The second switch element ST2 switches the electrical connection between the first node N1 and the third node N3 in response to the output of the first selector MUX1. The second switch element ST2 has the gate electrode G connected to the output terminal of the first selector MUX1, the source electrode S connected to the first node N1, And the electrode D is connected.

The third switch element ST3 switches the electrical connection between the third node N3 and the fourth node N4 in response to the output of the second selector MUX2. The third switch element ST3 has the gate electrode G connected to the output terminal of the second selector MUX2, the drain electrode D connected to the third node N3, the source connected to the fourth node N4, And the electrode S is connected.

The first selector MUX1 selectively outputs the logic power supply voltage Vcc and the ground voltage GND input from the backlight control circuit in response to the light source scan signal Lscan. For example, while the first selector MUX1 outputs the ground voltage GND in response to the light source scan signal Lscan of the high logic level H2, the first selector MUX1 outputs the ground voltage GND in response to the light source scan signal Lscan of the low logic level L2 And can output the logic power supply voltage Vcc in response.

The second selector MUX2 selectively outputs the reference voltage Vref and the ground voltage GND input from the backlight control circuit in response to the light source data signal Ldata. For example, while the second selector MUX2 outputs the reference voltage Vref in response to the light source data signal Ldata of the high logic level H1, the second selector MUX2 outputs the reference voltage Vref to the light source data signal Ldata of the low logic level L1 It is possible to output the base low voltage (Gnd) in response.

The current generating section includes a buffer BUF and a resistance element R to generate a control current Ix.

The buffer BUF is connected to the fourth node N4 by using a second input terminal (-) which is virtual ground when the reference voltage Vref is input to the first input terminal (+), To generate a control current Ix flowing through the resistor R. The buffer BUF has a first input terminal (+) connected to the output terminal of the second selector MUX2, a second input terminal (-) connected to the fourth node N4, an output terminal connected to the third switch element ST3). ≪ / RTI > The resistor element R is connected between the fourth node N4 and the input terminal of the ground voltage Gnd.

The operation of the light source driver LDij will be briefly described below with reference to FIGS. 4 and 6. FIG.

The first and second switch elements ST1 and ST2 are turned on in response to the base voltage Gnd input from the first selector MUX1 by the light source scan signal Lscan of the high logic level H2. The third switch element ST3 is turned on in response to the reference voltage Vref input from the second selector MUX2 by the light source data signal Ldata of the high logic level H1. The first mirror element MT1 is turned on by turning on the first to third switch elements ST1 to ST3. As a result, the control current Ix flows through the first mirror element MT1. At both ends of the capacitor C, the saturation voltage corresponding to the control current Ix, that is, the source-gate voltage Vsg of the first mirror element MT1 is stored. The source-gate voltage Vsg stored in the capacitor C is maintained until the light source data signal Ldata is inverted from the high logic level H2 to the low logic level L2. The second mirror element MT2 generates a drive current Id substantially equal to the control current Ix by being turned on by the source-gate voltage Vsg of the first mirror element MT1. Then, the driving current Id is supplied to the light source block LSij.

The first and second switch devices ST1 and ST2 are turned off in response to the logic supply voltage Vcc input from the first selector MUX1 by the light source scan signal Lscan of the low logic level L2. The third switch element ST3 is turned off in response to the base voltage Gnd input from the second selector MUX2 by the light source data signal Ldata of the low logic level L1. The potential of the first node N1 is higher than the potential of the second switch element ST2 during a period in which the third switch element ST3 is kept in the on state after the first and second switch elements ST1 and ST2 are turned off, Can be increased by the reverse current that flows in the anode. If the potential rise of the first node N1 is reflected to the second node N2 as it is, the source-gate voltage Vsg stored in the capacitor C fluctuates and the light source data signal Ldata becomes the low logic level The driving current Id can be varied before being inverted by the driving current I1, so that the driving current Id can not be stably supplied for a desired period. As a result, the desired lighting duty can not be realized. However, even if the potential of the first node N1 is raised, since the electrical connection between the first and second nodes N1 and N2 is released by turning off the first switch element ST1, The source-gate voltage Vsg stored in the pixel C maintains the previous state stably until the light source data signal Ldata is inverted to the low logic level L1. As a result, the driving current Id can be stably supplied for a desired period, and the desired lighting duty can be easily realized.

As described above, the liquid crystal display device according to the present invention constitutes light source driving units of a matrix type corresponding to the light source blocks on a one-to-one basis when the light sources of the backlight are driven block by block for local dimming implementation, The number of the light source control integrated circuits can be largely reduced compared with the conventional one by selecting the light source driver in synchronism with the light source scan signals.

Further, the liquid crystal display according to the present invention may be configured such that each light source driving unit includes the current mirror unit, the switching unit, the selecting unit, and the current generating unit, and the connection configuration of the switching unit is appropriately selected, The driving current can be stably supplied to the light source blocks even if the gate potential of the light source blocks is increased.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

2 is a view showing light source blocks.

3 is a diagram showing a configuration of a backlight control circuit;

4 is a diagram showing waveforms of a light source scan signal and a light source data signal.

5 is a view showing a connection configuration of light source drivers;

6 is a view showing a detailed configuration of a (i, j) th light source driving unit for applying a driving current to the (i, j) th light source block.

Description of the Related Art

10: liquid crystal display panel 11: timing controller

12: data driving circuit 13: gate driving circuit

14: backlight control circuit 15: backlight driving circuit

16: backlight unit 141: dimming value determining unit

142: light source scan control unit 143: light source data control unit

144: Driving voltage supply unit

Claims (9)

A liquid crystal display panel; A backlight unit including a plurality of light source blocks for emitting light to the liquid crystal display panel; A backlight control circuit for determining a dimming value for each block for controlling the light source blocks and then generating a light source scan signal and a light source data signal according to the dimming value for each block; And And a backlight driving circuit including a plurality of light source drivers selected by the light source scan signal and the light source data signal to generate a driving current to be supplied to each of the light source blocks, Each of the light source driving units includes a current mirror unit that generates the driving current corresponding to the control current, The current mirror unit includes: A first mirror element having a gate electrode connected to a first node, a source electrode connected to an input terminal of a logic power supply voltage, and a drain electrode connected to the first node; A source electrode is connected to an input terminal of the logic power supply voltage, and a drain electrode is connected to one of the light source blocks, wherein the gate electrode is connected to the second node, Comprising a mirror element, Each of the light source drivers includes: A first selector for selectively outputting a logic power supply voltage and a ground voltage in response to the light source scan signal; A second selector for selectively outputting a reference voltage and a ground voltage in response to the light source data signal; A switching unit for controlling the operation of the current mirror unit in response to the output of the first selector and the output of the second selector; And a current generator for generating the control current. The method according to claim 1, Wherein the light source driving units are connected to a row signal line to which the light source scan signal is sequentially applied and a column signal line to which the light source data signal is applied to form a matrix. delete The method according to claim 1, The current mirror unit includes: And a capacitor having one end connected to the input terminal of the logic power supply voltage and the other end connected to the second node. The method according to claim 1, The switching unit includes: A first switch element having a gate electrode connected to an output terminal of the first selector, a source electrode connected to the first node, and a drain electrode connected to the second node; A second switch element having a gate electrode connected to the output terminal of the first selector, a source electrode connected to the first node, and a drain electrode connected to the third node; And And a third switch element having a gate electrode connected to the output terminal of the second selector, a drain electrode connected to the third node, and a source electrode connected to the fourth node. 6. The method of claim 5, Wherein the current- A buffer having a first input terminal (+) connected to the output terminal of the second selector, a second input terminal (-) connected to the fourth node, and an output terminal connected to the gate electrode of the third switch element; And And a resistance element connected between the fourth node and an input terminal of the ground voltage. 6. The method of claim 5, Wherein the first and second mirror elements and the first and second switch elements are implemented as a P-type MOSFET; And the third switch element is implemented as an N-type MOSFET. The method according to claim 1, The backlight control circuit comprising: A dimming value determination unit for determining a dimming value for each block based on an analysis result of input digital video data; A light source scan controller for generating the light source scan signal swinging between a high logic level and a low logic level at regular intervals; A light source data control unit for generating the light source data signal swinging between a high logic level and a low logic level at regular intervals; And And a driving voltage supply unit for adjusting the input voltage to generate the logic power supply voltage and the reference voltage. 9. The method of claim 8, A lighting duty of the light source blocks is determined by the light source data signal; Wherein a time period during which the driving current is applied to the light source blocks becomes longer as the width of the high logic level of the light source data signal increases within one period.

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