KR20110066513A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display is provided to improve the performance of a MPRT without changing the structure of an optical driving circuit. CONSTITUTION: In a liquid crystal display, an LCD panel is divided by a plurality of display sides to be driven. A scan pulse is supplied to the gate liens of first and second display sides in first direction. The scan pulse is supplied to the gate liens of third and fourth display sides in second direction. The second direction is opposite to the first direction. A data driving circuit supplies a data voltage to the data lines A backlight unit projects light to the LCD panel.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device capable of improving moving picture response time (MPRT) performance.

An active matrix liquid crystal display device displays a moving image using a thin film transistor (“TFT”) as a switching element. This liquid crystal display device is thinner and higher resolution than cathode ray tube ("CRT"), so it is applied to display in portable information equipment, office equipment, computer, etc., and is rapidly replacing CRT. .

However, in the liquid crystal display device, the moving picture response time characteristic (MPRT) is worse than the CRT in view of its driving characteristics. As shown in FIG. 1A, the CRT is an impulse type that emits a fluorescent material only for an initial very short time of one frame period to display an image, and maintains a non-display state for the rest of one frame period. Driven. The perceived image of the moving image felt by the viewer in the CRT becomes clear as shown in FIG. 1 (b) due to the driving of the impulse type. On the other hand, as shown in FIG. 2A, the liquid crystal display supplies data to the liquid crystal cell during the scanning period during one frame period, and holds the data to display an image even during the non-scanning period, which is the remaining time of one frame period. It is driven by a hold-type. As a result, in the liquid crystal display, due to the hold type characteristic, a motion blurring phenomenon in which a screen is not clear and blurry in a video as shown in FIG. 2 (b) or an afterimage of a previous screen remains on the current screen Due to the tailing phenomenon, MPRT performance is reduced.

In order to improve MPRT performance, a technique of driving an impulse driving the liquid crystal display by sequentially turning on the backlight in synchronization with video data displayed on the screen, that is, a scanning backlight driving method, has been proposed.

Referring to FIG. 3, a liquid crystal display device driven by a scanning backlight method includes light sources sequentially driven in units of blocks and an inverter 1 that applies driving power to the light sources. The light sources are electrically connected to the balance patterns 4 formed on the balance board 3 and are dividedly driven by the plurality of blocks BL1, BL2, BL3. The inverter 1 includes the number of transformers 2 corresponding to the light source blocks BL1, BL2, and BL3 to sequentially operate the transformers 2 in response to the light source scan signal SS input from the outside. . The transformers 2 are each electrically connected to the balance patterns 4 to apply light source driving power to the corresponding light source block. As shown in FIG. 4, the liquid crystal display turns on the light sources of the corresponding block at the optimal light source sync point. The light sources are sequentially turned on in block units so as to be synchronized with the data voltage Vdata sequentially charged from the top to the bottom of the display surface.

Usually, the optimal light source sink timing is determined when the data voltage Vdata is charged in the middle portion of the corresponding display surface. Therefore, the light source sync timing may be out of sync with the data charging timing in the upper and lower portions of each block, that is, the boundary portion between blocks. As the distance between the light source sync timing and the data charging timing shifts much, double lines or blurring may occur at the boundary between blocks. Considering the synchronization problem between the light source sync timing and the data charging timing, as the number of light source blocks is increased to decrease the display area of one block, that is, as the number of light source sync points for determining the light source sync timing is increased, The sync point can be synchronized more precisely with the data charging timing. However, the scanning backlight method requires a larger number of transformers 2 in order to subdivide the light source block, and thus it is difficult to meet the slimming trend and manufacturing cost of the liquid crystal display.

Accordingly, there is a need for a driving technology capable of reducing side effects at the boundary between blocks without mechanically changing the liquid crystal display.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of reducing side effects at the boundary portion between blocks while improving MPRT performance without changing mechanically.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel in which a plurality of gate lines and a plurality of gate lines intersect, and are divided into a plurality of display surfaces; Scan pulses are sequentially supplied to the gate lines of the first and second display surfaces of the liquid crystal display panel in a first direction, and the first and second gate lines of the gate lines of the third and fourth display surfaces of the liquid crystal display panel are provided. A gate driving circuit which sequentially supplies scan pulses along a second direction opposite to a direction, and alternately supplies the scan pulses to the display surfaces at regular intervals; A data driving circuit configured to supply a data voltage to the data lines in synchronization with the scan pulse; A backlight unit radiating light to the liquid crystal panel including a plurality of light sources; And a light source control circuit which simultaneously controls driving of the light sources by using a light source sync signal for synchronizing the turn-on time of the light sources with the completion time of charging the data voltage charged in a specific portion of the liquid crystal display panel.

According to an exemplary embodiment of the present invention, a scan pulse is sequentially supplied to gate lines of first and second display surfaces of a liquid crystal display panel in a first direction, and gates of the third and fourth display surfaces of the liquid crystal display panel are provided. The scan pulses are sequentially supplied to the lines in a second direction opposite to the first direction, and the LCDs are driven in block units by supplying scan pulses alternately to the display surfaces at regular intervals. Then, the light sources are turned on at the same time in synchronism with the completion of charging of the data voltage charged at the inter-block boundary. Accordingly, the liquid crystal display according to the present invention can greatly reduce the side effects at the boundary between blocks while improving MPRT performance without changing the light source driving circuit.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 10.

5 shows a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 5, a liquid crystal display according to an exemplary embodiment of the present invention may include a liquid crystal display panel 10, a data driving circuit 12 driving first and second data lines DL of the liquid crystal display panel 10, and first through second to third liquid crystal display panels. The gate driving circuit 13, the data driving circuit 12, and the gate driving circuit 13 which drive the gate lines GL of the liquid crystal display panel 10 including the fourth gate drivers 13A to 13D are controlled. A timing controller 11, a backlight unit 16 for irradiating light to the liquid crystal display panel 10 including a plurality of light sources, a light source control circuit 14 for generating a light source control signal SS, and light source control And a light source driving circuit 15 for flashing the light sources according to the signal SS. Here, the flashing driving means driving driving all the light sources on and off at the same time.

The liquid crystal display panel 10 includes two glass substrates and a liquid crystal layer formed therebetween. A plurality of data lines DL and a plurality of gate lines GL cross on the lower glass substrate of the liquid crystal display panel 10. The liquid crystal cells Clc are arranged in a matrix form on the liquid crystal display panel 10 due to the cross structure of the data lines DL and the gate lines GL. In addition, a thin film transistor TFT, a pixel electrode 1 of a liquid crystal cell Clc connected to the thin film transistor TFT, a storage capacitor Cst, and the like are formed on a lower glass substrate of the liquid crystal display panel 10.

The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 10. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, and an alignment layer for setting a pretilt angle of the liquid crystal is formed on an inner surface of the liquid crystal display panel 10 in contact with the liquid crystal.

The liquid crystal display panel 10 is driven in units of blocks including a plurality of display surfaces 10A to 10D divided along the vertical direction. Each of the first to fourth display surfaces 10A to 10D includes k horizontal lines (k is a positive integer). Here, the horizontal line refers to a line formed by arranging liquid crystal cells in a line along the horizontal direction.

As illustrated in FIG. 6, the timing controller 11 includes a data storage 111, a data alignment unit 112, and a control signal generator 113.

The data storage unit 111 stores a frame of digital video data RGB input from a system board on which an external video source is mounted, including a frame memory.

The data alignment unit 112 rearranges the digital video data RGB of one frame from the data storage unit 111 in the panel scan order. In the panel scan according to the present invention, as shown in FIG. 7, the Y 'direction of the first and second display surfaces 10A and 10B of the liquid crystal display panel 10 and the third and fourth display surfaces of the liquid crystal display panel 10 are shown. At (10C, 10D) it is made along the Y direction, but alternately once on each display surface as indicated by the serial number. That is, the scan is performed on the first display surface 10A in 2j-1 (j is 1,3,5,7, ...) th order, and on the second display surface 10B in the 2j th order 2j. The third display surface 10C is performed in the +1 th order, and the fourth display surface 10D is performed in the 2j + 2 th order. On the first display surface 10A, the scan proceeds sequentially from the kth horizontal line H1k to the first horizontal line H11 along the Y 'direction, and the scan on the second display surface 10B follows the Y' direction. It proceeds sequentially from the kth horizontal line H2k to the first horizontal line H21. On the third display surface 10C, the scan proceeds sequentially from the first horizontal line H31 to the kth horizontal line H3k along the Y direction, and the scan on the fourth display surface 10D is the first along the Y direction. It progresses sequentially from the horizontal line H41 to the kth horizontal line H4k. Accordingly, the data alignment unit 112 may include data RGB (H1k) to be charged in the k-th horizontal line H1k of the first display surface 10A-> k-th horizontal line H2k of the second display surface 10B. ) To be charged in the data (RGB (H2k))-> the first horizontal line H31 to be filled in data (RGB (H31))-> the first of the fourth display surface 10D Data to be charged in the horizontal line H41 (RGB (H41))-> Data to be charged in the k-1th horizontal line H1k-1 of the first display surface 10A-> Data to be charged to the k-1th horizontal line H2k-1 of the second display surface 10B (RGB (H2k-1))-> To the second horizontal line H32 of the third display surface 10C Data to be charged (RGB (H32))-> Data to be charged to the second horizontal line H42 of the fourth display surface 10D (RGB (H42))-> digital video data for one frame Reorder (RGB). The data aligning unit 112 supplies the rearranged digital video data RGB to the data driving circuit 12.

The control signal generator 113 adjusts the operation timing of the data driver 12 and the first to fourth gate drivers 13A to 13D based on the timing signals Vsync, Hsync, DE, and DCLK from the system board. Generate timing control signals DDC and GDC1 to GDC4 for controlling.

The data timing control signal DDC for controlling the operation timing of the data driving circuit 12 is a source start pulse (SSP) indicating the position of the liquid crystal cell Clc to which valid data is applied in one horizontal period. A source sampling clock (SSC) for instructing latching of data in the data driving circuit 12 based on a rising or falling edge, and an output of the data driving circuit 12. A source output enable signal SOE, and a polarity control signal POL indicating the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 10.

The first gate timing control signal GDC1 for controlling the operation timing of the first gate driver 13A indicates a starting horizontal line at which scanning of the first display surface 10A starts in one vertical period in which one screen is displayed. And a first gate start pulse GSP1 having a first direction value and a shift register in the first gate driver 13A to be input to the first gate start pulse GSP1 according to the first direction value. A first gate shift clock signal (GSC1) generated by a pulse width approximately four times the ON period of the TFT as a timing control signal for sequentially shifting the signal in the Y 'direction, and the first And a first gate output enable signal GOE1 indicating the output of the gate driver 13A.

The second gate timing control signal GDC2 for controlling the operation timing of the second gate driver 13B indicates a starting horizontal line at which scanning of the second display surface 10B starts in one vertical period, and the first direction value. And a second gate start pulse GSP2 generated later than the first gate start pulse GSP1 and input to a shift register in the second gate driver 13B, and according to the first direction value, the second gate start pulse GSP2. Is a timing control signal for sequentially shifting the signal in the Y 'direction and has a pulse width approximately four times the ON period of the TFT and is delayed by one horizontal period than the first gate shift clock signal GSC1. And a second gate shift clock signal GSC2 and a second gate output enable signal GOE2 indicating the output of the second gate driver 13B.

The third gate timing control signal GDC3 for controlling the operation timing of the third gate driver 13C indicates the start horizontal line at which the scanning of the third display surface 10C starts in one vertical period and the second direction value. And a third gate start pulse GSP3 generated later than the second gate start pulse GSP2 and input to a shift register in the third gate driver 13C, and according to the second direction value, the third gate start pulse GSP3. Is a timing control signal for sequentially shifting the signal in the Y direction and has a pulse width approximately four times corresponding to the ON period of the TFT and is delayed by one horizontal period than the second gate shift clock signal GSC2. And a gate shift clock signal GSC3 and a third gate output enable signal GOE3 indicating the output of the third gate driver 13C.

The fourth gate timing control signal GDC4 for controlling the operation timing of the fourth gate driver 13D indicates the start horizontal line at which the scanning of the fourth display surface 10D starts in one vertical period and the second direction value. And a fourth gate start pulse GSP4 generated later than the third gate start pulse GSP3 and input to a shift register in the fourth gate driver 13D, and according to the second direction value, the fourth gate start pulse GSP4. Is a timing control signal for sequentially shifting the signal in the Y direction and has a pulse width approximately four times corresponding to the ON period of the TFT and is delayed by one horizontal period than the third gate shift clock signal GSC3. And a gate shift clock signal GSC4 and a fourth gate output enable signal GOE4 indicating the output of the fourth gate driver 13D.

Meanwhile, the timing controller 11 inserts an interpolation frame between frames of an input video signal input at a frame frequency of 60 Hz, multiplies the data timing control signal DDC and the gate timing control signals GDC1 to GDC4 by 60. The operation of the data driving circuit 12 and the gate driving circuit 13 can be controlled at a frame frequency of × N (N is a positive integer of 2 or more) Hz.

The data driving circuit 12 stores a shift line for sampling a clock signal, a register for temporarily storing digital video data (RGB), and one line for storing data in response to a clock signal from the shift register. Latch for outputting data at the same time, digital / analog converter for selecting positive / negative gamma voltage under reference to gamma reference voltage corresponding to digital data value from latch, conversion by positive / negative gamma voltage A plurality of data drive integrated circuits each include a multiplexer for selecting a data line DL to which analog data is supplied, and an output buffer connected between the multiplexer and the data line DL. The data driving circuit 12 latches the digital video data RGB in response to the data timing control signal DDC from the timing controller 11, and the latched digital video data RGB is positive / negative polarity gamma. The compensation voltage is converted into the positive / negative analog data voltage and then supplied to the data lines DL.

The gate driving circuit 13 includes first to fourth gate drivers 13A to 13D. The first to fourth gate drivers 13A to 13D respectively include a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell, a gate drive integrated circuit including an output buffer, and the like. admit.

The first gate driver 13A sequentially outputs scan pulses (or gate pulses) in response to the first gate timing control signal GDC1 from the timing controller 11 to display the first display of the liquid crystal display panel 10. The gate lines GL are formed on the surface 10A. Specifically, the first gate driver 13A has a pulse width of 4 horizontal periods 4HP and a rising edge and polling of the first gate shift clock signal GSC1 generated at a period of 8 horizontal periods 8HP as shown in FIG. 8. In synchronization with the edge, scan pulses SP1k, SP1k-1, ..., SP11 are generated which are shifted by 4 horizontal periods (4HP) along the Y 'direction with a pulse width of one horizontal period (1H).

In response to the second gate timing control signal GDC2 from the timing controller 11, the second gate driver 13B sequentially outputs scan pulses to the second display surface 10B of the liquid crystal display panel 10. Supply to the formed gate lines (GL). Specifically, the second gate driver 13B is delayed in phase by one horizontal period (1HP) than the first gate shift clock signal GSC1 as shown in FIG. 8 and has a pulse width of four horizontal periods (4HP). Shifting by 4 horizontal periods (4HP) along the Y 'direction with a pulse width of 1 horizontal period (1HP) in synchronization with the rising edge and the falling edge of the second gate shift clock signal GSC2 generated at a period of (8HP) To generate scan pulses SP2k, SP2k-1, ..., SP21.

In response to the third gate timing control signal GDC3 from the timing controller 11, the third gate driver 13C sequentially outputs scan pulses to the third display surface 10C of the liquid crystal display panel 10. Supply to the formed gate lines (GL). Specifically, the third gate driver 13C is delayed in phase by one horizontal period (1HP) than the second gate shift clock signal GSC2 as shown in FIG. 8 and has a pulse width of four horizontal periods (4HP). In synchronism with the rising edge and the falling edge of the third gate shift clock signal GSC3 generated at a period of (8HP), the pulse width of one horizontal period (1HP) is shifted by four horizontal periods (4HP) along the Y direction. Generate scan pulses SP31, SP32, ..., SP3k.

In response to the fourth gate timing control signal GDC4 from the timing controller 11, the fourth gate driver 13D sequentially outputs scan pulses to the fourth display surface 10D of the liquid crystal display panel 10. Supply to the formed gate lines (GL). Specifically, the fourth gate driver 13D is delayed in phase by one horizontal period (1HP) than the third gate shift clock signal GSC3 as shown in FIG. 8 and has a pulse width of four horizontal periods (4HP). In synchronism with the rising edge and the falling edge of the fourth gate shift clock signal GSC4 generated at a period of (8HP), the pulse width of one horizontal period (1HP) is shifted by four horizontal periods (4HP) along the Y direction. The scan pulses SP41, SP42, ..., SP4k are generated.

The backlight unit 16 includes a plurality of light sources to irradiate light to the liquid crystal display panel 10. The backlight unit 16 may be implemented as one of a direct type and an edge type. The direct type backlight unit 16 has a structure in which a plurality of optical sheets and a diffusion plate are stacked below the liquid crystal display panel 10 and a plurality of light sources are disposed below the diffusion plate. The edge type backlight unit 16 has a structure in which a plurality of optical sheets and a light guide plate are stacked below the liquid crystal display panel 10 and a plurality of light sources are disposed on the side of the light guide plate. The light sources can be implemented with line light sources such as Cold Cathode Fluorescent Lamps (CCFLs) and External Electrode Fluorescent Lamps (EEFLs), and can also be implemented as light emitting diodes (LEDs). It can be implemented with point light sources.

The light source control circuit 14 generates the light source control signal SS by using a pulse width modulation (PWM) signal and a light source sync signal Lsync input from the outside. The PWM signal may be input at a duty ratio of 40% to 60% that is fixed by the user in advance, and may be input at a duty ratio that is variable according to an analysis result of the display data. That is, the PWM signal may be input at a first duty ratio corresponding to display data of a relatively bright image, and may be input at a second duty ratio smaller than the first duty ratio corresponding to display data of a relatively dark image. The light source sync signal Lsync is a timing signal for controlling the turn-on time of the light sources for flashing driving, and the turn-on time of the light sources is generally synchronized with the completion of charging of the data voltage for a specific portion of the liquid crystal display panel 10. It is preset by the user.

As illustrated in FIGS. 9 and 10, the light source turn-on time may include a first time point t1 and a first time point at which the data voltage Vdata is charged at the first point P1 of the first display surface 10A. After t1, the second time point t2 at which the data voltage Vdata is fully charged at the second point P2 of the second display surface 10B, and the third display surface 10C following the second time point t2. The third time point t3 at which the data voltage Vdata is fully charged at the third point P3 of, and the data voltage at the fourth point P4 of the fourth display surface 10D subsequent to the third time point t3. Vdata may be set to be synchronized with any one of the fourth time points t4 at which charging is completed. As shown in FIG. 10, the timing of applying the data voltage Vdata between neighboring points differs only by one horizontal period 1HP, and thus, between the first time point t1 and the second time point t2, The difference between t2) and the third time point t3, and between the third time point t3 and the fourth time point t4 also differs by only one horizontal period 1HP, respectively. That is, even if the light source turn-on time is set based on any one of the first to fourth time points t1 to t4, the maximum temporal difference from the remaining time points is only 3 horizontal periods (3HP). This means that the MPRT performance can be sufficiently improved by flashing driving the light sources and driving the liquid crystal display panel 10 in units of blocks (display surfaces) even if the light sources are not driven in block units as in the related art.

In order to reduce side effects (double line, blurring, etc.) at the boundary between blocks, the first point P1 is the k-th horizontal line H1k of the first display surface 10A, and the second point P2 is The kth horizontal line H2k of the second display surface 10B, the third point P3 is the first horizontal line H31 of the third display surface 10C, and the fourth point P4 is the fourth The first horizontal line H41 of the display surface 10D may be determined. Considering that an important part of the display image is normally displayed at the center of the screen, it is highly desirable to set the turn-on time point of the light sources on the basis of the boundary of each block as in the present invention.

On the other hand, the turn-off time of the light sources for flashing driving may vary depending on the duty ratio of the PWM signal.

The light source driving circuit 15 flashes the light sources simultaneously in response to the light source control signal SS. Since the light sources are driven at the same time instead of individually driven in units of blocks, the light source driving circuit 15 does not need to have a structural change regardless of the number of blocks of the liquid crystal display panel 10.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 shows an example of driving an impulse type.

2 shows an example of driving of a hold type;

3 is a view showing a light source connection configuration in driving a conventional general scanning backlight;

4 is a view illustrating a charging timing of a data voltage and a light source sink timing according to FIG. 3.

5 is a view showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 6 illustrates the timing controller of FIG. 5 in detail; FIG.

7 is a view for explaining the operation of the data alignment unit of FIG.

8 is a view for explaining the operation of the gate driving circuit of FIG.

9 shows an optimal light source sink point.

FIG. 10 is a view illustrating a completion point of charging a data voltage in response to a turn-on time of light sources at each point of FIG. 9; FIG.

<Description of Symbols for Main Parts of Drawings>

10 liquid crystal display panel 11 timing controller

12: data driving circuit 13: gate driving circuit

14 light source control circuit 15 light source driving circuit

16: backlight unit

Claims (9)

A liquid crystal display panel in which a plurality of gate lines and a plurality of gate lines intersect and are divided and driven to a plurality of display surfaces; Scan pulses are sequentially supplied to the gate lines of the first and second display surfaces of the liquid crystal display panel in a first direction, and the first and second gate lines of the gate lines of the third and fourth display surfaces of the liquid crystal display panel are provided. A gate driving circuit which sequentially supplies scan pulses along a second direction opposite to a direction, and alternately supplies the scan pulses to the display surfaces at regular intervals; A data driving circuit configured to supply a data voltage to the data lines in synchronization with the scan pulse; A backlight unit radiating light to the liquid crystal panel including a plurality of light sources; And And a light source control circuit for simultaneously controlling the driving of the light sources by using a light source sync signal for synchronizing the turn-on time of the light sources with a completion point of charging of the data voltage charged in a specific portion of the liquid crystal display panel. A liquid crystal display device. The method of claim 1, The gate driving circuit, A first gate driver configured to generate a first scan pulse shifted by four horizontal periods in the first direction with a pulse width of one horizontal period and to supply the gate lines to the first display surface; A second gate driver configured to generate a second scan pulse shifted by four horizontal periods in the first direction with a pulse width of one horizontal period and to supply the gate lines to the second display surface; A third gate driver configured to generate a third scan pulse shifted by four horizontal periods in the second direction with a pulse width of one horizontal period and to supply the gate lines to the third display surface; And And a fourth gate driver configured to generate a fourth scan pulse shifted by four horizontal periods in the second direction with a pulse width of one horizontal period and to supply the gate lines to the fourth display surface. LCD display device. The method of claim 2, Wherein the first scan pulse is generated following the fourth scan pulse, the second scan pulse is generated following the first scan pulse, the third scan pulse is generated following the second scan pulse, Four scan pulses are generated following the third scan pulse; And scanning pulses generated adjacent to each other have a phase difference by one horizontal period from each other. The method of claim 3, wherein A timing controller for controlling the operation of the driving circuits; The timing controller, A data storage unit for storing one frame of digital video data; A data alignment unit for rearranging the digital video data in order of supply of the scan pulse and supplying the digital video data to the data driving circuit; And And a control signal generator for generating first to fourth gate timing control signals for controlling operation timings of the first to fourth gate drivers, respectively. The method of claim 4, wherein The first gate timing control signal includes a first gate shift clock signal having a pulse width of four horizontal periods and being generated at a period of eight horizontal periods; The second gate timing control signal has a phase delayed by one horizontal period compared to the first gate shift clock signal, and includes a second gate shift clock signal having a pulse width of four horizontal periods and having a period of eight horizontal periods. ; The third gate timing control signal has a phase delayed by one horizontal period compared to the second gate shift clock signal, and includes a second gate shift clock signal generated at intervals of eight horizontal periods with a pulse width of four horizontal periods. ; The fourth gate timing control signal has a phase delayed by one horizontal period compared to the third gate shift clock signal, and includes a second gate shift clock signal generated at intervals of eight horizontal periods with a pulse width of four horizontal periods. Liquid crystal display device characterized in that. The method of claim 1, The turn on time of the light sources is, A first time point at which the data voltage is charged at a first point on the first display surface; A second time point at which the data voltage is fully charged at a second point on the second display surface after the first time point; A third time point at which the data voltage is fully charged at a third point on the third display surface after the second time point; And And a fourth time point at which the data voltage is completely charged at a fourth point on the fourth display surface subsequent to the third time point. The method of claim 6, And a phase difference of one horizontal period between the first time point and the second time point, between the second time point and the third time point, and between the third time point and the fourth time point. The method of claim 6, Each of the display surfaces includes k (k is a positive integer) horizontal lines; The first point is a k-th horizontal line of the first display surface, the second point is a k-th horizontal line of the second display surface, and the third point is a first horizontal line of the third display surface. And the fourth point is defined as the first horizontal line of the fourth display surface. The method of claim 1, The light source control circuit further uses a pulse width modulated signal input from the outside in controlling the driving of the light sources; And a turn-off time point of the light sources varies depending on a duty ratio of the pulse width modulated signal.

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