KR20120068425A - Liquid crystal display and low power driving method thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a low power driving method thereof are provided to successively operate a plurality of light sources, thereby maintaining lifetime of the light sources with an equivalent level. CONSTITUTION: A timing control and source drive integrated circuit(110) write standby mode image data on a left side part of a screen C region. A second light source is operated in a standby mode. Other light sources are turned off in the standby mode. The second light source projects light to the left side part of the screen C region. Only a third gate-in-panel circuit outputs data in the standby mode. A gate pulse is successively provided to gate lines arranged within the screen C region.

Description

Liquid crystal display and its low power driving method {LIQUID CRYSTAL DISPLAY AND LOW POWER DRIVING METHOD THEREOF}

The present invention relates to a liquid crystal display and a low power driving method thereof.

Various flat panel displays (FPDs) are being developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (FEDs), plasma display panels (hereinafter referred to as "PDPs") and electric fields. Light emitting devices; and the like.

The LCD used as the display element of the mobile information terminal should be driven at low power in the standby mode. The standby mode is also known as Dimmed Low Power (DLP) mode, which uses about seven light emitting diodes (LEDs) as a light source of a backlight unit (BLU) in the LCD of a mobile information terminal.

In general, the LCD of a mobile information terminal has a target luminance of about 500 nit in a normal drive, and in this case, a current of about 20 mA and a voltage of about 3.2 V are driven. In the normal driving mode, the power consumption of the backlight unit is about 448mW.

Standby power consumption in LCD of mobile information terminal is aimed at 20mW level. However, in the standby mode, it is difficult to reduce the power consumption of the driving circuit for driving the data lines and the gate lines of the LCD, and simply reducing the current of the LEDs (Light Emitting Diode) cannot significantly lower the power consumption of the backlight unit. . Therefore, the LCD of the current mobile information terminal is difficult to reduce the power consumption below the target value in the standby mode. Due to the power consumption problem of the standby mode, a mobile information terminal such as a smart phone is driven at the minimum power without displaying any data on the LCD screen in the standby mode.

The present invention provides a liquid crystal display device and a low power driving method thereof capable of lowering power consumption in a standby mode.

The liquid crystal display of the present invention includes liquid crystal cells including data lines to which a data voltage is supplied, gate lines to which gate pulses are synchronized with the data voltages, and liquid crystal cells arranged in a matrix form. Display panel; A backlight unit radiating light of the liquid crystal display panel; A timing control and source driving circuit configured to supply a data voltage of the standby mode image only to data lines existing in a screen block on which a standby mode image is displayed among the data lines of the liquid crystal display panel; A gate driving circuit configured to supply the gate pulse only to gate lines existing in a screen block in which the standby mode image is displayed among the screen blocks divided in the screen of the liquid crystal display panel in the standby mode; And a light source driving circuit for lighting only a light source that is in charge of an area in which the standby mode image is displayed among light sources of the backlight unit in the standby mode, and turning off other light sources.

The low power driving method of the liquid crystal display includes supplying a data voltage of the standby mode image only to data lines existing in a screen block on which a standby mode image is displayed among data lines of the liquid crystal display panel; Supplying the gate pulse only to gate lines existing in the screen block in which the standby mode image is displayed among the screen blocks divided in the screen of the liquid crystal display panel in the standby mode; And turning on only a light source that is in charge of an area in which the standby mode image is displayed among light sources of the backlight unit in the standby mode, and turning off other light sources.

The present invention selectively drives one or a plurality of light sources among a plurality of light sources, sequentially turns on a plurality of light sources, thereby maintaining the lifespan of the light sources at the same level and shifts the display position of the standby mode image. As a result, the present invention can display the standby mode image on the LCD screen and minimize the LCD driving circuit and the power consumption of the backlight. Furthermore, the present invention prevents screen staining due to the difference in lifespan of light sources that vary by use time by turning on only one of the light sources and periodically changing the light source in the standby mode, and increasing the recognition rate of the standby mode image by shifting the standby mode image. have.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
2A to 2C are diagrams illustrating a standby mode operation in a liquid crystal display according to an exemplary embodiment of the present invention.
3 is a circuit diagram showing in detail the GIP circuit shown in FIG.
FIG. 4 is a waveform diagram illustrating clock signals input to the GIP circuit of FIG. 3.
5 is a waveform diagram illustrating input and output signals of the first GIP circuit.
FIG. 6 is a diagram illustrating a parallel connection structure of a light source driving circuit and light sources shown in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Referring to FIG. 1, a stereoscopic image display device according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, a display panel driving circuit, a light source 310, a light source driving circuit 300, and the like.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 100 includes pixels arranged in a matrix by a cross structure of the data lines DL and the gate lines GL. The TFT array substrate of the liquid crystal display panel 100 is connected to data lines, gate lines intersecting the data lines, TFTs formed at intersections of the data lines and the gate lines, pixel electrodes of the liquid crystal cell, and pixel electrodes. Storage capacitors (Cst), and the like. The liquid crystal of the pixels is driven by an electric field between the pixel electrode and the common electrode connected to the TFT. The color filter array substrate of the liquid crystal display panel 100 includes a black matrix, a color filter, a common electrode, and the like. A polarizing film is attached to each of the upper glass substrate and the lower glass substrate, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal display of the present invention has a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, or a horizontal electric field driving method such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. Can be implemented.

The display panel driver circuit includes a timing control and source driver IC 110, a gate driver circuit, and the like.

The timing control and source driving IC 110 converts the digital video data input from the host system 200 into positive / negative data voltages and supplies them to the data lines DL. In the mobile information terminal, the host system 200 may be a main board of a phone system. The timing control and source driving IC 110 generates a gate timing control signal for controlling the operation timing of the gate driving circuit so that a gate pulse synchronized with the data voltage can be output from the gate driving circuit. The gate timing control signal includes a start pulse VST and clock signals CLK. In addition, the timing control and source driving IC 110 controls the light source driving circuit 300 by supplying light source control data for controlling the timing and brightness of the light source 310 to be turned on and off.

The gate driving circuit includes a GIP circuit 120 directly formed on a substrate of the liquid crystal display panel 100 by a gate in panel (GIP) process. The GIP circuit 120 includes a shift register for outputting a gate pulse (or scan pulse) synchronized with the data voltage in response to the start pulse VST and the clock signals CLK.

The light source driving circuit 300 controls the lighting of each of the light sources 310 under the timing control and the source driving IC 110 and adjusts the brightness thereof. Each of the light sources 310 may be implemented as an LED.

In the normal driving mode, the host system 200 transmits a normal driving mode switching command to the timing control and the source driving IC 110. The timing control and source driving IC 110 displays the positive / negative data voltages input from the host system 200 in the data lines DL in response to the normal driving mode switching command. The GIP circuit 120 sequentially supplies the gate pulses synchronized with the data voltage to all the gate lines GL in the normal driving mode. The light source driving circuit 300 turns on all the light sources 310 in the normal driving mode, and adjusts the brightness of the light sources 310 according to the dimming value input from the timing control and the source driving IC 110. do. The timing control and source driving IC 110 determines a dimming value according to the analysis result of the input image and adjusts the brightness of the light sources 310 by pulse width modulation (PWM) according to the dimming value.

In the standby mode, the host system 200 transmits a standby mode switch command to the timing control and source driving IC 110. The timing control and source driving IC 110 partially drives the GIP circuit 120 in the standby mode in response to the standby mode switching command, and also turns on and turns on any one of the light sources 310. Is changed according to a preset timing sequence to minimize power consumption. In addition, the timing control and source driving IC 110 may transmit data lines in the screen block in which the standby mode image is displayed in the standby mode, that is, data connected to pixels to which the data voltage of the standby mode image is to be written in response to the standby mode switching command. The data voltage is supplied only to the lines, and no voltage is applied to the other data lines.

In the standby mode, the host system 200 may supply data preset in the standby mode image (hereinafter, referred to as a “standby mode image”) to the timing control and source driving IC 110. The timing control and source driving IC 110 supplies the data voltage of the standby mode image input from the host system 200 only to the data lines DL existing in the backlight lighting region in the standby mode, thereby supplying the data voltage to the pixels in the lighting region. Enter. Therefore, the timing control and source driving IC 110 supplies the data voltage of the standby mode image only to some data lines. When the standby mode image is not input from the host system 200, the timing control and source driving IC 110 may supply the standby mode image data preset in the internal memory only to the data lines DL existing in the backlight lighting area. have.

In the standby mode, the GIP circuit 120 outputs the gate pulse only to the gate lines for selecting the pixels to which the standby mode image is written, and does not output the gate pulse to the other gate lines. To this end, the GIP circuit 120 may be divided into a plurality of screen blocks divided on the display screen so that the gate pulse may be supplied only to the gate lines GL existing in the region where the standby mode image is displayed. In the standby mode, the divided driving GIP circuit 120 may share the start pulse VST and supply clock signals CLK separately as shown in FIGS. 3 and 4.

2A to 2C are diagrams illustrating a standby mode operation in a liquid crystal display according to an exemplary embodiment of the present invention.

2A to 2C, the standby mode image data may be set to minimum data indicating a date, a time, and the like, but is not limited thereto. For example, the standby mode image data may be set as various data, such as a user's preset or selected data, for example, a user name, a motto, and a fortune of the day.

The timing control and source driving IC 110 supplies the data voltage of the standby mode image only to the data lines that are in charge of the area in which the standby mode image is displayed. The timing control and source driving IC 110 turns on only one light source 310 irradiating light to the area of the light sources 310 such that the area where the standby mode image is displayed is turned on. Since only one light source 310 is turned on in the standby mode, power consumption of the backlight unit is minimized. In order to increase the recognition rate of the standby mode image and prevent afterimages of the liquid crystal, the timing control and source driving IC 110 shifts the standby mode image on the screen at predetermined time intervals and shifts the standby mode image on the screen as shown in FIGS. 2A to 2C. The previously lit light source 310 is turned off so as to be synchronized with the other light source, and the other light source 310 for irradiating light to the shifted standby mode image screen is turned on.

The display screen of the liquid crystal display panel 100 is dividedly driven into a plurality of screens A through E as shown in FIGS. 2A to 2C in the standby mode. In the standby mode, the GIP circuit 120 sequentially supplies the gate pulses to the first GIP circuit that sequentially supplies the gate pulses to the gate lines GL present on the screen A, and the gate lines GL that exist on the screen B. To the second GIP circuit to supply the gate pulses to the gate lines GL present in the screen C and the gate pulses to the gate lines GL present in the screen D. A fourth GIP circuit and a fifth GIP circuit for sequentially supplying gate pulses to the gate lines GL present on the screen E may be included.

2A to 2C, it is assumed that the light sources 310 are arranged in the order of the first light source, the second light source, and the seventh light source from the left.

As shown in FIG. 2A, the timing control and source driving IC 110 transmits the data voltage to the pixels included in the left portion of the screen C region through the data lines DL in the left portion of the screen C region in the standby mode. Standby mode image data can be written. In the standby mode of FIG. 2A, only the second light source 310 that illuminates the left portion of the screen C is turned on and other light sources are turned off. In the standby mode of FIG. 2A, only the third GIP circuit generates an output under the control of the timing control and the source driving IC 110 so that the gate pulses are sequentially supplied to the gate lines existing in the screen C region.

As shown in FIG. 2B, the timing control and source driving IC 110 transmits the data voltage to the pixels included in the center portion of the screen C region through the data lines DL existing in the center portion of the screen C region in the standby mode. Standby mode image data can be written. In the standby mode of FIG. 2B, only the fourth light source 310 that illuminates the center portion of the screen C is turned on and other light sources are turned off. In the standby mode of FIG. 2B, only the third GIP circuit generates an output under the control of the timing control and the source driving IC 110 so that the gate pulses are sequentially supplied to the gate lines existing in the screen C region.

As shown in FIG. 2C, the timing control and source driving IC 110 transmits the data voltage to the pixels included in the center portion of the screen C area through the data lines DL in the right portion of the screen C area in the standby mode. Standby mode image data can be written. In the standby mode of FIG. 2C, only the sixth light source 310 that illuminates the right portion of the screen C is turned on and other light sources are turned off. In the standby mode of FIG. 2C, only the third GIP circuit generates an output under the control of the timing control and the source driving IC 110, and the gate pulses are sequentially supplied to the gate lines existing in the screen C region.

The number of lighting of the light sources 310 is not limited to one. For example, the light sources 310 may be turned on one by one as shown in FIGS. 2A to 2C or may be turned on simultaneously by two to six.

The standby mode image is not limited to the shift direction as shown in FIGS. 2A to 2C. The standby mode image may be shifted in left, right, and up and down directions of the screen. Therefore, the driving timings of the first to fifth GIP circuits divided by the GIP circuit 120 may be changed in synchronization with the shift timing of the standby mode image.

3 is a circuit diagram showing the GIP circuit 120 in detail. 4 is a waveform diagram illustrating clock signals A to E 'input to the GIP circuit 120.

) 노드의 전압에 응답하여 출력단자의 전압을 하강시키는 제1 및 제2 풀다운 트랜지스터(T2, T3), 및 Q 노드와 Q bar 노드의 전압을 제어하는 스위치 제어회로(도시하지 않음)를 포함한다. 3 and 4, the shift register of the GIP circuit 120 includes cascaded stages. Each of the stages includes a pull-up transistor T1 and Q bar (which raise the voltage at the output terminal in response to the voltage at the Q node).

First and second pull-down transistors T2 and T3 for lowering the voltage of the output terminal in response to the voltage of the node; and a switch control circuit (not shown) for controlling the voltages of the Q node and the Q bar node. .

In each of the first to fifth GIP circuits divided by the GIP circuit 120, the start pulse VST is input to the start pulse input terminal of the first stage. In each of the first to fifth GIP circuits, an output (or carry signal) of the previous stage, for example, the n-2 stage, is input to the start pulse input terminal of the nth stage (n is a positive integer of 2 or more). The output of the next stage is input to the reset terminals of the stages. For example, the output of the n + 2th stage is input to the reset terminal of the nth stage. In each of the first to fifth GIP circuits, one of the clock signals A-E 'is input to the clock signal input terminal of the stage.

In each of the stages, the gate electrode of the pull-up transistor T1 is connected to the Q node, and the source electrode is connected to the gate line through the output terminal of the stage. One of the clock signals A to E 'is supplied to the drain electrode of the pull-up transistor T1. In each of the stages, the gate electrodes of the first and second pull-down transistors T2 and T3 are connected to the Q bar node, and the drain electrode is connected to the gate line through the output terminal of the stage. The base voltage VSS or GND is supplied to the source electrodes of the first and second pull-down transistors T2 and T3.

The Q node is charged when the start pulse or the output of the previous stage is input to the start pulse input terminal of the stage to turn on the pull-up transistor T1. The pull-up transistor T1 of the stage connected to the gate line GL when the voltage of the Q node rises sufficiently above its own turn-on voltage and the clock signal A to E 'input to its drain terminal is a high logic voltage. Raise the output terminal voltage to the gate high voltage (VGH). The Q bar node is charged when the output of the next stage stage is input to the reset terminal of the stage to turn on pull-down transistors T2 and T3. The pull-down transistors T2 and T3 drop the output terminal voltage of the stage connected to the gate line GL to the gate low voltage VGL when the voltage of the Q bar node sufficiently rises above its Moonturn voltage. Therefore, each of the stages outputs a gate pulse swinging between the gate high voltage VGH and the gate low voltage VGL when the clock signals A to E 'are input to the gate line.

In order to divide and drive the screen in the standby mode, clock signals A-E 'input to the GIP circuit 120 are separated from each of the first to fifth GIP circuits. The first GIP circuit sequentially supplies gate pulses to the gate lines GL present on the screen A in response to the clock signal pairs A and A '. The second GIP circuit sequentially supplies gate pulses to the gate lines GL present on the screen B in response to the clock signal B pairs B and B '. The third GIP circuit sequentially supplies gate pulses to the gate lines GL existing on the screen C in response to the clock signal C pairs C and C '. The fourth GIP circuit sequentially supplies gate pulses to gate lines GL present in the screen D in response to the clock signal D pairs D and D '. The fifth GIP circuit sequentially supplies gate pulses to the gate lines GL existing on the screen E in response to the clock signal E pairs E and E '.

In the normal driving mode, the timing control and source driving IC 110 generate all clock signals A to E '. Therefore, the GIP circuit 120 sequentially supplies the gate pulses to the gate lines GL of the entire screen in the normal mode.

The timing control and source driving IC 110 generates only some of the clock signals in order to drive only a part of the GIP circuit which is in charge of the screen area where the standby mode image is displayed in the standby mode. In the case of FIGS. 2A to 2C, the timing control and source driving IC 110 outputs the clock signal C pairs C and C 'and the remaining clock signals A-A', B-B ', and D-D'. , E-E ') is not output. Therefore, in the case of FIGS. 2A to 2C, only the third GIP circuit that is responsible for the screen C in the GIP circuit 120 may output the gate pulse, and the first, second, fourth, and fifth GIP circuits may generate an output. none.

The timing control and source driving IC 110 generates a pair of clock signals A-A 'during the scanning period of the screen A to drive the first GIP circuit. The clock signal A 'is delayed by 180 degrees compared to the clock signal A, and is generated in the reverse phase of the clock signal A. The timing control and source driving IC 110 generates a pair of clock signals B-B 'during the scanning period of the screen B to drive the second GIP circuit. The clock signal B 'is delayed by 180 degrees compared to the clock signal B, and is generated in the reverse phase of the clock signal B. The timing control and source driving IC 110 generates the clock signal C pair C-C 'during the scanning period of the screen C to drive the third GIP circuit. The clock signal C 'is delayed by 180 degrees compared to the clock signal C, and is generated in the reverse phase of the clock signal C. The timing control and source driving IC 110 generates the clock signal D pair D-D 'during the scanning period of the screen D to drive the fourth GIP circuit. The clock signal D 'is delayed by 180 degrees relative to the clock signal D, and is generated as an antiphase of the clock signal D. The timing control and source driving IC 110 generates a pair of clock signals E-E 'during the scanning period of the screen E to drive the fifth GIP circuit. The clock signal E 'is delayed by 180 degrees compared to the clock signal E, and is generated as the reverse phase of the clock signal E. The timing control and source driving IC 110 includes a clock signal A pair (A-A '), a clock signal B pair (B-B'), a clock signal C pair (C-C '), and a clock signal D in a normal driving mode. The clock signals A-E 'are output in the order of the pair D-D' and the clock signal E-pair E-E '. Each of the clock signals A-E 'is supplied to the clock signal input terminal of the GIP circuit through a separate wiring. The timing control and source driving IC 110 includes a pair of clock signals A (A-A '), a pair of clock signals B (B-B'), a pair of clock signals C (C-C '), and a pair of clock signals D in a standby mode. (D-D '), only the clock signal pairs of some GIP circuits that are in charge of the screen block in which the standby mode image is displayed among the pair of clock signals E (E-E') are output.

Although the screen is divided into five blocks in the standby mode and thus the clock signals are divided into five pairs, the GIP circuit 120 is divided into five, but the present invention is not limited thereto. For example, in the standby mode, the screen may be divided into N blocks (N is a positive integer of 2 or more), and thus the clock signals may be divided into N pairs so that the GIP circuit 120 may be driven by being divided into N blocks.

FIG. 5 is a waveform diagram illustrating input and output signals of a first GIP circuit for driving gate lines of screen A. FIG.

Referring to FIG. 5, the first GIP circuit sequentially outputs the gate pulses G1 to G3 to the gate lines existing on the screen A by shifting the start pulse VST for each pair of clock signals A-A '. do.

6 is a diagram illustrating a parallel connection structure of the light source driving circuit 300 and the light sources 310 shown in FIG. 1.

Referring to FIG. 6, the host system supplies the image data to the timing control and source driving IC 110, and supplies the light source control signal C _BL synchronized with the image data to the light source driving circuit 300.

The light sources 310 are connected to the light source driving circuit 300 in parallel. The light source driving circuit 300 applies the light source driving voltage to the anode of the light sources under the control of the host system 200 in the normal driving mode, and connects the cathodes of all the light sources 310 to the ground voltage source GND to provide all the light sources ( 310) lights up. In contrast, the light source driving circuit 300 applies a light source driving voltage to the anodes of all the light sources 310 under the control of the host system 200 in the standby mode, and based on the cathode of some of the light sources of one or more of the light sources 310. Only some of the light sources are turned on by connecting to the voltage source GND. In the standby mode, as shown in FIGS. 2A to 2C, the light source 310 previously turned on at predetermined time intervals is turned off, and the other light source 310 is turned on in synchronization with the shift timing of the standby mode image.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

100: liquid crystal display panel 110: timing control and source driving IC
120: GIP circuit 200: over-drive circuit
310: light source

Claims (9)

A liquid crystal display panel including data lines supplied with a data voltage, gate lines intersecting the data lines, and gate lines supplied with a gate pulse synchronized with the data voltage, and liquid crystal cells arranged in a matrix form;
A backlight unit radiating light of the liquid crystal display panel;
A timing control and source driving circuit configured to supply a data voltage of the standby mode image only to data lines existing in a screen block on which a standby mode image is displayed among the data lines of the liquid crystal display panel;
A gate driving circuit configured to supply the gate pulse only to gate lines existing in a screen block in which the standby mode image is displayed among the screen blocks divided in the screen of the liquid crystal display panel in the standby mode; And
And a light source driving circuit that turns on only a light source that is in charge of an area in which the standby mode image is displayed among light sources of the backlight unit in the standby mode, and turns off other light sources.
The method of claim 1,
The gate driving circuit sequentially supplies the gate pulses to all the gate lines formed on the screen of the liquid crystal display panel in a normal driving mode.
And the light source driving circuit lights all of the light sources of the backlight unit in the normal driving mode.
The method of claim 1,
The liquid crystal display panel,
In the standby mode, the screen is divided into N (N is a positive integer of 2 or more) blocks,
The gate driving circuit,
N GIP circuits which share a start pulse and are dividedly driven by receiving clock signal pairs divided into N pairs,
The timing control and source driving circuit,
The clock signal pair is supplied to the gate driving circuit, and the start pulse and the clock signal pair are supplied to the gate driving circuit and connected to the gate lines of the screen block in which the standby mode image is displayed. Liquid crystal display, characterized in that for supplying.
The method of claim 1,
The timing control and source driving circuit
Changing the display position of the standby mode image at predetermined time intervals in the standby mode to change data lines to which the data voltage of the standby mode image is supplied;
And the other light source is turned on in synchronization with the timing of changing the display position of the standby mode image.
The method of claim 4, wherein
The gate driving circuit,
And when the display position of the standby mode image is changed, supply the gate pulse to gate lines existing in another screen block on which the standby mode image is displayed.
A liquid crystal display panel including data lines supplied with a data voltage, gate lines supplied with a gate pulse crossing the data lines and supplied with a gate pulse synchronized with the data voltage, and liquid crystal cells arranged in a matrix; In the low power driving method of a liquid crystal display device comprising a backlight unit for irradiating light of the panel,
Supplying a data voltage of the standby mode image only to data lines existing in the screen block in which the standby mode image is displayed among the data lines of the liquid crystal display panel;
Supplying the gate pulse only to gate lines existing in the screen block in which the standby mode image is displayed among the screen blocks divided in the screen of the liquid crystal display panel in the standby mode; And
And turning on only a light source that is in charge of an area in which the standby mode image is displayed among light sources of the backlight unit in the standby mode, and turning off other light sources.
The method according to claim 6,
Sequentially supplying the gate pulses to all the gate lines formed on the screen of the liquid crystal display panel in a normal driving mode; And
And turning on all of the light sources of the backlight unit in the normal driving mode.
The method according to claim 6,
Changing the display positions of the standby mode image at predetermined time intervals in the standby mode to change data lines to which the data voltage of the standby mode image is supplied;
And turning off the light source previously turned on in the standby mode and turning on another light source in synchronization with the timing of changing the display position of the standby mode image.
The method of claim 8,
And supplying the gate pulses to gate lines existing in another screen block in which the standby mode image is displayed when the display position of the standby mode image is changed. .

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