KR20070119951A - Liquid crystal display - Google Patents

Abstract

An LCD is provided to ensure a stable data charging time and form data lines having different line widths and lengths corresponding to respective display blocks by providing a liquid crystal cell array that is driven separately into a plurality of display blocks. A plurality of data lines(D1 to Dm) include a plurality of R data lines, a plurality of G data lines, and a plurality of B data lines. A liquid crystal cell array is formed in pixel regions defined by the data lines and a plurality of gate lines(G1 to Gn), and is driven separately into a plurality of display blocks that are virtually divided. A gate driving circuit(33) sequentially supplies a scan signal to the gate lines for each of the display blocks during a first scan period, then sequentially supplies the scan signal to the gate lines for each of the display blocks for a second scan period, and then sequentially supplies the scan signal to the gate lines for each of the display blocks during a third scan period. A data driving circuit(32) sequentially supplies a red data voltage to the R data lines during the first scan period, sequentially supplies a green data voltage to the G data lines during the second scan period, and sequentially supplies a blue data voltage to the B data lines for the third scan period. A backlight unit emits red light to the liquid crystal cell array during a first lighting period between the first scan period and the second scan period, then emits green light to the liquid crystal cell array during a second lighting period between the second period and the third scan period, and then emits blue light to the liquid crystal cell array during a third lighting period after the third scan period. The data lines have different line widths according to the display blocks(BL1 to BLk).

Description

Liquid Crystal Display

1 is a view showing an arrangement of light sources in a liquid crystal display device driven by a conventional field sequential driving method.

FIG. 2 is a waveform diagram illustrating a lighting time of light sources shown in FIG. 1 and a data charging time of liquid crystal cells.

3 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

4 and 5 illustrate a portion of FIG. 3 to show that wiring widths of data lines corresponding to each display block are changed in the liquid crystal display according to the exemplary embodiment of the present invention.

6 is a waveform diagram showing a lighting time of light sources and a data charging time of liquid crystal cells in a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

31: timing controller 32: data drive circuit

33: gate driving circuit 36: liquid crystal display panel

38R, 38G, 38B: light source 39: light source driving circuit

12: LED module BL1 to BLk: display block

The present invention includes a liquid crystal cell array divided into a plurality of display blocks that are virtually divided in a liquid crystal display device driven according to a field sequential driving method to ensure stable charging time of data and The present invention relates to a liquid crystal display device which eliminates a block dim phenomenon by changing wiring widths of data lines corresponding to a display block.

The liquid crystal display adjusts the light transmittance of liquid crystal cells according to a video signal to display an image.

Among the liquid crystal display devices, an active matrix type liquid crystal display device in which switching elements are formed for each liquid crystal cell is advantageous in implementing a moving picture because active control of the switching elements is possible. As a switching element used in an active matrix type liquid crystal display device, a thin film transistor (hereinafter referred to as TFT) is mainly used.

In general, a liquid crystal display of a normal driving type divides one pixel into R, G, and B subpixels for color implementation, and includes R, G, and B color filters corresponding to the R, G, and B subpixels.

In contrast, the liquid crystal display of the field sequential driving system has an R light emitting diode (LED) for generating red light on the side of the light guide plate 11 as shown in FIG. 1. And a plurality of LED modules 12 each including a G LED for generating green light and a B LED for generating blue light, and turns on the R LED while the R data is charged in the liquid crystal cell of the R subpixel to generate red light. After irradiating the liquid crystal panel, the G LED is turned on while the G data is charged in the liquid crystal cell of the G subpixel, and the green light is irradiated to the liquid crystal panel. Blue light is irradiated onto the liquid crystal panel to implement a color image. Therefore, the field sequential liquid crystal display device does not need a color filter, but since R, G, and B are sequentially expressed by dividing one frame period, there is a shortcoming between the data voltage chargers of the liquid crystal cells.

2 is a waveform diagram showing a data charging time of a liquid crystal cell and a lighting time of an LED in a field sequential driving liquid crystal display device.

Referring to FIG. 2, the LCD of the field sequential driving method waits for the response of the liquid crystals during the waiting time (WT) after charging the R data into the R liquid crystal cells on the front of the panel, and then turns on the R LED during the lighting time (DT). Turn on. Subsequently, after filling the G data into the G liquid crystal cells on the front of the panel and waiting for the response of the liquid crystal during the waiting time WT, the G LED is turned on during the lighting period DT. After charging the B data to the B liquid crystal cells in front of the panel and waiting for the response of the liquid crystal during the waiting time WT, the B LED is turned on during the lighting period DT.

As can be seen in Figure 2, the field sequential liquid crystal display device requires a waiting time (WT) and a lighting time (DT) for the response of the liquid crystal, so that the data voltage charging time of the liquid crystal cells is shortened, so that the line It is difficult to be applied to a large number of high resolution liquid crystal display devices or high frame rate liquid crystal display devices.

In such a conventional field sequential liquid crystal display device, a method of dividing and driving a liquid crystal cell array into a plurality of virtual display blocks has been proposed in order to secure a charging time of a sufficient data voltage. However, by driving according to this division driving method, in the conventional field sequential driving type liquid crystal display device, the RC delay increases due to an increase in line resistance and parasitic capacitance in the display block farther from the data driving circuit, and thus in the same gray scale. There is a problem in that a block dim phenomenon in which luminance gradually decreases appears.

Accordingly, an object of the present invention is to ensure a stable charging time of data by having a liquid crystal cell array divided into a plurality of display blocks virtually divided in a liquid crystal display device driven according to a field sequential driving method. In addition, the present invention provides a liquid crystal display device which eliminates block dim by changing wiring widths and lengths of data lines corresponding to each display block.

In order to achieve the above object, the liquid crystal display device according to the present invention comprises a plurality of data lines including a plurality of R data lines, a plurality of G data lines and a plurality of B data lines; A plurality of gate lines; A liquid crystal cell array formed in the pixel area defined by the data lines and the gate lines and divided into a plurality of display blocks that are virtually divided; After sequentially supplying a scan signal to the gate lines for each of the plurality of display blocks during a first scan period, and sequentially supplying the scan signal to the gate lines for each of the display blocks during a second scan period. A gate driving circuit sequentially supplying the scan signal to the gate lines for each of the display blocks during a third scan period; After the red data voltage is sequentially supplied to the R data lines during the first scan period, the green data voltage is sequentially supplied to the G data lines during the second scan period, and then the third scan is performed. A data driving circuit sequentially supplying blue data voltages to the B data lines during the period; And irradiating red light to the liquid crystal cell array during the first lighting period between the first scan period and the second scan period, and then emitting green light during the second lighting period between the second scan period and the third scan period. A backlight unit which irradiates the liquid crystal cell array and then irradiates the liquid crystal cell array with blue light during a third lighting period after the third scan period; The data lines may have different wiring widths according to each display block.

The display blocks may include: a first display block for displaying data from a first data line group including a plurality of the data lines; And a second display block for displaying data from a second data line group including a plurality of said data lines.

The line widths of the data lines included in each data line group satisfy a relationship between data lines of the first data line group <data lines of the second data line group.

The line width of the at least some of the data lines increases as the distance from the output terminal of the data driving circuit increases.

The length of a data line included in each data line group may satisfy a relationship between data lines of the first data line group <data lines of the second data line group.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 6.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a liquid crystal display according to an exemplary embodiment of the present invention is formed in a pixel area defined by a plurality of data lines D1 to Dm and a plurality of gate lines G1 to Gn, and is virtually divided. A liquid crystal display panel 36 which is separately driven by the plurality of display blocks BL1 to BLk, a backlight unit for irradiating light to the liquid crystal display panel 36, and a plurality of display blocks during the first to third scan periods. A gate driving circuit 33 which sequentially supplies scan signals to the gate lines G1 to Gn for each of the blocks BL1 to BLk, and R, G, and B data voltages for each of the first to third scan periods. The data driving circuit 32 which sequentially supplies the G and B data lines, the light source driving circuit 39 for driving the light source of the backlight, and the operation timings of the driving circuits 32, 33, 39 are controlled. Timing cone for supplying digital video data to data driving circuit 32 And a roller (31). Here, the first scan period is defined as a period in which R data is filled, the second scan period is defined as a period in which G data is filled, and the third scan period is defined as a period in which B data is charged.

In the liquid crystal display panel 36, liquid crystal is injected between two glass substrates, and the data lines D1 to Dm and the gate lines G1 to Gn are orthogonal to each other on the lower glass substrate. The TFTs formed at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn may receive data from the data lines D1 to Dm in response to scan pulses from the gate lines G1 to Gn. Is supplied to the liquid crystal cell Clc. For this purpose, the gate electrode of the TFT is connected to the gate line G, and the source electrode is connected to the data line D. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 36 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the front gate line G, or may be formed between the liquid crystal cell Clc and a separate common line. In particular, in the liquid crystal display panel 36 according to the present invention, the pixel area defined by the data lines D1 to Dm and the gate lines G1 to Gn is divided into a plurality of display blocks BL1 to BLk. do.

The backlight unit includes a plurality of R light sources 38R, G light sources 38G and B light sources 38B, and a plurality of light sources for irradiating the liquid crystal display panel 36 with the light from the light sources 38R, 38G, and 38B uniformly. Optical sheets and the like. In this backlight unit, the R light source 38R, the G light source 38G and the B light source 38B are implemented with a plurality of LED modules 12 as shown in FIG. Each of the plurality of LED modules 12 includes R LEDs, G LEDs, and B LEDs, and is disposed to correspond to each of the divided regions BL1 to BLk that are virtually divided on the screen of the liquid crystal display panel 36.

The gate driving circuit 33 sequentially supplies a scan signal to the gate lines G1 to Gn for each of the plurality of display blocks BL1 to BLk during the first scan period, and then displays the display blocks during the second scan period. The scan signals are sequentially supplied to the gate lines G1 to Gn for each BL1 to BLk, and the scan signals are sequentially applied to the gate lines G1 to Gn for each of the display blocks BL1 to BLk during the third scan period. To supply. The gate driving circuit 33 has a shift register which sequentially generates scan pulses in response to the gate control signal GDC from the timing controller 31, and a level suitable for driving the liquid crystal cell Clc with a swing width of the scan pulses. Level shifter, output buffer, etc. The gate driving circuit 33 turns on the TFTs connected to the gate line G by supplying scan pulses to the gate line G, thereby reducing the pixel voltage of the data, that is, the analog gamma compensation voltage. The liquid crystal cells Clc of one horizontal line to be supplied are selected. Data generated from the data driving circuit 32 is supplied to the liquid crystal cells Clc of the selected one horizontal line by being synchronized with the scan pulse.

The data driving circuit 32 sequentially supplies the red data voltages to the R data lines during the first scan period, and then sequentially supplies the green data voltages to the G data lines during the second scan period. The blue data voltage is sequentially supplied to the B data lines during the three scan periods. The data driving circuit 32 stores a shift register, a register for temporarily storing digital video data RGB from the timing controller 31, and a line for storing data one line at a time in response to a clock signal from the shift register. A latch for simultaneously outputting minute data, a digital / analog converter for converting digital data from the latch into an analog data voltage using gamma reference voltages, and a buffer for outputting an analog data voltage.

The timing controller 31 controls the gate control signal GDC and the data driving circuit 32 for controlling the gate driving circuit 33 by using the vertical / horizontal synchronization signals V and H and the pixel clock CLK. A data control signal DDC for generating a field and a field sequential control signal FSC for controlling the light source driving circuit 39 are generated.

The light source driving circuit 39 is disposed between the first scan period and the second scan period in the LED modules corresponding to the display blocks BL1 to BLk in response to the field sequential control signal FSC from the timing controller 31. The R LEDs are turned on during the first lighting period of. Subsequently, the light source driving circuit 39 turns on the G LEDs during the second lighting period between the second scan period and the third scan period, and then turns on the B LEDs during the third lighting period after the third scan period.

4 and 5 illustrate a portion of FIG. 3 to show that wiring widths of data lines corresponding to each display block are changed in the liquid crystal display according to the exemplary embodiment of the present invention. For convenience of explanation, the number of display blocks will be described as three.

4 and 5, in the liquid crystal display panel 36 according to the exemplary embodiment, three pixel areas defined by the data lines D1 to Dm and the gate lines G1 to Gn are displayed. Drive is divided into blocks BL1 to BL3. The number of gate lines formed on the first to third display blocks BL1 to BL3 corresponds to one third of the total number of gate lines, respectively, and k (k) of each of the first to third display blocks BL1 to BL3. Since k is a positive integer less than or equal to i, the gate lines (for example, G1, Gi + 1, and G2i + 1) are simultaneously scanned, so that the liquid crystal display according to the present invention, which adopts the divided driving method, is divided into driving methods. Compared to this, one horizontal period is increased by about three times. Accordingly, the charging time of the data is stably secured, so that application to a high resolution or high frame rate liquid crystal display device is easy.

In addition, in the liquid crystal display according to the exemplary embodiment of the present invention, the wiring widths of the data lines for supplying the data voltage to each of the liquid crystal cells Clc of the display blocks BL1 to BL3 are assigned to the display blocks BL1 to BL3. By doing so, the block dim phenomenon is eliminated. That is, the wiring width according to the embodiment of the present invention is the wiring width of the data lines D1 (BL3) for supplying data voltages to the liquid crystal cells Clc of the third display block BL3> the second display block. Wiring width of the data lines D1 (BL2) for supplying a data voltage to each of the liquid crystal cells Clc of BL2> Supply a data voltage to each of the liquid crystal cells Clc of the first display block BL1 The RC delay due to the line resistance R and the parasitic capacitance C is reduced by adjusting to satisfy the relationship of the wiring width of the data lines D1 BL1. Here, the wiring width is formed differently according to each of the display blocks BL1 to BL3, and data lines (eg, D1) supplying data voltages to the liquid crystal cells Clc of the same display block (for example, BL3). In the case of the wiring width of BL3), the wiring width may be formed as shown in FIG. 4, and may increase as the distance from the data driving circuit increases as shown in FIG. 5.

Meanwhile, in the liquid crystal display according to the exemplary embodiment of the present invention, lengths of data lines for supplying data voltages to the liquid crystal cells Clc of each of the display blocks BL1 to BL3 are determined according to the display blocks BL1 to BL3. By doing so, the block dim phenomenon is eliminated. That is, the length of the data lines according to the exemplary embodiment of the present invention is the length of the data lines D1 (BL3) for supplying data voltages to the liquid crystal cells Clc of the third display block BL3> the second display. The length of the data lines D1 (BL2) for supplying the data voltage to each of the liquid crystal cells Clc of the block BL2> The data voltage is supplied to each of the liquid crystal cells Clc of the first display block BL1. The RC delay due to the line resistance R and the parasitic capacitance C is reduced by adjusting to satisfy the relationship that is the length of the data lines D1 BL1.

6 is a waveform diagram illustrating a lighting time of light sources and a data charging time of liquid crystal cells in a liquid crystal display according to an exemplary embodiment of the present invention. For convenience of explanation, the number of display blocks will be described as three.

The liquid crystal display according to the present invention charges R data to the R liquid crystal cells on the front of the liquid crystal display panel during the first scan period SCAN 1. To this end, during the first scan period, the first to third display blocks BL1 to BL3 are simultaneously scanned at the same time, and then sequentially scanned for each display block. When the scan is completed for each of the first to third display blocks BL1 to BL3, the R LED is turned on during the lighting time DT after waiting for a response of the liquid crystal during the liquid crystal response time WT. Here, the sum of the first scan period SCAN 1, the liquid crystal response time WT, and the lighting time DT is a 1/3 frame period.

Subsequently, G data is charged in the G liquid crystal cells on the front of the liquid crystal display panel during the second scan period SCAN 2. To this end, during the second scan period, the first to third display blocks BL1 to BL3 are simultaneously scanned at the same time, and then sequentially scanned for each display block. When the scan is completed for each of the first to third display blocks BL1 to BL3, the G LED is turned on during the lighting time DT after waiting for a response of the liquid crystal during the liquid crystal response time WT. Here, the sum of the second scan period SCAN 2, the liquid crystal response time WT, and the lighting time DT is a 1/3 frame period.

 Subsequently, B data is charged in the B liquid crystal cells in front of the liquid crystal display panel during the third scan period SCAN 3. To this end, during the third scan period, the first to third display blocks BL1 to BL3 are simultaneously scanned at the same time, and then sequentially scanned for each display block. When the scan is completed for each of the first to third display blocks BL1 to BL3, the B LED is turned on during the lighting time DT after waiting for a response of the liquid crystal during the liquid crystal response time WT. Here, the sum of the third scan period SCAN 3, the liquid crystal response time WT, and the lighting time DT is a 1/3 frame period.

As described above, the liquid crystal display device according to the present invention includes a liquid crystal cell array which is divided and driven into a plurality of display blocks that are virtually divided in the liquid crystal display device driven according to the field sequential driving method to stabilize the charging time of data. In addition, the width and length of the data lines corresponding to each display block may be differently formed, thereby reducing the RC delay occurring between the display blocks.

Accordingly, the liquid crystal display according to the present invention can improve the display quality by removing the block dim generated between the display blocks.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (5)

A plurality of data lines including a plurality of R data lines, a plurality of G data lines, and a plurality of B data lines; A plurality of gate lines; A liquid crystal cell array formed in the pixel area defined by the data lines and the gate lines and divided into a plurality of display blocks that are virtually divided; After sequentially supplying a scan signal to the gate lines for each of the plurality of display blocks during a first scan period, and sequentially supplying the scan signal to the gate lines for each of the display blocks during a second scan period. A gate driving circuit sequentially supplying the scan signal to the gate lines for each of the display blocks during a third scan period; After the red data voltage is sequentially supplied to the R data lines during the first scan period, the green data voltage is sequentially supplied to the G data lines during the second scan period, and then the third scan is performed. A data driving circuit sequentially supplying blue data voltages to the B data lines during the period; And Radiating red light to the liquid crystal cell array during a first lighting period between the first scan period and the second scan period, and then emitting green light during the second lighting period between the second scan period and the third scan period. A backlight unit irradiating the cell array and then irradiating blue light to the liquid crystal cell array during a third lighting period after the third scan period; And the data lines have different wiring widths according to each display block. The method of claim 1, The display blocks, A first display block for displaying data from a first group of data lines including a plurality of said data lines; And And a second display block for displaying data from a second group of data lines including a plurality of said data lines. The method of claim 2, The line width of the data line included in each data line group is And a relationship between data lines of the first data line group and data lines of the second data line group. The method of claim 3, wherein And at least some of the data lines of the data lines increase in line width from an output terminal of the data driving circuit. The method of claim 2, The length of the data lines included in each data line group is And a relationship between data lines of the first data line group and data lines of the second data line group.

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