JP2714161B2 - Liquid crystal display device - Google Patents

Description

The present invention relates to a liquid crystal display device using a matrix type display panel, and more particularly to driving a data line of the display panel by an AC driving method. Related to a driving circuit.

(Prior Art) A display device using a matrix type display panel using a liquid crystal cell as a display element, in particular, an active matrix type liquid crystal display device is generally configured as shown in FIG.

In FIG. 11, a matrix type liquid crystal display panel 1 has a plurality of data lines 2 extending in a vertical scanning direction (Y direction).
A liquid crystal cell 5 is connected via a switch element 4 to an intersection of a plurality of address lines 3 extending in the horizontal scanning direction (X direction). The liquid crystal cell 5 is actually composed of a capacitor for holding a drive voltage, a display electrode corresponding to a pixel to which the drive voltage held by the capacitor is applied, a transparent common electrode facing the same, a display common electrode and a transparent common electrode. And a liquid crystal layer sandwiched between these layers.

Data line drive circuit (hereinafter referred to as X drive circuit) 6
Is a circuit for driving the data line 2 according to an image signal, and an address line driving circuit (hereinafter, referred to as a Y driving circuit) 7 is a circuit for driving the address line 3 according to a scanning signal. That is, the X-ray circuit 6 is shown in FIG.
A plurality of data lines 2 are simultaneously driven upon receiving one line (horizontal scanning line) of the image signal shown in (b), and the Y drive circuit 7 sets one address line 3 each time the data line 2 is driven once. Drive by shifting each book. Thus, the display panel 1 is driven line by line in a so-called line-sequential manner.

In a liquid crystal display device, when a driving voltage of a fixed polarity is applied to a liquid crystal cell, the liquid crystal cell burns. Therefore, as shown in FIG. 13, positive and negative driving voltages are alternately applied to the liquid crystal cell 5, so-called AC driving. Need to be done. In this case, since the X drive circuit 6 must alternately generate positive and negative drive voltages, the amplitude and output amplitude of the image signal to be handled are pp values compared to the case where a drive voltage having a constant polarity is generated. It will be doubled.

Therefore, high withstand voltage characteristics are required for the X drive circuit, and the power consumption of the X drive circuit increases. In addition, when the amplitude of the image signal handled by the X drive circuit increases, a high withstand voltage process must be selected, and this process has a low signal processing speed, which is disadvantageous when handling a high-quality image signal. Further, when the amplitude of the image signal to be handled is large, the influence of the variation in the characteristics of the drive circuit becomes large, and display unevenness on the screen occurs.

A signal line inversion method is known as one of the methods for performing AC driving of a liquid crystal cell. In general, when the number of liquid crystal cells is large, the X drive circuits 6 are separately arranged above and below the display panel 1 as shown in FIG.
A mounting format is adopted in which every other data line 2 (signal line) is driven by the upper X drive circuit and the lower X drive circuit.

The signal line inversion method is a method using such a mounting form. As shown in FIG. 15, the upper X drive circuit and the lower X drive circuit have polarities opposite to each other and each line or An image signal for inverting the polarity is applied for each field, so that the data lines 2 are inverted for each line or for each field, and a driving voltage of opposite polarity is applied between adjacent data lines. Is the way.

However, even with this signal line inversion method, the problem that the amplitude and output amplitude of the image signal handled by the X drive circuit increase cannot be avoided.

(Problems to be Solved by the Invention) As described above, in the conventional liquid crystal display device,
When the liquid crystal cell is AC-driven, the amplitude and the output amplitude of the image signal handled by the X drive circuit are increased, and the X drive circuit is required to have a high withstand voltage characteristic. There have been various problems such as an increase in display unevenness due to variations in the characteristics of the display.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device capable of AC driving a liquid crystal cell without the problems described above.

[Constitution of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a data line driving circuit for driving a data line of a liquid crystal display panel based on an image signal for one horizontal scanning line. A first drive circuit for generating a positive drive voltage and a second drive circuit for generating a negative drive voltage, which are commonly connected to each data line, and the first and second drive circuits correspond to each other. The data lines are alternately driven at a predetermined period, for example, every line, every field or every frame.

Then, the first drive circuit inputs an image signal of the first polarity to an output portion thereof to generate a positive drive voltage from a positive power supply voltage, and the second drive circuit outputs a second polarity image signal to the output portion. To generate a negative drive voltage from a negative power supply voltage. Further, the first and second drive circuits may be provided with first and second sample-and-hold circuits, respectively, and an image signal may be input to an output unit via these sample-and-hold circuits.

Further, each of the first and second drive circuits may be configured to alternately drive two adjacent data lines.

(Operation) In the present invention, when attention is paid to each data line, the data lines are alternately driven by a positive drive voltage generated from the first drive circuit and a negative drive voltage generated from the second drive circuit,
A so-called AC drive is performed. Since both the first and second drive circuits need only generate a drive voltage of a single polarity,
The output amplitude and the amplitude of the image signal to be handled are halved as compared with the case where one driving circuit generates a driving voltage that is inverted to positive or negative.

Further, the first drive circuit is configured to input an image signal of a first polarity to an output section and generate a positive drive voltage from a positive power supply voltage, and the second drive circuit outputs a second drive signal to the output section. Is configured to generate a negative drive voltage from a negative power supply voltage by inputting an image signal of the same polarity, for example, by inputting an image signal of the same polarity to the first and second drive circuits, 1
The withstand voltage of the output section can be lower than in a configuration in which a non-inverting buffer is used for the output section of the driving circuit and an inverting buffer is used for the output section of the second driving circuit.

Therefore, when an integrated circuit is formed, the output section can be realized by a miniaturization process, good characteristics can be obtained, and operating current can be reduced to reduce power consumption. Further, the first and second drive circuits can have the same configuration, which is advantageous for integration into an integrated circuit.

(Example) Hereinafter, an example of the present invention is described with reference to drawings.

First Embodiment FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display device according to a first embodiment of the present invention, in which (a) is a state at the time of the n-th frame, and (b) is a (n + 1) -th frame. The state at the time is shown.

This liquid crystal display device mainly comprises a matrix type liquid crystal display panel 1, an X drive circuit and a Y drive drive circuit 7, as in FIG. X drive circuit is display panel 1
1st and 2nd drive circuit 1 respectively arranged above and below
It is composed of 1,12. In this embodiment, the first and second driving circuits 11 and 12 are each composed of two integrated circuits due to the limitation of the number of terminals and the number of elements in the case of integration. It may be divided into circuits.

As shown in FIG. 2, the first and second driving circuits 11 and 12 sample and hold an analog input image signal, and a sample / hold circuit (S / H) 13 and respective outputs of the sample / hold circuit 13. An output buffer 14 and a timing generation circuit 15 for generating a sample pulse to the sample-and-hold circuit 13 are connected to the terminals. Output buffer 1 in first and second drive circuits 11 and 12
4 are provided in the same number as the number of data lines 2, respectively.
The output buffers 14 in the first and second drive circuits 11 and 12 are commonly connected to each data line 2. Output buffer
Reference numeral 14 has an output on / off function, and output enable signals OE1 and OE2 are separately provided for odd and even numbers. Note that the output buffer 14 is constituted by, for example, a voltage follower using an operational amplifier.

As shown in FIG. 1, a positive image signal is input to the first drive circuit 11, and a positive power supply voltage + Vcc and a ground level GND are given to the first drive circuit 11. The second drive circuit 12 receives a negative image signal and receives a negative power supply voltage −Vc
c and ground level GND are given. That is,
The first drive circuit 11 generates a positive drive voltage, and the second drive circuit 12 generates a negative drive voltage.

Next, the operation of this embodiment will be described. FIGS. 3 and 4 are timing diagrams at the time of the n-th frame and the (n + 1) -th frame. 3A and 4A, (a) is a positive input image signal input to the first drive circuit 11, (b) is a sample pulse to the sample and hold circuit in the drive circuit 11, and (c) is The negative input image signal input to the second drive circuit 12, and (d) shows a sample pulse to the sample and hold circuit in the drive circuit 12. Also,
The number written below the waveform of the sample pulse represents the number of the data line 2 to be driven.

In the n-th frame, as shown in FIG. 3, the first drive circuit 11 which receives a positive image signal drives the first, third, fifth,... Odd-numbered data lines, and outputs a negative image signal. The input second drive circuit 12 drives the second, fourth, sixth,..., Even-numbered data lines. In the next (n + 1) th frame, as shown in FIG. 4, the first drive circuit 11 drives even-numbered data lines, and the second drive circuit 12 drives odd-numbered data lines. Of the data lines 2 shown in FIG. 1, the lines written in bold lines indicate lines to which a positive drive voltage is applied, and the lines written in thin lines indicate lines to which a negative drive voltage is applied. It represents.

At this time, of the output buffers 14 in the first and second driving circuits 11 and 12 connected to the same data line, the output buffer in the driving circuit that drives the data line is the output enable signal. Turns on by OE1 or OE2, but the output buffer in the drive circuit that is not driving the data line is controlled to the off state and the output is open, so that it does not interfere with the output buffer in the on state It has become. That is, among the output buffers 14 in FIG. 1, those hatched are in the on state, and those not hatched are in the off state.

According to this configuration, when focusing on the individual data lines 2, a driving voltage of a reverse polarity is applied at the time of the n-th frame and at the time of the (n + 1) -th frame, and the AC driving is performed.

As described above, the first drive circuit 11 receives the positive image signal and generates only the positive drive voltage, and the second drive circuit 12
Since it is only necessary to generate a negative drive voltage with a negative image signal as an input, the output amplitude and the output amplitude and the drive circuit are compared with a drive circuit that generates both positive and negative drive voltages used in the conventional AC drive system. The amplitude of the image signal to be handled is halved.

Therefore, the power supply voltages + Vcc and -Vcc of the X drive circuit can be reduced, and the power consumption is reduced and the withstand voltage can be reduced to half. Further, as the signal voltage handled by the drive circuit is reduced, the processing speed is increased, and the absolute value of the variation in the characteristics of the drive circuit is reduced, so that the display unevenness on the screen is reduced.

Further, according to the above embodiment, as shown in FIG. 2, the output buffer 14 connected to the two adjacent data lines 2 is used.
Are connected to a common sample and hold circuit 13, and two adjacent data lines are alternately driven by the output of the same sample and hold circuit. Therefore, the number of output buffers 14 is twice the number of data lines 2. However, the number of the sample-and-hold circuits 13 and the control circuits and the like having a larger number of constituent elements can be reduced, and an increase in the circuit scale of the entire drive circuit can be suppressed.

Second Embodiment FIG. 5 shows a second embodiment of the present invention, in which the input image signal is a digital signal. As in FIG.
FIGS. 5 (a) and 5 (b) show an n-th frame and an n-th frame, respectively.
The state at the time of the +1 frame is shown. In the figure, first and second drive circuits 11 and 12 are respectively provided with a signal distribution circuit 21.
And a D / A converter (DAC) 22 and an output buffer 23. Output buffer 23 is connected to data line 2
The output buffers 23 in the first and second driving circuits 11 and 12 are commonly connected to each data line 2. The output buffer 14 has an output on / off function, and the output enable signal is separately provided for odd and even numbers.
OE1 and OE2 are given.

In FIG. 5, similarly to FIG. 1, of the data lines 2, a line written in a thick line is a line to which a positive drive voltage is applied, and a line written in a thin line is a negative drive line. Lines to which a voltage is applied are shown, and among the output buffers 23, those hatched are in an on state, and those not hatched are in an off state.

As shown in FIG. 6, the signal distribution circuit 21 includes a shift register 31 for taking in, for example, an 8-bit digital image signal input to the serial device for one line, and a shift register 31.
And a timing generation circuit 33 which holds the output of the latch circuit 32. The timing generation circuit 33 generates a shift clock supplied to the shift register 31 and a latch pulse supplied to the latch circuit group 32.

7 and 8 are timing charts at the time of the n-th frame and the (n + 1) -th frame. In both FIGS. 7 and 8, (a) is a positive digital input image input to the first drive circuit 11. Signals, (b) and (c) are shift lock to the shift register 31 in the drive circuit 11 and latch data of the latch circuit 32, (d) is a negative digital input image signal input to the second drive circuit 12, e) and (f) show the shift clock to the shift register 31 in the drive circuit 12 and the latch data of the latch circuit 32. (B) The shift clock of (e) has a cycle twice the data rate of the digital input image signal, and the shift clock of (b) and (e)
Is shifted by a half cycle from the shift clock of the shift clock.

In the n-th frame, as shown in FIG. 7, in the first drive circuit 11, positive digital input image signals D ₁ , D ₂ , D ₃ , D
_4, ... of the odd-numbered data D _1, D _3, ... are latch circuits 32
, And in the second drive circuit 12, of the negative digital input image signals ₁ , ₂ , ₃ , ₄ ,..., The even-numbered data ₂ , ₄ ,. The latched data is converted into an analog signal by the D / A converter 22, and the output of the D / A converter 22 is input to two output buffers 23 each.

Then, the first drive circuit 11 outputs the output enable signal OE1
As a result, the odd-numbered output buffer is turned on, thereby driving the odd-numbered data line with the positive drive voltage. The second drive circuit 12 drives the even-numbered data lines with a negative drive voltage when the even-numbered output buffers are turned on by the output enable signal OE2. At this time, the first not used for driving the data line
The even-numbered output buffers in the drive circuit 11 and the odd-numbered output buffers in the second drive circuit 12 are turned off and the outputs are opened, so that the output buffers are turned on, and the output buffers are turned on. Does not interfere with certain output buffers.

In the next n + 1 frame, as shown in FIG. 8, in the first drive circuit 11, positive digital input image signals D ₁ , D
_2, D _3, D _4, ... of the even-numbered data D _2, D _4, ... is latched in the latch circuit 32, a negative digital input image signal in the second drive circuit 12 _{1, 2, 3} , ₄ ,..., The odd-numbered data ₁ , ₃ ,. Each of the latched data is supplied to the D / A
The data is input to each output buffer 23.

The first drive circuit 11 turns on the even-numbered output buffers by the output enable signal OE2,
The even-numbered data lines are driven with a positive driving voltage. The second drive circuit 12 drives the odd-numbered data lines with a negative drive voltage when the odd-numbered output buffers are turned on by the output enable signal OE1. At this time, a first drive circuit not used for driving the data line
The odd-numbered output buffers in 11 and the even-numbered output buffers in the second drive circuit 12 are turned off, and the on-state outputs connected to the same data line do not interfere with the buffers.

Third Embodiment FIG. 9 shows a third embodiment of the present invention.
The drive circuit 11 includes a drive voltage generation circuit 41, an output buffer 42 connected to the output terminal of the drive voltage generation circuit 41, and two switches 43 connected to the output terminals of the output buffer 42, respectively. . The drive voltage generation circuit 41 is a circuit corresponding to the sample and hold circuit 13 in the first embodiment or the D / A converter 22 in the second embodiment.

In the first and second embodiments, the same number of output buffers 14 and 23 as the number of data lines are provided in the first and second drive circuits 11 and 12, respectively. And the number of output buffers 42 in the second drive circuits 11 and 12 is the same as the number of data lines 2, and instead, each switch is connected between the output buffer 42 and two adjacent data lines. 43 is connected. The ON / OFF control of the switch 43 is the same as the ON / OFF control of the output buffers 14 and 23 in the first and second embodiments.
Thereby, a data line to which a drive voltage is to be applied is selected.

According to this embodiment, a switch is newly required as compared with the first and second embodiments, but the number of output buffers is reduced to half, so that the circuit scale is further reduced.

Fourth Embodiment FIG. 10 shows a fourth embodiment of the present invention, in which a switch 44 corresponding to the switch 43 of FIG. 9 in the third embodiment is provided in the display panel 1. This switch 44
Since the number of switches may be smaller than the number of switches 4 for selecting the liquid crystal cell 5 shown in FIG. 11, a switch having good transfer characteristics can be used by design even for a thin film transistor or the like using amorphous silicon.

According to the present embodiment, the circuit scale of the drive circuits 11 and 12 can be further reduced, and the number of output pins of the drive circuits 11 and 12 and the display panel 1 is halved. The number of wirings between them is reduced by half, so that when the drive circuit is mounted on the display panel 1, the mounting is facilitated, and the advantage that the manufacturing cost is reduced is obtained.

Note that, in the present invention, before driving the data line 2 with a positive or negative driving voltage (in other words, charging the data line), the driving line which is accumulated on the data line to be driven and is to be applied from now on It is desirable to have a means for discharging the signal charge 4 having a polarity opposite to the voltage (charged by the drive voltage applied during the previous drive). Specific examples thereof will be described with reference to the following fifth to seventh embodiments.

Fifth Embodiment In this embodiment, a discharge function is provided in the first and second drive circuits 11 and 12 as a discharge means.
Before the data line 2 is charged, the discharge is performed by the driving circuit itself that is charging the data line 2.

Specifically, for example, when the output buffer is a voltage follower, when the drive circuit for charging the data line 2 is turned on, the data line 2 is connected to the data line 2 via the output buffer (14, 23, 42). When a drive voltage having a polarity opposite to that of the signal charge is applied, discharge is first performed through the current source transistor of the output buffer. After that, the data line 2 becomes zero potential and discharge is completed, and then charging is started.

In this case, since the drive circuit itself that applies the drive voltage to the data line 2 absorbs the signal charges accumulated on the data line 2 and performs the discharge, the timing control for the discharge is not particularly necessary. Output buffer is data line 2 before discharge
It is sufficient that the device has a withstand voltage equal to or greater than the potential difference between the potential of the driving circuit and the power supply voltage (+ Vcc or -Vcc) of the driving circuit.

Note that a discharge means such as a switch may be provided after the output buffer to discharge the data line 2.

Sixth Embodiment In this embodiment, the first and second discharge means are used.
Although the drive circuits 11 and 12 have a discharge function in the same manner as the fifth embodiment,
Before applying the drive voltage from 11 (or 12), the discharge is performed by the drive circuit 12 (or 11) to which the drive voltage has been applied before.

Specifically, for example, before the drive circuit 11 applies the drive voltage, by controlling the timing circuit, the output potential of the output buffer (14, 23, 42) in the drive circuit 12 is forcibly set to the temporary zero potential. Good. This is achieved, for example, by applying a zero level to the input of the voltage follower to make the output potential zero, in the case of an output buffer voltage follower. In the case of this embodiment, since the polarity of the signal charges accumulated on the data line 2 and the polarity of the power supply voltage of the driving circuit for discharging are the same, the withstand voltage of the driving circuit may be smaller than that of the fifth embodiment. .

Note that the discharge on the data line 2 may be performed using a discharging means such as a switch.

Seventh Embodiment In this embodiment, a discharge device is provided outside the first and second drive circuits 11 and 12 as a discharge means, and the discharge line is once set to a zero level by the discharge device to perform a discharge. Also in this case, the withstand voltage of the drive circuit may be equivalent to that of the sixth embodiment.

According to the present invention, a first drive circuit for generating a positive drive voltage and a second drive circuit for generating a negative drive voltage are provided as data line drive circuits. By performing AC driving by alternately driving each data line, compared with the conventional AC driving method in which one driving circuit generates a driving voltage that alternately reverses positive and negative,
The output amplitude of the drive circuit and the amplitude of the image signal to be handled are halved.

Therefore, the withstand voltage characteristic of the drive circuit is reduced, the power consumption is reduced, and the signal processing speed can be increased. This is advantageous when handling a high-speed image signal such as a high-definition image signal in the future. The effect of reducing the absolute value of the variation in the characteristics of the circuit and reducing display unevenness can be obtained.

The output of the first drive circuit is configured to receive the image signal of the first polarity and generate a positive drive voltage from the positive power supply voltage, and the output of the second drive circuit is configured to output the second drive circuit. Is configured to generate a negative drive voltage from a negative power supply voltage by inputting an image signal having a negative polarity, so that the withstand voltage of the output unit can be further reduced from this point. In this case, good characteristics can be realized by making it possible to adopt a miniaturization process for the output section, and furthermore, the operating current can be suppressed to reduce power consumption, and
Further, since the second drive circuit and the second drive circuit may have the same configuration, it is more advantageous to form an integrated circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
FIG. 3 is a block diagram showing the internal configuration of the first and second drive circuits in FIG. 1, FIG. 3 and FIG. 4 are timing diagrams for explaining the operation of the first embodiment, and FIG. FIG. 6 is a block diagram showing the second embodiment of the invention, FIG. 6 is a block diagram showing the internal configuration of the first and second drive circuits in FIG. 5, and FIGS. FIG. 9 is a timing chart for explaining the operation, FIG. 9 is a block diagram showing a third embodiment of the present invention, FIG. 10 is a block diagram showing a fourth embodiment of the present invention, and FIG. Is a diagram showing a schematic configuration of a display device using a liquid crystal display panel, FIG.
FIG. 12 is a waveform diagram of an image signal for explaining the operation, and FIG.
FIG. 13 is a diagram for explaining the AC driving method of the liquid crystal cell, and FIG.
FIG. 14 is a block diagram showing a configuration example of a drive circuit when the number of liquid crystal cells is large, and FIG. 15 is a block diagram showing a configuration of a drive circuit by a conventional signal line inversion method. DESCRIPTION OF SYMBOLS 1 ... Matrix liquid crystal display panel 2 ... Data line 3 ... Address line 6 ... X drive circuit (data line drive circuit) 7 ... Y drive circuit (address line drive circuit) 11,12 ... Second drive circuit 13 Sample hold circuit 14, 23, 42 Output buffer 21 Signal distribution circuit 22 D / A converter 31 Shift register 32 Latch circuit 41 Drive voltage generation Circuit 43,44 …… Switch

Claims (3)

(57) [Claims] 1. A liquid crystal display panel having liquid crystal cells connected to intersections of a plurality of data lines in a vertical scanning direction and a plurality of address lines in a horizontal scanning direction, wherein the plurality of data lines correspond to one horizontal scanning line. In a liquid crystal display device having a data line driving circuit that drives based on an image signal and an address line driving circuit that sequentially drives the plurality of address lines, the data line driving circuit is commonly connected to each data line. A first drive circuit for generating a positive drive voltage from a positive power supply voltage by inputting an image signal of a first polarity to an output unit and a negative power supply by inputting an image signal of a second polarity to an output unit A second driving circuit for generating a negative driving voltage from the voltage, wherein the first and second driving circuits alternately drive the corresponding data lines at a predetermined cycle. A liquid crystal display device according to claim and. 2. A liquid crystal display panel having liquid crystal cells connected to intersections of a plurality of data lines in a vertical scanning direction and a plurality of address lines in a horizontal scanning direction, wherein the plurality of data lines correspond to one horizontal scanning line. In a liquid crystal display device having a data line driving circuit that drives based on an image signal and an address line driving circuit that sequentially drives the plurality of address lines, the data line driving circuit is commonly connected to each data line. , An image signal of a first polarity is input to an output unit via a first sample and hold circuit, and a first drive circuit and a second sample and hold circuit generate a positive drive voltage from a positive power supply voltage. A second driving circuit for inputting an image signal of a second polarity to the output unit and generating a negative driving voltage from a negative power supply voltage. And a liquid crystal display device the second drive circuit, characterized in that the drive alternately corresponding data line at a predetermined cycle. 3. A display panel in which liquid crystal cells are respectively connected to intersections of a plurality of data lines in a vertical scanning direction and a plurality of address lines in a horizontal scanning direction; In a display device having a data line driving circuit that drives based on signals, and an address line driving circuit that sequentially drives the plurality of address lines, the data line driving circuit is connected to each of the data lines by a positive connection. A first drive circuit for generating a drive voltage and a second drive circuit for generating a negative drive voltage, wherein the first and second drive circuits alternately drive corresponding data lines at a predetermined cycle, A liquid crystal display device wherein each of the first and second driving circuits alternately drives two adjacent data lines.