JPH11282434A - Planar display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save power consumption, to attain a low cost and to-provide a thin structure with a narrow frame by permitting a driving circuit part to set the polarity inversion of a voltage to be impressed on an optical modulation layer by means of inversion period unit being a period which is n times as big as one horizontal display period. SOLUTION: An active matrix-type normal white liquid crystal display device 1 being one execution example of a planar display device is constituted of a liquid crystal display panel 16, a data signal line driving part 12, a gate line driving part 16, a control circuit part 20 and an opposite electrode driving circuit part 22. Then, the circuit 22 sets the polarity inversion of the voltage to be impressed on the optical modulation layer by inversion period unit being the period which is n (n is an integer being more than two) times as big as one horizontal display period. The polarity inversion of the voltage to be impressed on the layer is executed by inversion period unit being n times as big as one horizontal display period so that a polarity inversion cycle becomes longer, power consumption is reduced, unnecessary radiation countermeasure parts are reduced, the low cost is attained and the thin structure with the narrow frame is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display, and more particularly, to a drive which achieves low power consumption.

[0002]

2. Description of the Related Art In a liquid crystal panel used in a liquid crystal display device, a switching element (TFT, thin film transistor) is provided in each pixel to apply a desired voltage to each pixel. However, in an actually manufactured liquid crystal panel, since a capacitance component exists between signal wirings and between electrodes, a voltage is applied to peripheral pixels via the capacitance component. This becomes an interference component, that is, noise.

Therefore, in order to prevent this noise, a scanning line inversion driving method and a pixel inversion driving method have been conventionally proposed (Japanese Patent Publication No. Hei 5-29916).

The scanning line inversion driving method is a method of changing the polarity of a voltage applied to each scanning line of a liquid crystal panel, and the pixel inversion driving method is a method of changing the polarity of a voltage for each pixel.

[0005] A conventional polarity inversion schematic diagram shown in FIG. 11 is for the scanning line inversion driving method described above.
The n-th line in the frame has a positive polarity, and the (n + 1) -th line has a negative polarity.

[0006]

In the above-described scanning line inversion driving method and pixel inversion driving method, there is a problem that power consumption increases because the polarity inversion period is performed for each scanning line. Also, since this power consumption is required, D
There is also a problem that the number of components of the C / DC converter increases and cost cannot be reduced.

In view of the above problems, the present invention provides a flat panel display device which can be configured to have low power consumption, low cost, and a thin frame.

[0008]

According to the present invention, there is provided a flat display device comprising: a first electrode substrate having a plurality of pixel electrodes connected in a matrix to data signal lines and gate lines via switching elements; A flat panel display device comprising: a second electrode substrate having a counter electrode facing the second electrode substrate; and a display panel having a light modulation layer disposed between the first electrode substrate and the second electrode substrate. The polarity inversion of the voltage applied to the light modulation layer is performed in units of an inversion period, which is n times (n is an integer of 2 or more) one horizontal display period.

In this flat display device, the polarity of the voltage applied to the light modulation layer is inverted in units of an inversion period, which is n times as long as one horizontal display period. Power consumption can be reduced as compared with the inversion driving method.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a liquid crystal display device according to an embodiment of the flat display device of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of the active matrix type normally white liquid crystal display device 1. As shown in FIG. The liquid crystal display device 1 includes a liquid crystal display panel 16, a data signal line driving unit 12, a gate line driving unit 14, a control circuit unit 20, and a counter electrode driving circuit unit 22.

First, the liquid crystal display panel 16 will be described.

Although not shown, the liquid crystal display panel 16 includes a twisted nematic liquid crystal layer held between an array substrate and a counter substrate via an alignment film. The array substrate includes signal lines X and scanning lines Y arranged in a matrix on an insulating substrate such as glass, and a thin film transistor (TFT) 17 is disposed near the intersection of the signal lines X and scanning lines Y.
, And a pixel electrode is arranged via the. The opposing substrate is provided with an opposing electrode opposing a pixel electrode of an array substrate on an insulating substrate such as glass.

As shown in FIG. 2, the data signal line drive section 12 outputs a shift register 38 for sequentially outputting shift pulses based on the input horizontal start signal ST1 and horizontal clock signal CK1, and a shift register 38 based on the output of the shift register 38. A digital-to-analog conversion circuit (hereinafter, referred to as a digital-to-analog conversion circuit) that sequentially converts digital image data DATA input by
A D / A circuit 40) and a latch 42 for two horizontal pixel lines that latches and outputs the output of the D / A circuit 40 based on the load signal LD. Also, D / A
The circuit 40 is configured to receive the polarity inversion signal POL, and output an analog signal voltage Vsig based on the corresponding gray scale on the positive polarity side or the negative polarity side with respect to the reference voltage based on the polarity inversion signal POL.

The gate line driving section 14 is mainly constituted by a shift register, not shown, and sequentially transfers and outputs the input vertical start signal ST2 based on the vertical clock signal CK2, and outputs this via a buffer to the liquid crystal display panel 16 Are output as scanning pulses to each scanning line Y.

The control circuit 20 receives digital image data DATA, horizontal / vertical synchronization signals, and a reference clock signal CK from outside. Then, the data signal line driving unit 1
2 is a horizontal clock signal CK1 and a horizontal start signal ST.
1. The digital image data DATA, the load signal LD, and the polarity inversion signal POL are output, the vertical clock signal CK2 and the vertical start signal ST2 are output to the gate line drive unit 14, and the polarity inversion signal P is output to the counter electrode drive circuit unit 22.
OL is output.

In the following description, a specific example of the present invention will be simplified by taking an example of an area of 4 pixels in the horizontal line direction and 4 pixels in the vertical line direction.

First Inverting Driving Method As shown in FIG. 3, in a p-frame (p is a natural number), a positive voltage is applied to the liquid crystal layers of all pixels on the n-th line, and the n + 1-th line is also applied. A positive voltage is applied to the liquid crystal layers of all the pixels. Conversely, a negative voltage is applied to the (n + 2) th line and the (n + 3) th line. Then, in the p + 1 frame which is the next vertical display period, the polarity of the nth line and the n + 1th line are all inverted to the negative polarity, and the polarity of the n + 2th line and the n + 3 line are inverted to the positive polarity. Note that the positive polarity means that the pixel electrode voltage is maintained at a higher voltage side than the counter electrode voltage, and the negative polarity means the opposite.

In order to realize the first inversion driving method, the control circuit 20 includes a counter for counting the horizontal synchronizing signal Hsync, and the control circuit 20 goes high and low every two horizontal display periods (2H) as shown in FIG. The polarity inversion signal POL whose level is inverted is output. The polarity inversion signal POL is supplied to the vertical synchronization signal Vsync every frame period.
, And are set to have different levels between adjacent frames.

Based on such a polarity inversion signal POL,
The data signal line driver 12 outputs an analog signal voltage Vsig based on a corresponding gray scale on the positive polarity side or the negative polarity side with respect to the reference voltage.

The counter electrode drive circuit 22 also outputs a first level and a second level counter electrode voltage Vcom having a phase opposite to the analog signal voltage Vsig and lower than the first level, based on the polarity inversion signal POL. .

When the polarity is inverted every two horizontal display periods as in the first inversion driving method, the inversion cycle becomes longer than when the polarity is inverted every one horizontal display period. it can. Further, since the inversion period is long, unnecessary radiation (EMI) can be reduced.

In the above-described example, the data signal line driver 12
Performed the polarity inversion operation based on the polarity inversion signal POL. However, the digital image data DATA output inside the control circuit 20 can be controlled.

Second Inversion Driving Method In the second inversion driving method, the polarity is inverted every two horizontal display periods (2H) as in the first inversion driving method, and the pixels ( The polarity is inverted every 1 HV. That is, as shown in FIG.
In the p-th frame, the n-th line has a polarity of +-+-, and in the (p + 1) -th frame, the polarity is-++-+.

In this case, the D / A circuit 40 corresponding to the odd-numbered signal line X and the D / A circuit corresponding to the even-numbered signal line X
This is achieved by making the polarity inversion signal POL input to the circuit 40 and the circuit 40 have opposite phases. In this case, the common electrode voltage Vcom is set to a constant DC voltage.

According to this embodiment, the flicker is suppressed because the polarity is different between the adjacent signal lines as compared with the embodiment described above.

Third Inversion Driving Method FIG. 5 is a diagram showing a third inversion driving method. The feature of this inversion driving method is that it is different from the first inversion driving every two horizontal display periods (2H). The polarity is inverted, and the portion of the two horizontal periods to be inverted is shifted by one horizontal display period (1H) for each frame.

That is, in the p-th frame, the positive portion is the n-th line and the (n + 1) -th line. In the (p + 1) -th frame, the n + 1-th line and the (n + 2) -th line have the positive polarity, shifted by one horizontal display period. . Then, the polarity inversion is completed in four frames from the p frame to the p + 3 frame. Here, "complete the polarity inversion" means a state in which the polarity inversion is performed such that the number of positive and negative polarities becomes the same in all the pixels in four consecutive vertical display periods.

Even in this method, power consumption can be reduced by increasing the polarity inversion cycle.

In this inversion driving method, the polarity of the pixels in each horizontal line may be inverted as shown in FIG.

Fourth Inversion Driving Method In the third inversion driving method, as shown in FIG. 6, the polarity is inverted every three horizontal periods (3H). That is, the nth to n + 2th lines have positive polarity, and the nth to n + 5 lines have negative polarity. Then, the polarity is inverted in the next frame p + 1.

Fifth Inversion Driving Method In the fifth inversion driving method, as shown in FIG. 7, polarity inversion is performed every three horizontal periods (3H), and one horizontal period (1H) between adjacent frames. In this inversion driving method, the polarity inversion is completed in six frames.

Also in this inversion driving method, the polarity of the pixels for each horizontal line may be inverted as shown in FIG.

Sixth Inversion Driving Method In the sixth inversion driving method, as shown in FIG. 8, the polarity is inverted every four horizontal periods (4H) and the next inversion driving method is overlapped by one horizontal period (1H). In this frame, the polarity inversion portion is shifted. In this inversion driving method, the polarity inversion is completed in eight frames.

Also in this inversion driving method, the polarity may be inverted for the pixels for each horizontal line as shown in FIG.

Seventh Inversion Driving Method In the seventh inversion driving method, as shown in FIG. 9, the polarity is inverted every five horizontal periods (5H), and overlaps the next frame by two horizontal periods (2H). The polarity inversion portion is shifted as described above. In this inversion driving method, the polarity inversion is completed in 10 frames.

Also in this inversion driving method, the polarity may be inverted for the pixels for each horizontal line as shown in FIG.

Other Inversion Driving Method In the above embodiment, the method of inverting the polarity in two to five horizontal periods has been described. However, the present invention is not limited to this, and the polarity inversion may be performed in every six or more horizontal periods. The horizontal period overlapping with the next frame is not limited to one or two horizontal periods, and may be three or more horizontal periods. However, in this case, the condition is that the number of positive and negative polarities in the same horizontal line is the same during the period in which the polarity inversion is completed.

[0039]

As described above, according to the flat display device of the present invention, the inversion period is performed in two or more horizontal display periods, thereby increasing the polarity inversion cycle and reducing power consumption. Also,
Unnecessary radiation can be reduced, and unnecessary radiation countermeasures can be reduced. Therefore, low cost and narrow frame can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a driving circuit of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a signal line driving circuit.

FIG. 3 is a schematic diagram of a first inversion driving method.

FIG. 4 is a schematic diagram of a second inversion driving method.

FIG. 5 is a schematic diagram of a third inversion driving method.

FIG. 6 is a schematic diagram of a fourth inversion driving method.

FIG. 7 is a schematic diagram of a fifth inversion driving method.

FIG. 8 is a schematic diagram of a sixth inversion driving method.

FIG. 9 is a schematic diagram of a seventh inversion driving method.

FIG. 10 is a timing chart of each signal.

FIG. 11 is a schematic view of a conventional polarity inversion driving method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Drive circuit 12 Data signal line drive part 14 Gate line drive part 16 Matrix substrate part 18 Applied voltage generation circuit 20 Control circuit 22 Counter electrode drive circuit

Claims (9)

[Claims] A pixel electrode connected to a data signal line and a gate line via a switching element is arranged in a matrix, and a counter electrode facing the pixel electrode; With a light modulation layer in between,
A display panel including a plurality of horizontal pixel lines including a plurality of display pixels arranged along the gate line direction, and a drive circuit unit for applying a predetermined voltage to the data signal lines, the gate lines, and the counter electrode In the flat panel display device, the drive circuit unit performs a polarity inversion of a voltage applied to the light modulation layer by n times of one horizontal display period (n is an integer of 2 or more).
The flat display device is set in a unit of an inversion period, which is a period of the period. 2. The method according to claim 1, wherein the switching of the polarity every one vertical display period is performed in units of the inversion period, so that the polarity inversion is performed by making the number of times of the positive polarity and the negative polarity the same in all two consecutive vertical display periods. 2. The method according to claim 1, wherein
A flat display device as described in the above. 3. The method according to claim 1, wherein the switching of the polarity for each vertical display period is performed in units of the inversion period, and at the same time, the number of times is equal to m times the horizontal display period (m is n
By shifting the polarity inversion portion by the slip period which is a period of (smaller integer), the polarity inversion is performed by making the number of positive and negative polarities the same in all pixels in the continuous 2p (p is an integer) vertical display period. And 2p
2. The flat display device according to claim 1, wherein the number of positive and negative polarities in the same horizontal line during the vertical display period is the same. 4. The flat display device according to claim 1, wherein the polarity inversion is performed such that the polarity is inverted for each pixel adjacent in the horizontal line direction. 5. A pixel electrode connected to a data signal line and a gate line via a switching element is arranged in a matrix, and a counter electrode facing the pixel electrode; With a light modulation layer in between,
A display panel including a plurality of horizontal pixel lines including a plurality of display pixels arranged along the gate line direction, and a drive circuit unit for applying a predetermined voltage to the data signal lines, the gate lines, and the counter electrode Wherein the drive circuit outputs to the data signal line a signal voltage whose polarity is inverted with respect to a reference voltage at least every two horizontal scanning periods to a half vertical scanning period. A flat display device characterized by the above-mentioned. 6. The flat display device according to claim 5, wherein the driving circuit outputs a counter electrode voltage having a phase opposite to that of the signal voltage to the counter electrode every period. 7. The flat display device according to claim 5, wherein the polarities of the signal voltages are different between adjacent vertical scanning periods. 8. The flat display device according to claim 5, wherein a ratio between a positive polarity and a negative polarity of the signal voltage is set to be equal in a predetermined vertical scanning period. 9. The signal processing apparatus according to claim 8, wherein the polarity of the signal voltage includes a period different from an equal period in adjacent vertical scanning periods in the predetermined vertical scanning period.
A flat display device as described in the above.