JP2001306015A - Driving circuit for image display device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in the conventional device that signal line drive circuits of a digital system occupies a large area in an image display device and that this is an obstacle to reduction in size of the display device. SOLUTION: A storage circuit of a signal line drive circuit and D/A converter circuit are made to share n-pieces of signal lines (n is a natural number not smaller than 2) with each other. One horizontal scanning period is divided into n-pieces, and during each divided period, processing is performed to signal lines having respectively different storage circuits and D/A converter circuits, and thereby all the signal lines can be driven. Thus, it makes possible to reduce the number of the storage circuits and the D/A converter circuits in the signal line driving circuit to one n-th of that in the conventional device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates to a driving circuit of an image display device for inputting a digital video signal, and more particularly to a driving circuit of an image display device capable of reducing its occupied area, and an electronic apparatus.

[0003]

2. Description of the Related Art In recent years, an image display device in which a semiconductor thin film is formed on a glass substrate, particularly a thin film transistor (hereinafter referred to as TFT).
Active matrix type image display devices using the same are widely used. An active matrix image display device using TFTs has hundreds of thousands to millions of TFTs arranged in a matrix and controls the charge of each pixel.

Further, as a recent technology, in addition to a pixel TFT constituting a pixel, a polysilicon TFT in which a driving circuit is simultaneously formed using a TFT outside a pixel matrix is used.
Technology is evolving.

[0005] In addition, not only a drive circuit formed at the same time as that for an analog video signal but also a drive circuit for a digital video signal has been realized.

FIG. 19 shows a conventional example of an active matrix type liquid crystal display device which is a kind of an active matrix type image display device. As shown in FIG. 19, the liquid crystal display device includes a signal line driving circuit 101, a scanning line driving circuit 102, a pixel matrix 103, a signal line 104, a scanning line 105, a pixel TFT 106, a liquid crystal 107, and the like.

FIG. 20 explains in detail the configuration of a conventional signal line drive circuit. FIG. 21 is a timing chart for FIG. Here, k (horizontal)
An image display device having x1 (vertical) pixels will be described as an example. For the sake of simplicity, the digital signal takes 3 bits as an example, but the number of bits is not limited to 3 in an actual image display device. In FIGS. 20 and 21, k = 640 and a specific number are used.

A conventional signal line drive circuit has the following configuration. The shift register receives a clock signal (CLK) and a start pulse (SP), sequentially shifts a pulse, and a first latch circuit (LAT1) that receives an output signal of the shift register and sequentially stores a digital video signal. ), A second latch circuit (LAT) which latches the output of the first latch circuit in accordance with a latch pulse.
2) A D / A converter (DAC) for converting the output of the second latch circuit into an analog signal. Here, a latch circuit is used as the storage circuit.

The number of shift register stages (corresponding to the number of DFFs shown in FIG. 20) is k + 1. The output signal of the shift register is supplied directly or via a buffer to the control signal (SR-) of the first latch circuit (LAT1).
001-SR-640). The first latch circuit (L
AT1) latches digital video signals (D0 to D2) on digital video signal lines in accordance with the control signal.
Here, the first latch circuit (LAT1) is required for the number of digital video signal lines 3 (the number of bits) × k (the number of horizontal signal lines). The second latch circuit (LAT2) is also 3k
Just need.

The signal line drive circuit receives a shift register clock signal (CLK), a start pulse (SP), digital video signals (D0 to D2), and a latch pulse (LP). First, the shift register receives a start pulse (SP) and a clock signal (CLK), and sequentially shifts the pulse. Output of shift register (FIG. 20)
SR-001 to SR-640) are pulses shifted by one cycle of the clock signal (CLK) as shown in FIG. Depending on the output signal of the shift register, the first
Operates, and latches the digital video signal input at that time. By shifting the pulse of the shift register by one line,
The digital video signal for one line is supplied to the first latch circuit (L
AT1). (In FIG. 20, L1-001 to L1-001
1-640. However, for simplicity, the bits are collectively shown without distinction. )

Next, a latch pulse (L
P) is input, the second latch circuit (LAT2) operates by the latch pulse, and the video signal (L1-001 to L1 in FIGS. 20 and 21) stored in the first latch circuit (LAT1). −640) is stored in the second latch circuit (LAT2). When the retrace period ends and the next horizontal scanning period starts, the shift register starts operating again. On the other hand, the digital video signal (L2-0 in FIGS. 20 and 21) stored in the second latch circuit (LAT2)
01 to L2-640. However, for simplicity, the bits are collectively shown without distinction. ) Is a D / A conversion circuit (DA
In C), it is converted into an analog signal. This analog signal is sent to a signal line (S001 to S640 in FIG. 20), and is written to the pixel when the pixel TFT is turned on.

With the above operation, the image display device writes a video signal to the pixel and performs display.

[0013]

The digital driving circuit described above has a disadvantage that its occupied area is much larger than that of the analog driving circuit. The digital system has an advantage that a signal is represented by a binary value of “Hi” or “Lo”. However, the amount of data becomes huge instead. It has become. The increase in the area of the image display device causes an increase in the manufacturing cost thereof, and there is a problem that the profit of the manufacturing company is deteriorated.

Further, with the rapid increase in the amount of information to be handled in recent years, the number of pixels and the definition of pixels have been increased. However, as the number of pixels increases, the number of drive circuits also increases, and it is desired to reduce the area of the drive circuit.

Here, examples of the display resolution of a commonly used computer are shown below by the number of pixels and the standard name. Number of pixels Standard name 640 × 480 VGA 800 × 600 SVGA 1024 × 768 XGA 1280 × 1024 SXGA 1600 × 1200 UXGA

For example, taking the SXGA standard as an example,
Assuming that the number of bits is 8, the conventional driving circuit described above has 1 bit.
For each of the 280 signal lines, 10240 first memory circuits and 10240 second memory circuits are required. In addition, high-definition television receivers such as a high-definition TV (HDTV) have become widespread.
In this field, a high-definition image is required. Terrestrial digital broadcasting has begun in the United States, and the era of digital broadcasting will begin in Japan. In digital broadcasting, one having 1920 × 1080 pixels is the most prominent, and reduction of the driving circuit is urgently required.

However, as described above, the area occupied by the signal line driving circuit is large, which hinders downsizing of the image display device. In order to solve such a problem, the present invention provides an advantageous technique for reducing the area occupied by a signal line driving circuit and reducing the size.

[0018]

A memory circuit and a D / A conversion circuit in a signal line driving circuit are shared by n (n is a natural number of 2 or more) signal lines. One horizontal scanning period is divided into n, and in each of the divided periods, the storage circuit and the D / A conversion circuit process different signal lines, so that all signal lines are driven normally. be able to. In this manner, the storage circuit and the D / A conversion circuit in the signal line driving circuit are replaced with the conventional n
It becomes possible to make it 1/100.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, an image display device in which the number of pixels in the horizontal direction and the number of pixels in the vertical direction are generally k and l will be described as an example. In the present embodiment, the digital video signal is described as having three bits, but the present invention is not limited to three bits, and is also effective for 6 bits, 8 bits, or any other number of bits. In the following description, n is used as a parameter indicating how many signal lines are driven by one D / A conversion circuit. However, when the number k of pixels in the horizontal direction is not a multiple of n, it is appropriate to use k. And a number that is a multiple of n is newly defined as k. in this case,
If the added pixel is treated as a virtual one, there is no hindrance to the actual operation.

The configuration and operation of this embodiment will be described below. FIG. 1 shows an example of the signal line driving circuit of the present embodiment, and FIG.
Shows the operation timing. However, FIGS. 1 and 2 show specific examples of k = 640. In the following, symbols such as k are used for general description, but specific numbers corresponding to FIGS. 1 and 2 are shown in []. Note that the configuration of the scanning line driving circuit and the configuration of the pixel matrix are the same as those in the related art.

The signal line driving circuit according to the present embodiment includes a shift register including a delay flip-flop (DFF), a first storage circuit (LAT1), a second storage circuit (LAT2), and a D / A converter. It has a circuit (DAC) and a signal line selection circuit 10a. In FIG. 1, unlike the conventional example, two types of latch signal lines (LPa, LPb) are supplied, the first latch signal line (LPa) is provided in the first half of the second memory circuit, and the second latch signal line is provided in the second half. Latch signal line (LPb)
Are connected respectively.

As can be seen from FIG. 1, the number of circuits constituting the signal line driving circuit is approximately 1 / n [1/4] of the conventional example. That is, in the shift register, the DFF has (k / n) +1 stages [161 stages] and the first storage circuit (LA
T1) and the second storage circuit (LAT2) are each 3 k /
n [480] and a D / A conversion circuit (DAC) are composed of k / n [160]. Here, n is a natural number of 2 or more, which corresponds to driving n signal lines by one D / A conversion circuit. However, FIG. 1 specifically shows the case where n = 4.

Next, the operation will be described with reference to FIG. A start pulse (S
P) and a clock signal (CLK) are input. The shift register sequentially shifts the pulses in the same manner as in the conventional example, and outputs the pulses to the first storage circuit as sampling pulses of the digital video signal (shown in SR-001 to SR-160). In a conventional example, a start pulse is input once in one horizontal scanning period, whereas in the present embodiment, a start pulse is input n times [four times] in one horizontal scanning period. The digital video signals (D0 to D2) are sequentially stored in the first storage circuit by the output sampling pulse of the shift register (the bits are collectively shown as L1-001 to L1-160 without distinguishing the bits). Unlike the conventional example, when the arrangement order of the digital video signals is represented by the number of the corresponding signal line, “1, n +
1, 2n + 1,..., Kn + 1, 2, n + 2, 2n +
2, ..., kn-2,3, n + 3,2n + 3, ..., k-
n + 3, 4, ..., k "[" 1, 5, 9, ..., 637,
2, 6, 10, ..., 638, 3, 7, 11, ..., 63
9, 4, 8, 12, ..., 640 "].

In addition, the number of stages of the DFF is reduced to about 1 / n [1/4] as compared with the prior art, and the first storage circuit operates n times [4 times] during one horizontal scanning period. Is different from the conventional example.

The latch pulse input to the second storage circuit portion during one horizontal scanning period includes two types of latch signal lines (LP
a, LPb), n in each case, for a total of 2n [8
) Pulses. The latch pulse is input not only during the retrace period but also during the period when the digital video signal is being input. In this embodiment, a latch pulse is input at the following timing.

First, the (k / 2n) th stage [80th stage] DFF generated by the input of the first start pulse.
After the first storage circuit of the (k / 2n) th stage [80th stage] completes the storage operation by the sampling pulse output by the first stage, the first stage generated by the input of the second start pulse The first latch pulse is input to the first latch signal line (LPa) before the data in the first memory circuit in the first stage is rewritten by a new digital video signal by the sampling pulse output from the DFF. I do.

Next, the (k / n) stage [160th stage] DFF generated by the input of the first start pulse
After the first storage circuit at the (k / n) th stage [160th stage] completes the storage operation with the sampling pulse output by the first stage, the second start pulse is generated, and the (k / 2n) Before the (k / 2n) + 1-stage [81st] data in the first storage circuit is rewritten by a new digital video signal by the sampling pulse output from the DFF of the + 1st stage [81st] , The second latch pulse is input to the second latch signal line (LPb).

In the operation up to this point, the signal line numbers "1, n"
+1, 2n + 1,..., K−n + 1 ”[“ 1, 5, 9,.
637 "] has been transferred to the second storage circuit.

The third latch pulse corresponds to the first latch pulse described above.
In the description of inputting the second latch pulse, the “first start pulse” is replaced with the “second start pulse”.
At the timing when the “second start pulse” is replaced with the “third start pulse”.

The fourth latch pulse is based on the second latch pulse.
In the description of inputting the second latch pulse, the “first start pulse” is changed to the “second start pulse”, and the “second start pulse” is changed to “second start pulse”, as in the case of the third latch pulse. The timing is replaced with the "third start pulse".

In this operation, the signal line number "2, n +
2, 2n + 2, ..., kn + 2 "[" 2, 6, 10, ...,
638 "] has been transferred to the second storage circuit.

In general, the (2i-1) -th latch pulse is changed from “first start pulse” to “i-th start pulse” in the above description of inputting the first latch pulse. It is input at the timing when the “second start pulse” is replaced with the “(i + 1) th start pulse”. For the subsequent (2i) -th latch pulse, in the description of inputting the second latch pulse described above, the “first start pulse” is changed to the “i-th start pulse”, and the “second start pulse” is changed to “the second start pulse”. Start pulse "
Is replaced with the “(i + 1) th start pulse”. Here, i is a natural number satisfying i <n.

By these operations, the signal line numbers "i,
That is, the digital video signal corresponding to “n + i, 2n + i,..., kn + i” has been completely transferred to the second storage circuit.

The latch pulse may be input during one horizontal scanning period as described above, but the last (2n-
1) For the second n-th latch pulse, the timing is as follows.

That is, in the (2n-1) -th latch pulse, the sampling pulse output by the (k / 2n) -th [80th-stage] DFF generated by the input of the n-th start pulse is used. (K / 2n) The first stage generated by the input of the first start pulse in the next horizontal scanning period after the first storage circuit of the 80th stage has completed the storage operation Before the data in the first storage circuit in the first stage is rewritten by a new digital video signal by the sampling pulse output from the DFF, the latch pulse is input to the first latch signal line (LPa).

The second n-th latch pulse is generated by the input of the n-th start pulse.
After the first memory circuit of the (k / n) th stage [160th stage] completes the storage operation by the sampling pulse output from the DFF of the (k / n) th stage [160th stage], the next horizontal (K / 2n) + 1st stage [81st stage] In response to the sampling pulse output by the (k / 2n) + 1st stage [81st stage] DFF generated by the input of the first start pulse in the scanning period. Before the data in the first storage circuit is rewritten by a new digital video signal, a latch pulse is input to the second latch signal line (LPb).

By these operations, the signal line numbers "n,
2n, 3n, ..., k "[" 4, 8, 12, ..., 640 "]
Has been transferred to the second storage circuit.

With the input of the latch pulse as described above,
This means that all the digital video signals for one row of the signal line have been transferred to the second storage circuit.

In the above description, the latch pulse is input 2n times [8 times] in one horizontal scanning period. However, the clock is temporarily stopped every time one scan of the shift register is completed, and the next scan is performed. May be input before the start of the operation. In this case, one type of latch signal line may be used, and the input of the latch pulse is performed n times [four times] during one horizontal scanning period.

The output of the second storage circuit is input to a D / A conversion circuit, and a 3-bit digital signal is converted into an analog signal. The converted analog signal is written to an appropriate signal line via the signal line selection circuit 10a. less than,
The write timing will be described.

In one horizontal scanning period, the shift register scans n times, and the second storage circuit also operates n times as described above.
The memory operation is repeated twice. Therefore, while the digital video signal for a certain signal line is stored in the second storage circuit, the corresponding signal line must be selected and the writing must be completed.

First, the signal line numbers "1, n + 1, 2n +
1,... Kn + 1 ”[“ 1, 5, 9,... 637 ”] during the period in which the digital video signal corresponding to“ 1, 5, 9,. A pulse is input to one control signal line (SS1), and each signal line selection circuit 10a outputs "1, n + 1, 2n + 1, ..., k-n + 1".
The [1, 5, 9,..., 637]] th signal line is selected.

Next, the data in the second storage circuit is renewed, and the signal line numbers "2, n + 2, 2n + 2,..., Kn"
+2 ”[“ 2, 6, 10,..., 638 ”] during the period in which the digital video signal corresponding to“ 2, 6, 10,..., 638 ”is stored in the second storage circuit unit. SS
2), and each signal line selection circuit 10a outputs “2, n + 2, 2n + 2,... Kn + 2” [“2, 6,.
, 638 "] th signal line.

Generally, assuming that i is a natural number, the digital video signal corresponding to the signal line number “i, n + i, 2n + i,..., K−n + i” is stored in the second storage circuit during the period. The i-th control signal line (S
Si), a pulse is input, and each signal line selection circuit 10a selects the “i, n + i, 2n + i,..., Kn + i” th signal line, respectively.

Thus, n times in one horizontal scanning period,
By inputting a control signal pulse to the signal line selection circuit 10a, the output of the D / A conversion circuit can be written to an appropriate signal line.

Note that a buffer circuit, a level shift circuit, an enable circuit for limiting an output period, and the like may be provided between the output of the second storage circuit and the D / A conversion circuit. The input arrangement order of the digital video signals is not limited to the above order. This arrangement order is determined by the operation method of the signal line selection circuit.

In the above description of the embodiment, a shift register is used as a circuit for controlling the first storage circuit, but a decoder circuit may be used instead of the shift register. Further, a ramp type D / A conversion circuit may be used as the D / A conversion circuit. In that case, the number of D / A conversion circuits is not limited to k / n.

[0048]

(Embodiment 1) In the present embodiment, an image display device conforming to the XGA standard having 1024 pixels in the horizontal direction and 768 pixels in the vertical direction will be described as an example. In the present embodiment, the digital video signal is described as having three bits, but the present invention is not limited to three bits, but is also effective for six bits, eight bits, or any other number of bits. It is also assumed that one D / A conversion circuit drives four signal lines.

The configuration of this embodiment will be described below, and then the operation of this embodiment will be described.

FIG. 3 shows an example of a signal line driving circuit using the present invention. The configuration of the scanning line driving circuit and the configuration of the pixel matrix are the same as those in the related art. The signal line drive circuit of the present embodiment has 2
A shift register composed of 57 DFFs and 256 × 3
It has a (bit) first storage circuit, the same number of second storage circuits, and 256 D / A conversion circuits. The output of the D / A conversion circuit is connected to a signal line via a signal line selection circuit 10b.

The shift register has a start pulse (S
P) and a clock signal (CLK) are input to the second storage circuit (LAT2), and two types of latch signal lines (LP
a, LPb) are supplied, a first latch signal line (LPa) is connected to the first half of the second memory circuit, and a second latch signal line (LPb) is connected to the second half of the second memory circuit. The signal line selection circuit 10b has four control signal lines (SS1 to SS4)
Are connected respectively.

Next, the operation will be described with reference to FIG. A start pulse (S
P) and a clock signal (CLK) are input. The shift register sequentially shifts the pulse in the same manner as in the conventional example, and outputs it to the first storage circuit as a sampling pulse of the digital video signal [shown in SR-001 to SR-256]. In the conventional example, a start pulse is input once in one horizontal scanning period, whereas in the present embodiment, a start pulse is input four times in one horizontal scanning period. A digital video signal (D0 to D0) is generated by the output sampling pulse of the shift register.
2) are sequentially stored in the first storage circuit (the bits are collectively shown as L1-001 to L1-256 without distinction of bits). Unlike the conventional example, the arrangement order of digital video signals is
Expressed by the number of the corresponding signal line, "1, 5, 9,
..., 1021, 2, 6, 10, ..., 1022, 3, 5,
11, ..., 1023, 4, 8, 12, ..., 1024 ".

Further, the number of stages of the DFF is reduced to about one-fourth as compared with the related art, and the first memory circuit is different from the related art in that the first memory circuit performs the storing operation four times during one horizontal scanning period.

The latch pulse input to the second storage circuit section during one horizontal scanning period includes two types of latch signal lines (LP
a, LPb), a total of eight pulses, four each. The latch pulse is input not only during the retrace period but also during the period when the digital video signal is being input. In this embodiment, a latch pulse is input at the following timing.

First, after the first storage circuit in the 128th stage completes the storage operation by the sampling pulse output from the 128th stage DFF generated by the input of the first start pulse, the second operation is performed. Before the data in the first storage circuit in the first stage is rewritten with a new digital video signal by the sampling pulse output from the first stage DFF generated by the input of the start pulse of
The first latch pulse is supplied to the first latch signal line (LP
Enter in a).

Next, after the first storage circuit in the 256th stage completes the storage operation by the sampling pulse output from the 256th stage DFF generated by the input of the first start pulse, the second operation is performed. Before the data in the 129th stage is rewritten with a new digital video signal by the sampling pulse output from the 129th stage DFF generated by the input of the start pulse, the second latch is performed. The pulse is input to the second latch signal line (LPb).

In the operation so far, the signal line number “1,
, 1021, "1021" has been completely transferred to the second storage circuit.

The third latch pulse is the first latch pulse described above.
In the description of inputting the second latch pulse, the “first start pulse” is replaced with the “second start pulse”.
At the timing when the “second start pulse” is replaced with the “third start pulse”.

The fourth latch pulse is the second latch pulse described above.
In the description of inputting the second latch pulse, the “first start pulse” is changed to the “second start pulse”, and the “second start pulse” is changed to “second start pulse”, as in the case of the third latch pulse. The timing is replaced with the "third start pulse".

In this operation, the signal line numbers “2, 6,
That is, the transfer of the digital video signal corresponding to “10,..., 1022” to the second storage circuit is completed.

In general, the (2i-1) -th latch pulse may be changed from “first start pulse” to “i-th start pulse” in the description of inputting the first latch pulse. It is input at the timing when the “second start pulse” is replaced with the “(i + 1) th start pulse”. For the subsequent (2i) -th latch pulse, in the description of inputting the second latch pulse described above, the “first start pulse” is changed to the “i-th start pulse”, and the “second start pulse” is changed to “the second start pulse”. Start pulse "
Is replaced with the “(i + 1) th start pulse”. Here, i is a natural number satisfying i <4.

By these operations, the signal line numbers “i,
That is, the digital video signal corresponding to “4 + i, 8 + i,..., 1020 + i” has been completely transferred to the second storage circuit.

The latch pulse may be input during one horizontal scanning period as described above. The timing of the last seventh and eighth latch pulses is as follows.

In other words, in the seventh latch pulse, the 128th stage first storage circuit is operated by the sampling pulse output from the 128th stage DFF generated by the input of the fourth start pulse. Is completed, the data in the first storage circuit in the first stage is changed by the sampling pulse output by the first stage DFF generated by the input of the first start pulse in the next horizontal scanning period. Before being rewritten by a new digital video signal, the latch pulse is supplied to the first latch signal line (LP).
Enter in a).

The last, eighth latch pulse is generated by the input of the fourth start pulse.
After the 256th-stage first storage circuit completes the storage operation with the sampling pulse output from the 256th-stage DFF, the 129th stage generated by the input of the first start pulse in the next horizontal scanning period Before the data in the 129th stage in the first storage circuit is rewritten with a new digital video signal by the sampling pulse output from the DFF, the latch pulse is changed to the second latch signal line (LP).
Input to b).

By these operations, the signal line number “4,
, 1024 "has been completely transferred to the second storage circuit.

With the input of the latch pulse as described above,
This means that all the digital video signals for one row of the signal line have been transferred to the second storage circuit.

In the above description, the latch pulse is input eight times in one horizontal scanning period. However, the clock is temporarily stopped every time the scanning of the shift register is completed once.
A latch pulse may be input before the next scan starts.
In this case, one type of latch signal line may be used, and the input of the latch pulse is performed four times during one horizontal scanning period.

The output of the second storage circuit is input to a D / A conversion circuit, and a 3-bit digital signal is converted into an analog signal. The converted analog signal is written to an appropriate signal line via the signal line selection circuit 10b. less than,
The write timing will be described.

In one horizontal scanning period, the shift register scans four times, and as described above, the second storage circuit also operates four times.
The memory operation is repeated twice. Therefore, while the digital video signal for a certain signal line is stored in the second storage circuit, the corresponding signal line must be selected and the writing must be completed.

First, signal line numbers “1, 5, 9,..., 1”
During the period in which the digital video signal corresponding to “021” is stored in the second storage circuit section, a pulse is input to the first control signal line (SS1) of the signal line selection circuit 10b, and each signal line selection circuit Reference numeral 10b selects the “1, 5, 9,..., 1021” th signal line, respectively.

Next, the data in the second storage circuit is renewed, and the digital video signals corresponding to the signal line numbers “2, 6, 10,..., 1022” are stored in the second storage circuit section. During the time period in which the signal line selection circuit 10b receives a pulse, the pulse is input to the second control signal line (SS2) of the signal line selection circuit 10b.
b selects the “2, 6, 10,..., 1022” th signal lines, respectively.

Generally, assuming that i is a natural number, the digital video signal corresponding to the signal line number “i, 4 + i, 8 + i,..., 1020 + i” is stored in the second storage circuit during the signal line selection. The i-th control signal line (S
Si), a pulse is input, and each signal line selection circuit 10b selects the “i, 4 + i, 8 + i,..., 1020 + i” th signal line.

Thus, four times during one horizontal scanning period,
By inputting a control signal pulse to the signal line selection circuit 10b, the output of the D / A conversion circuit can be written to an appropriate signal line.

Note that a buffer circuit, a level shift circuit, an enable circuit for limiting an output period, and the like may be provided between the output of the second storage circuit and the D / A conversion circuit.

FIG. 5 shows a specific example of the storage circuit. FIG.
FIG. 5A shows an example using a clocked inverter, FIG. 5B shows an SRAM type, and FIG.
AM type. These are representative examples, and the present invention is not limited to these types.

As described above, according to the present invention, the conventional quarter shift register, the conventional quarter first storage circuit, the conventional quarter second storage circuit, Quarter
The image display device can be driven by the D / A conversion circuit, and the area occupied by the drive circuit and the number of elements can be significantly reduced.

In this embodiment, the control signal for the first storage circuit is generated using the shift register. However, the present invention is not limited to the shift register, and a decoder circuit may be used.

(Embodiment 2) In this embodiment, an example in which a ramp type D / A conversion circuit is adopted as the D / A conversion circuit will be described. FIG. 6 is a schematic diagram of a signal line driving circuit in the case where a ramp type D / A conversion circuit is used. In this embodiment, the XGA
A case in which a standard image display device supports a 3-bit digital video signal will be described. However, the present invention is not limited to a 3-bit digital video signal.
The present invention is also effective for a case where the number of bits is other than that, and for an image display device of a standard other than XGA.

The configuration of the present embodiment will be described below, and then the operation of the present embodiment will be described.

This embodiment is the same as the first embodiment from the shift register to the second storage circuit. Downstream of the second storage circuit, a bit comparison pulse width conversion circuit (BPC),
It has an analog switch 20 and a signal line selection circuit 10c. The 3-bit digital video signal, the count signal (C0 to C2), and the set signal (ST) stored in the second storage circuit are input to the bit comparison pulse width conversion circuit (BPC). The output of the bit comparison pulse width conversion circuit (PW-i, i is 00
1 to 256) and a gradation power supply (VR). The output of the analog switch 20 and the control signals (SS1 to SS4) are input to the signal line selection circuit 10c.

FIG. 8 shows a configuration example of the ith bit comparison pulse width conversion circuit (BPC). The BPC has an exclusive OR gate, a three-input NAND gate, an inverter, and a set / reset flip-flop (RS-FF). In FIG. 8, the output of the second storage circuit at the i-th stage is represented by L2-i (0), L2-i (1), L2-i
(2).

Next, the operation of this embodiment will be described.
FIG. 7 shows the operation timing of the signal system necessary for understanding the outline of the circuit operation of FIG. The operation from the shift register to the second storage circuit is the same as in the first embodiment. The control signal (SS) input to the signal line selection circuit 10c
1 to SS4) are the same as in the first embodiment. Each time four signal lines are sequentially selected by the signal line selection circuit 10c, a count signal (C0 to C2), a set signal (ST), and a gradation power supply (VR) are periodically input. Thus, information can be written to all signal lines equally.

In order to explain the detailed operation of the ramp type D / A conversion circuit, FIG. 9 shows the operation timing during a period when one of the four signal lines is selected by the signal line selection circuit. First, the RS-FF 30 is set by the input of the set signal, and the output PW-i becomes Hi level. next,
The digital video signal stored in the second storage circuit is
The count signal (C0 to C
2) is compared bit by bit. If all three bits match, the outputs of all exclusive OR gates go high, and as a result, the output (RC-i) of the three-input NAND gate goes low (thus, RC-).
i becomes Hi level). The output of the three-input NAND is also input to the RS-FF 30, and is reset when RC-i becomes Hi level, and the output PW-i returns to Lo level.
FIG. 9 shows a 3-bit digital video signal {L2-i}.
(0), L2-i (1) L2-i (2)} is {0, 0,
Output examples of RC-i, PW-i, and DA-i for the case of 1 are shown. Thus, the information of the digital video signal is output from the output PW-i of the bit comparison pulse width conversion circuit (BPC).
Is converted to a pulse width.

The output PW-i of the bit comparison pulse width conversion circuit (BPC) controls opening and closing of the analog switch 20. The analog switch 20 has a count signal (C0 to C
2) A gray scale power supply (V) having a step-like voltage level synchronized with
R) is applied, the BPC output PW-i conducts to the signal line only during the Hi level, and the voltage at the moment when the PW-i becomes the Lo level is written to the signal line.

With the above operation, the digital video signal is converted into the analog signal, and the signal line is driven. Note that the gradation power supply (VR) does not need to be stepwise, and may be a monotonous one that changes continuously. Further, between the output of the bit comparison pulse width conversion circuit (BPC) and the analog switch 20,
A buffer circuit, a level shift circuit, and the like may be provided.

As described above, in the present invention, a ramp type D / A conversion circuit can be used as the D / A conversion circuit.
The circuit configuration is only about one-fourth of the conventional one, and the area occupied by the drive circuit and the number of elements can be significantly reduced.

(Embodiment 3) In this embodiment, Embodiments 1 and 2
As a specific example of a method of manufacturing an active matrix type image display device using the driving circuit described in the above section, a method of manufacturing an active matrix type liquid crystal display device will be described as an example.
In particular, here, the pixel T which is a switching element of the pixel portion
A method for manufacturing an FT and a TFT of a driver circuit (a signal line driver circuit, a scan line driver circuit, or the like) provided around the pixel portion over the same substrate will be described in detail according to steps. However, for the sake of simplicity, a CMOS circuit, which is a basic configuration circuit, is shown as a driving circuit unit, and an n-channel TFT is shown as a pixel TFT unit.

In FIG. 10A, a low alkali glass substrate or a quartz substrate can be used as a substrate (active matrix substrate) 6001. In this embodiment, a low alkali glass substrate was used. In this case, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. A base film 6002 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a surface of the substrate 6001 where a TFT is to be formed, in order to prevent impurity diffusion from the substrate 6001. For example, plasma C
A silicon oxynitride film formed from SiH ₄ , NH ₃ , and N ₂ O is formed to a thickness of 100 nm by the VD method, and a silicon oxynitride film formed from SiH ₄ and N ₂ O is similarly formed to a thickness of 200 nm.

Next, 20 to 150 nm (preferably 30 nm)
Semiconductor film 60 having an amorphous structure with a thickness of
03a is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 54 nm by a plasma CVD method. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used.
In addition, since the base film 6002 and the amorphous silicon film 6003a can be formed by the same film formation method, both may be formed continuously. In that case, after forming the base film,
By not once exposing to the air atmosphere, the surface can be prevented from being contaminated, and the variation in the characteristics of the TFT to be manufactured and the fluctuation of the threshold voltage can be reduced (FIG. 10).
(A)).

Then, the amorphous silicon film 6003a is converted to the crystalline silicon film 6003 by using a known crystallization technique.
b is formed. For example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied. Here, according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652, crystallization is performed by a crystallization method using a catalyst element. Quality silicon film 6003b
Was formed. Prior to the crystallization step, depending on the amount of hydrogen contained in the amorphous silicon film, heat treatment may be performed at 400 to 500 ° C. for about 1 hour to reduce the amount of hydrogen to 5 atom% or less before crystallization. desirable. When the amorphous silicon film is crystallized, rearrangement of atoms occurs and the film becomes denser. Therefore, the thickness of the crystalline silicon film to be formed is set to be smaller than the initial thickness of the amorphous silicon film (54 nm in this embodiment). Also 1
It is reduced by about 15% (FIG. 10B).

Then, the crystalline silicon film 6003b is patterned into an island shape to form island-like semiconductor layers 6004 to 604.
07 is formed. After that, a mask layer 6008 made of a silicon oxide film having a thickness of 50 to 150 nm is formed by a plasma CVD method or a sputtering method. (FIG. 10
(C)).

Then, a resist mask 6009 is provided, and n
Island-like semiconductor layer 6 for forming a channel type TFT
1 × 10 ^{16 to} 5 × 10 ¹⁷ atom on the entire surface of 005 to 6007
Boron (B) is added at a concentration of about s / cm ³ as an impurity element imparting p-type. This addition of boron (B) is performed for the purpose of controlling the threshold voltage. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. Here, boron (B) addition is not always necessary (FIG. 10D). After that, the resist mask 6009 is removed.

LDD region of n-channel type TFT of drive circuit
In order to form the region, the impurity element imparting n-type
It is selectively added to the semiconductor layers 6010 to 6012. That
Therefore, the resist masks 6013 to 6016 are
Form. As an impurity element imparting n-type, phosphorus
(P) or arsenic (As) may be used.
Phosphine (PH) to add (P)_Three)
An ion doping method was applied. Impurity region 60 formed
The phosphorus (P) concentration of 17, 6018 is 2 × 10¹⁶~ 5 × 1
0¹⁹atoms / cm^ThreeShould be within the range. In this specification,
Included in impurity regions 6017 to 6019 formed here
(N) ^-) And table
You. Further, the impurity region 6019 serves as a storage capacitor of the pixel portion.
This is the semiconductor layer to be formed.
To add phosphorus (P) (FIG. 11 (A)). After that,
The distant masks 6013-6016 are removed.

Next, after removing the mask layer 6008 with hydrofluoric acid or the like, a step of activating the impurity element added in FIGS. 10D and 11A is performed. Activation is 5
It can be performed by a heat treatment for 1 to 4 hours in a nitrogen atmosphere at 00 to 600 ° C. or a laser activation method.
Moreover, you may perform it using both together. In this embodiment, a laser activation method is used. K for laser light
rF excimer laser light (wavelength 248 nm) is used.
In this embodiment, the laser beam is processed into a linear beam and used at an oscillation frequency of 5 to 50 Hz and an energy density of 10 to 50 Hz.
The entire surface of the substrate on which the island-shaped semiconductor layer is formed is processed by scanning the linear beam at an overlap ratio of 80 to 98% at 0 to 500 mJ / cm ² . Note that there are no particular restrictions on the laser light irradiation conditions, and they can be determined appropriately.

Then, a gate insulating film 6020 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm by a plasma CVD method or a sputtering method. For example, 12
A silicon oxynitride film is formed with a thickness of 0 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (FIG. 11B)

Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, or may be formed as a two-layer or three-layer structure as necessary. In this embodiment, a conductive layer (A) 6021 made of a conductive nitride metal film and a conductive layer (B) 6022 made of a metal film are stacked. Conductive layer (B) 602
2 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the above elements as a main component, or an alloy film combining the above elements (typically, The conductive layer (A) 6021 may be formed of tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), or molybdenum nitride (MoN). Form. The conductive layer (A) 6021 is used as an alternative material.
Tungsten silicide, titanium silicide, or molybdenum silicide may be used. The conductive layer (B) preferably has a reduced impurity concentration for low resistance, and particularly preferably has an oxygen concentration of 30 ppm or less. For example, tungsten (W) has an oxygen concentration of 30 pp.
m or less, a specific resistance of 20 μΩcm or less can be realized.

The conductive layer (A) 6021 has a thickness of 10 to 50 nm.
(Preferably 20 to 30 nm), and the conductive layer (B) 60
22 is 200 to 400 nm (preferably 250 to 350 nm)
nm). In this embodiment, the conductive layer (A) 60
A 21 nm-thick tantalum nitride film was used for 21, and a 350 nm-thick Ta film was used for the conductive layer (B) 6022, both of which were formed by sputtering. In the film formation by the sputtering method, if an appropriate amount of Xe or Kr is added to Ar of the gas for sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 6021. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 6020. Can be prevented (FIG. 11C).

Next, the resist masks 6023 to 6027
Are formed, and a conductive layer (A) 6021 and a conductive layer (B) 602 are formed.
2 and the gate electrodes 6028-60
31 and a capacitor wiring 6032 are formed. Gate electrode 602
8 to 6031 and the capacitor wiring 6032 are formed integrally with 6028a to 6032a made of a conductive layer (A) and 6028b to 6032b made of a conductive layer (B). At this time, the gate electrode 6 of the TFT constituting the driving circuit
028 to 6030 are formed so as to overlap with part of the impurity regions 6017 and 6018 with the gate insulating film 6020 interposed therebetween (FIG. 11D).

Next, in order to form a source region and a drain region of the p-channel TFT of the driving circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligned manner using the gate electrode 6028 as a mask. At this time, the n-channel TFT
Are formed with a resist mask 6033. Then, an impurity region 6034 was formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . After that, the resist mask 6033 is removed. In this specification, the impurity region 6 formed here is used.
The concentration of the impurity element imparting p-type contained in No. 034 is represented by (p ⁺⁺ ) (FIG. 12A).

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 6035 to 6037 were formed, and impurity regions 6039 to 6042 were formed by adding an impurity element imparting n-type. This is performed by an ion doping method using phosphine (PH ₃ ), and the phosphorus (P) concentration in this region is set to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / c.
It was m ^3. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6039 to 6042 formed here is expressed as (n ⁺ ) (FIG. 12B).

Although impurity regions 6039 to 6042 contain phosphorus (P) or boron (B) already added in the previous step, phosphorus (P) is added at a sufficiently high concentration. Therefore, it is not necessary to consider the influence of phosphorus (P) or boron (B) added in the previous step.
The concentration of phosphorus (P) added to impurity region 6038 is １ ／ of the concentration of boron (B) added in FIG.
Since it was １ ／, p-type conductivity was ensured, and there was no effect on the characteristics of the TFT.

After removing the resist masks 6035 to 6037, an n-type impurity imparting step for forming an LDD region of an n-channel TFT in a pixel portion was performed. Here, an impurity element imparting n-type in a self-aligned manner is added by an ion doping method using the gate electrode 6031 as a mask. The concentration of phosphorus (P) to be added is 1 × 10 ^{16 to} 5 ×
10 ¹⁸ atoms / cm ³ , as shown in FIG.
By adding at a concentration lower than the concentration of the impurity element added in FIGS.
Only 43 and 6044 are formed. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6043 and 6044 is expressed as (n ⁻ ). (FIG. 12
(C))

Thereafter, a heat treatment step is performed to activate the n-type or p-type imparting impurity elements added at the respective concentrations. This process is furnace annealing,
It can be performed by a laser annealing method or a rapid thermal annealing method (RTA method). Here, the activation step was performed by the furnace annealing method. The heat treatment is performed in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, at 400 to 800 ° C., typically 500 to 60 ° C.
The heat treatment is performed at 0 ° C., and in this embodiment, the heat treatment is performed at 500 ° C. for 4 hours. When a substrate having heat resistance such as a quartz substrate is used for the substrate 6001, 800
The heat treatment may be performed at 1 ° C. for 1 hour, whereby the activation of the impurity element and the junction between the impurity region to which the impurity element is added and the channel formation region can be favorably formed. In addition,
This effect may not be obtained when an interlayer film is formed to prevent the peeling of Ta as the gate electrode described above.

In this heat treatment, the gate electrode 6028
Film 602 forming the capacitor wiring 6032 and the capacitor wiring 6032
For 8b to 6032b, conductive layers (C) 6028c to 6032c are formed with a thickness of 5 to 80 nm from the surface. For example, when the conductive layers (B) 6028b to 6032b are tungsten (W), tungsten nitride (WN) is formed, and when the conductive layers (B) 6028b to 6032b are tantalum (Ta), tantalum nitride (Ta) is formed.
N) can be formed. The conductive layer (C) 60
28c to 6032c are gate electrodes 6028 to 3028 in a plasma atmosphere containing nitrogen using nitrogen or ammonia.
Even when the capacitor 6031 and the capacitor wiring 6032 are exposed, they can be similarly formed. Further, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to hydrogenate the island-shaped semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma or hydrogenated into plasma) may be performed.

The island-like semiconductor layer is formed from the amorphous silicon film.
When produced by the crystallization method using a medium element,
A trace amount of catalytic element remained in the conductor layer. Of course
It is possible to complete the TFT in such a state,
Remove the remaining catalyst element from at least the channel formation region.
I preferred to leave. Remove this catalytic element
Utilizing the gettering action of phosphorus (P) as one of the means
There was a way to do that. Phosphorus (P) required for gettering
The concentration is the impurity region (n ⁺Same as)
Of the activation process performed here.
And n-channel TFT and p-channel TFT.
Gettering of catalytic elements from the channel formation region
It was completed (FIG. 12 (D)).

When the activation and hydrogenation steps are completed,
A second conductive film serving as a gate wiring (scanning line) is formed.
This second conductive film is made of aluminum (A) which is a low-resistance material.
l) a conductive layer (D) mainly composed of copper (Cu) and a conductive layer (E) made of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo). good. In the present embodiment, titanium (Ti) is set to 0.1.
An aluminum (Al) film containing 1 to 2% by weight is used as the conductive layer (D) 6045, and a titanium (Ti) film is used as the conductive layer (E).
6046. The conductive layer (D) 6045 is 20
The conductive layer (E) 6046 may be formed to have a thickness of 50 to 200 (preferably 100 to 150 nm). (Figure 1
3 (A))

Then, the conductive layer (E) 6046 and the conductive layer (D) 6045 are etched to form a gate wiring (scanning line) connected to the gate electrode, and gate wirings (scanning lines) 6047 and 6048 are formed. And a capacitor wiring 6049 were formed. In the etching process, first, a portion of the conductive layer (D) is removed from the surface of the conductive layer (E) by a dry etching method using a mixed gas of SiCl ₄ , Cl _2, and BCl ₃ ,
Thereafter, the conductive layer (D) was removed by wet etching using a phosphoric acid-based etching solution, whereby a gate wiring (scanning line) could be formed while maintaining selectivity with the base.

The first interlayer insulating film 6050 is 500 to 15
A contact hole which is formed of a silicon oxide film or a silicon oxynitride film with a thickness of 00 nm and reaches a source region or a drain region formed in each of the island-shaped semiconductor layers is formed.
6054 and drain wirings 6055 to 6058 are formed. Although not shown, in this embodiment, this electrode is
100 nm film, 300n aluminum film containing Ti
A laminated film having a three-layer structure was formed by continuously forming an m and Ti film of 150 nm by a sputtering method.

Next, as the passivation film 6059, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is 50 to 500 nm (typically, 100 to 3 nm).
(00 nm). When hydrogenation treatment was performed in this state, favorable results were obtained for improving the characteristics of the TFT. For example, in an atmosphere containing 3 to 100% hydrogen,
It is preferable to perform heat treatment at 300 to 450 ° C. for 1 to 12 hours, or similar effects can be obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 6059 at a position where a contact hole for connecting a pixel electrode and a drain wiring is formed later. (FIG. 13 (C))

Thereafter, a second interlayer insulating film 6060 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide,
Polyimide amide, BCB (benzocyclobutene) and the like can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used. Then, a contact hole reaching the drain wiring 6058 is formed in the second interlayer insulating film 6060, and pixel electrodes 6061 and 6062 are formed. As the pixel electrode, a transparent conductive film may be used for a transmission type liquid crystal display device, and a metal film may be used for a reflection type liquid crystal display device. In this embodiment, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film has a thickness of 100 n.
m was formed by a sputtering method. (FIG. 14)

Thus, the TFT of the driving circuit is formed on the same substrate.
And a substrate having pixel TFTs in the pixel portion. The driving circuit includes a p-channel TFT 6101,
A first n-channel TFT 6102, a second n-channel TFT 6103, a pixel TFT 6104 in the pixel portion, and a storage capacitor 6105 were formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the p-channel TFT 6101 of the driver circuit, the channel formation region 610 is formed in the island-shaped semiconductor layer 6004.
6, source regions 6107a and 6107b, and drain regions 6108a and 6108b. In the first n-channel TFT 6102, an L overlapping the channel formation region 6109 and the gate electrode 6029 in the island-shaped semiconductor layer 6005.
DD region 6110 (hereinafter, such an LDD region is referred to as Lov
, Source region 6111 and drain region 6112
have. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. The second n-channel TFT 6103 includes a channel formation region 6113, LDD regions 6114 and 6115, a source region 6116, and a drain region 6117 in the island-shaped semiconductor layer 6006. This LDD region is an LDD region that does not overlap with the Lov region and the gate electrode 6030 (hereinafter referred to as an LDD region).
Such an LDD region is referred to as Loff).
The length of the Loff region in the channel length direction is 0.3 to 2.
0 μm, preferably 0.5 to 1.5 μm. Pixel T
In the FT 6104, channel formation regions 6118 and 6119 and Loff regions 6120 to 61 are formed in the island-shaped semiconductor layer 6007.
23, a source or drain region 6124-6126. The length of the Loff region in the channel length direction is 0.
It is 5-3.0 μm, preferably 1.5-2.5 μm. Further, the capacitor wirings 6032 and 6049, an insulating film made of the same material as the gate insulating film, and a pixel TFT 6104
From the semiconductor layer 6127 to which the impurity element imparting n-type is added.
105 is formed. In FIG. 14, the pixel TFT 610
4 has a double gate structure, but may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

As described above, in this embodiment, it is necessary to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the driving circuit, and to improve the operation performance and reliability of the image display device. Can be possible.

Next, a process for manufacturing a transmission type liquid crystal display device based on the active matrix substrate manufactured by the above process will be described.

Referring to FIG. An alignment film 6201 is formed on the active matrix substrate in the state shown in FIG. In this embodiment, polyimide is used for the alignment film 6201. Next, a counter substrate is prepared. The opposite substrate is a glass substrate 62
02, light-shielding film 6203, counter electrode 6 made of a transparent conductive film
204 and an alignment film 6205.

In this embodiment, a polyimide film in which liquid crystal molecules are aligned in parallel with the substrate is used as the alignment film. After the alignment film was formed, a rubbing treatment was performed so that the liquid crystal molecules were aligned in parallel with a certain pretilt angle.

Next, the active matrix substrate and the counter substrate having undergone the above-described steps are subjected to a known cell assembling step to perform
It is bonded via a sealing material or a spacer (both not shown). Thereafter, a liquid crystal 6206 is injected between the two substrates, and completely sealed with a sealant (not shown). Thus, a transmission type liquid crystal display device as shown in FIG. 15 is completed.

The TFT formed by the above process
Has a top gate structure but a bottom gate structure TF
The present invention can be applied to TFTs having T or other structures.

Although the image display device produced by the above process is a transmission type liquid crystal display device, the present invention can be applied to a reflection type liquid crystal display device.

(Embodiment 4) In this embodiment, an electronic apparatus incorporating an active matrix type image display device using the driving circuit of the present invention will be described. These electronic devices include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a still camera, a personal computer, a television, and the like. Examples of these are shown in FIGS.

FIG. 16A shows a mobile phone,
01, audio output unit 9002, audio input unit 9003, display unit 9004, operation switch 9005, antenna 9006
It is composed of The present invention can be applied to the display portion 9004.

FIG. 16B shows a video camera, which includes a main body 9101, a display portion 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 910.
Consists of six. The present invention can be applied to the display portion 9102.

FIG. 16C shows a mobile computer or a portable information terminal which is a kind of personal computer, and includes a main body 9201, a camera section 9202, and an image receiving section 92.
03, an operation switch 9204, and a display unit 9205. The present invention can be applied to the display portion 9205.

FIG. 16D shows a head-mounted display (goggle-type display).
A display portion 9302 and an arm portion 9303 are provided. The present invention can be applied to the display portion 9302.

FIG. 16E shows a television set,
1, speaker 9402, display portion 9403, receiving device 9
404, an amplification device 9405 and the like. The invention can be applied to the display portion 9402.

FIG. 16F shows a portable book, and a main body 95.
01, a display unit 9502, a storage medium 9504, operation switches 9505, and an antenna 9506.
It displays the data stored in the satellite disc) and the data received by the antenna. The invention can be applied to the display portion 9502.

FIG. 17A shows a personal computer, which includes a main body 9601, an image input section 9602, and a display section 96.
03, and a keyboard 9604. The present invention can be applied to the display portion 9603.

FIG. 17B shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 9701, a display portion 9702, and a speaker portion 970.
3, a recording medium 9704, and operation switches 9705. This apparatus uses a DVD, a CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 9702.

FIG. 17C shows a digital camera, which comprises a main body 9801, a display portion 9802, an eyepiece portion 9803, operation switches 9804, and an image receiving portion (not shown).
The present invention can be applied to the display portion 9802.

FIG. 17D shows a one-eye head mounted display, in which a display portion 9901 and a head mount portion 9 are provided.
902. The present invention can be applied to the display portion 9901.

FIG. 18A shows a front type projector, which comprises a projection device 3601 and a screen 3602.

FIG. 18B shows a rear type projector, which includes a main body 3701, a projection device 3702, and a mirror 370.
3. It is composed of a screen 3704.

FIG. 18C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 18A and 18B. Projection devices 3601, 37
02 denotes a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display unit 3808, retardation plate 3809,
It is composed of a projection optical system 3810. Projection optical system 3810
Is composed of an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but the present invention is not limited to this. For example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in an optical path indicated by an arrow in FIG. Good. The present invention can be applied to the liquid crystal display portion 3808.

FIG. 18D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 18C. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, a lens array 3813,
814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system shown in FIG. 18D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields using an image display device.

[0137]

The driving circuit of the image display device according to the present invention can greatly reduce the area of the signal line driving circuit, which is effective for downsizing the image display device, and further reduces the cost and the yield of the image display device. Effective for improvement.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a signal line driving circuit according to an embodiment.

FIG. 2 is a diagram showing operation timings of the signal line driving circuit of FIG.

FIG. 3 is a diagram illustrating a configuration of a signal line driving circuit according to the first embodiment.

FIG. 4 is a diagram showing operation timings of the signal line driving circuit of FIG. 3;

FIG. 5 illustrates a specific example of a storage circuit.

FIG. 6 is a diagram illustrating a configuration of a signal line driving circuit according to a second embodiment.

7 is a diagram showing operation timings of the drive circuit of FIG.

FIG. 8 is a diagram showing a configuration of a bit comparison pulse width conversion circuit (BPC).

FIG. 9 is a diagram illustrating the operation of the ramp type D / A conversion circuit.

FIG. 10 is a diagram illustrating an example of a manufacturing process of an active matrix liquid crystal display device according to a third embodiment.

FIG. 11 is a diagram illustrating an example of a manufacturing process of an active matrix liquid crystal display device according to a third embodiment.

FIG. 12 is a diagram illustrating an example of a manufacturing process of an active matrix liquid crystal display device according to a third embodiment.

FIG. 13 is a diagram illustrating an example of a manufacturing process of the active matrix liquid crystal display device according to the third embodiment.

FIG. 14 is a diagram illustrating an example of a manufacturing process of the active matrix liquid crystal display device according to the third embodiment.

FIG. 15 is a diagram illustrating an example of a manufacturing process of the active matrix liquid crystal display device according to the third embodiment.

FIG. 16 illustrates an example of an electronic device using the present invention.

FIG. 17 is a diagram illustrating an example of an electronic device using the present invention.

FIG. 18 is a diagram showing a configuration of a projection type liquid crystal display device.

FIG. 19 is a configuration diagram of an active matrix liquid crystal display device.

FIG. 20 is a configuration diagram of a conventional digital signal line driving circuit.

FIG. 21 is a timing chart of a conventional digital signal line driving circuit.

[Explanation of symbols]

 10 (ac) Signal line selection circuit 20 Analog switch 101 Signal line drive circuit 102 Scan line drive circuit 103 Pixel matrix 104 Signal line 105 Scan line 106 Pixel TFT 107 Liquid crystal

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G02F 1/1345 G02F 1/1345 G09G 3/36 G09G 3/36 (72) Inventor Yasushi Kubota Osaka-shi, Osaka (22) Inventor Kazu Washio 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka, Japan

Claims (16)

[Claims] 1. A first storage circuit for storing an m-bit (m is a natural number) digital video signal, a second storage circuit for storing an output signal of the first storage circuit, and the second storage In a drive circuit of an active matrix type image display device having a D / A conversion circuit for converting an output signal of the circuit into an analog signal, when the number of effective signal lines in the horizontal direction is k,
A driving circuit for an image display device, wherein the number of each of the first storage circuit and the second storage circuit is m × k for n (n is a natural number of 2 or more). 2. A first storage circuit for storing an m-bit (m is a natural number) digital video signal; a second storage circuit for storing an output signal of the first storage circuit; and a second storage circuit. In a drive circuit of an active matrix type image display device having a D / A conversion circuit for converting an output signal of the circuit into an analog signal, the first storage circuit and the second storage circuit operate for a time equivalent to one horizontal scanning period. A driving circuit for an image display device, wherein a memory operation is performed n times (n is a natural number of 2 or more). 3. A first storage circuit for storing an m-bit (m is a natural number) digital video signal, a second storage circuit for storing an output signal of the first storage circuit, and the second storage circuit In a drive circuit of an active matrix type image display device having a D / A conversion circuit for converting an output signal of the circuit into an analog signal, the second storage circuit is divided into a plurality of groups divided in a horizontal direction, A driving circuit for an image display device, wherein each group performs a storage operation n times (n is a natural number of 2 or more) in one horizontal scanning period at different timings. 4. The driving circuit for an image display device according to claim 1, wherein the first storage circuit is controlled by a shift register. 5. The driving circuit for an image display device according to claim 1, wherein the first storage circuit is controlled by a decoder. 6. A first storage circuit storing an m-bit (m is a natural number) digital video signal, a second storage circuit storing an output signal of the first storage circuit, and the second storage circuit A driving circuit for an active matrix image display device having a D / A conversion circuit for converting an output signal of the circuit into an analog signal, wherein the first storage circuit is controlled by a shift register, and in one horizontal scanning period, The drive circuit for an image display device, wherein the shift register has n (n is a natural number of 2 or more) clock suspension periods, and the second storage circuit performs a storage operation in each suspension period. 7. The driving circuit for an image display device according to claim 4, wherein said shift register scans n times within a time corresponding to one horizontal scanning period. 8. The driving circuit for an image display device according to claim 1, wherein the first storage circuit and the second storage circuit are latch circuits. 9. A driving circuit according to claim 8, wherein said latch circuit comprises an analog switch and a storage capacitor. 10. The driving circuit according to claim 8, wherein said latch circuit is constituted by a clocked inverter. 11. The driving circuit according to claim 8, wherein said latch circuit comprises an analog switch and a plurality of inverters. 12. An image display according to claim 1, wherein the number of said D / A conversion circuits is a number obtained by dividing the number of horizontal signal lines by n. The drive circuit of the device. 13. A driving circuit for an image display device according to claim 1, wherein said D / A conversion circuit is a ramp type D / A conversion circuit. 14. A driving circuit for an image display device according to claim 1, wherein the driving circuit for the image display device is constituted by a polysilicon thin film transistor. 15. The driving circuit for an image display device according to claim 1, wherein the driving circuit for the image display device is constituted by a single crystal transistor. 16. An electronic apparatus using the driving circuit of the image display device according to claim 1. Description: