JPH10319924A - Liquid crystal display panel driving circuit of digital system - Google Patents

Liquid crystal display panel driving circuit of digital system

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Publication number
JPH10319924A
JPH10319924A JP12838698A JP12838698A JPH10319924A JP H10319924 A JPH10319924 A JP H10319924A JP 12838698 A JP12838698 A JP 12838698A JP 12838698 A JP12838698 A JP 12838698A JP H10319924 A JPH10319924 A JP H10319924A
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JP
Japan
Prior art keywords
array
display panel
liquid crystal
crystal display
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12838698A
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Japanese (ja)
Inventor
Gil Bum Ahan
バム,アハン ギル
Original Assignee
Lg Electron Inc
エルジー電子株式会社
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Publication date
Priority to KR1997-19142 priority Critical
Priority to KR1019970019142A priority patent/KR100229380B1/en
Application filed by Lg Electron Inc, エルジー電子株式会社 filed Critical Lg Electron Inc
Publication of JPH10319924A publication Critical patent/JPH10319924A/en
Application status is Pending legal-status Critical

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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes
    • G09G3/3688Details of drivers for data electrodes suitable for active matrices only
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/027Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0297Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0271Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes

Abstract

PROBLEM TO BE SOLVED: To reduce instantaneous power consumption by providing a multiplexer between an output amplifier array and data line of a liquid crystal display panel or the like thereby simplifying the circuit configuration.
SOLUTION: This driving circuit 40 is provided with a first latch array 42, the second latch array cascaded to the first latch array 42, a multiplexer 46 and a D-A converter array 48. The first and the second latch arraies are respectively constituted of 2400 pieces of latches or the like. The multiplexer 46 separates 800 pieces of pixel data from the second latch array 44 at a time to transfer them to the D-A converter array 48 side while dividing them in three times. Consequently, the number of converters of the D-A converter array 48 and amplifiers of the output amplifier array 52 is reduced to the half, the one third the number of data lines DL1-DL2400 or a number less than these numbers. Thus, instantaneous power consumption of circuits is reduced.
COPYRIGHT: (C)1998,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、液晶表示パネルを利用する表示装置に関するもので、特に液晶表示パネルをデジタル映像信号により駆動するデジタル方式の液晶表示パネル駆動回路に関する。 The present invention relates to relates to a display device using the liquid crystal display panel, and more particularly to a liquid crystal display panel driving circuit of digital driving the liquid crystal display panel by the digital video signal.

【0002】 [0002]

【従来の技術】最近、映像媒体で視聴者に高解像度の画像を提供するための方法として、既存のアナログ映像信号の代わりに、情報の圧縮が容易なデジタル映像信号で転送する方式に転換されつつある趨勢である。 Recently, as a method for providing high-resolution images of the viewer in the video medium is converted to method of forwarding in place of existing analog video signal, the compression information in an easy digital video signal while it is a trend. それにより、映像表示装置の一つの種類の液晶表示パネルも、既存のアナログ映像信号の代わりにデジタル映像信号により駆動されなければならないようになった。 Thereby, one type of liquid crystal display panel of the image display device is also now must be driven by a digital video signal instead of existing analog video signal. そのために、液晶表示パネル用の駆動回路は、アナログ信号を要求する液晶表示パネルの画素等を駆動することに適合するように新たに構成されている。 Therefore, the drive circuit for a liquid crystal display panel is newly configured to fit to drive a pixel of a liquid crystal display panel that requires an analog signal. その結果、液晶表示パネル駆動回路には、既存のアナログ方式の液晶表示パネル駆動回路とデジタル方式の液晶表示パネル駆動回路とが併存している。 As a result, the liquid crystal display panel driving circuit, a liquid crystal display panel driving circuit of the liquid crystal display panel driving circuit and a digital method of the existing analog system has coexist.

【0003】このような液晶表示パネル駆動回路は、液晶表示パネル上の画素等のそれぞれに、映像信号に該当する電圧を正確に印加することができる十分な信号供給時間を確保しなければならない。 Such a liquid crystal display panel driving circuit, in each of such pixels on the liquid crystal display panel, it is necessary to secure a sufficient signal supply time a voltage corresponding to the video signal can be accurately applied. それを解決するために、アナログ方式の液晶表示パネル駆動回路としては、 To solve it, the liquid crystal display panel driving circuit of the analog scheme,
1水平走査ライン上の画素等を2個以上の一定個数づつ順次的に駆動する方案が、日本国公開特許公報第199 1 scheme for driving the pixels or the like on the horizontal scanning line of two or more predetermined number at a time sequential manner is, Japanese patent publication No. 199
5(平成7年)−181933号に開示された。 Disclosed in 5 (1995) No. -181933. この日本国公開特許公報第1995−181933号によると、アナログ方式の液晶表示パネル駆動回路は、遅延素子を利用して映像信号を遅延させ、遅延された映像信号は、水平ライン上の中間部分から右側先端に至る画素等に、そして遅延されない映像信号は、左側先端から中央部分に至る画素等に順次的に印加した。 According to this Japanese patent publication No. 1995-181933, a liquid crystal display panel driving circuit of the analog scheme delays the video signal by using a delay element, delayed video signal from the intermediate portion on the horizontal line the pixel or the like reaches the right tip, and a video signal which is not delayed, was sequentially applied to the pixel or the like extending from the left side distal to the central portion. このようなアナログ方式の液晶表示パネル駆動回路は、アナログ映像信号を画素の駆動電圧としてそのまま利用しているので、 The liquid crystal display panel driving circuit of such an analog system, since the use as an analog video signal as the driving voltage of the pixel,
水平ライン上の画素等を2個づつ順次的に駆動しても、 Be driven pixels or the like on the horizontal line 2 at a time sequential manner,
画素別に十分な信号供給時間を確保することができた。 It was possible to secure a sufficient signal supply time by pixel.

【0004】それとは異なって、デジタル方式の液晶表示パネル駆動回路は、デジタル映像信号をアナログ映像信号に変換する信号変換時間を必要とするので、前記の日本国公開特許公報第1995−181933号のようなアナログ方式の液晶表示パネル駆動方法によっては、 [0004] different from that, the liquid crystal display panel driving circuit of a digital system, since the digital video signal requiring signal conversion time for converting the analog video signal, of said Japanese Patent Publication No. 1995-181933 some liquid crystal display panel driving method of the analog system as,
画素別の信号供給時間を十分に確保することができなかった。 Pixel-signal supply time can not be sufficiently secured. それにより、デジタル方式の液晶表示パネル駆動回路は、1水平ライン上の画素等を同時に駆動するように、図1に示されるように構成された。 Thereby, the liquid crystal display panel driving circuit of a digital system, so as to simultaneously drive the pixels or the like on one horizontal line, which is configured as shown in FIG.

【0005】図1を参照すると、液晶表示パネル(1 [0005] Referring to FIG. 1, the liquid crystal display panel (1
0)は、それぞれ垂直方向に配列された600個の画素等に接続された2400個のデータライン(DL1乃至DL2400)を備える。 0) includes 2400 data lines connected to the 600 pixels or the like which is arranged in the vertical direction, respectively (DL1 to DL2400). そして、液晶表示パネル(1 Then, a liquid crystal display panel (1
0)上の600×2400個の画素等を駆動するための駆動回路(20)は、第1乃至第3データバス(Data Bu Drive circuit for driving a 600 × 2400 pixels or the like on 0) (20), the first to third data bus (Data Bu
s;DB1乃至DB3)に接続された第1ラッチアレー(22)と、この第1ラッチアレー(22)に縦属接続された第2ラッチアレー(24)、デジタル−アナログ変換器アレー(26)及び出力増幅器アレー(28)から構成される。 s; a first latch array connected to DB1 to DB3) (22), a second latch array is cascaded to the first latch array (22) (24), a digital - analog converter array (26) and the output amplifier It consists of an array (28). 第1及び第2ラッチアレー(22,2 First and second latch array (22, 24, 32
4)は、それぞれ2400個のラッチ等から構成される。 4) is composed of each 2400 such as a latch. 第1ラッチアレー(22)に含まれた2400個のラッチ等は、800個つづ区分され、第1乃至第3データバス(DB1乃至DB3)に分散接続される。 2400 such as a latch included in the first latch array (22) is 800 tsuzuic division, it is dispersed connected to the first to third data buses (DB1 to DB3). 併せて、第1ラッチアレー(22)に含まれた2400個のラッチ等は、3個づつ順次的に駆動され、第1乃至第3 In addition, 2400 such as a latch included in the first latch array (22), three at a time sequential manner is driven, the first to third
データバス(DB1乃至DB3)から1水平ライン分の赤色(以下“R”という)、緑色(以下“G”という) Data bus (DB1 to DB3) from the one horizontal line red (hereinafter referred to as "R"), (hereinafter referred to as "G") Green
及び青色(以下“B”という)画素データを入力する。 And (hereinafter referred to as "B") blue inputs the pixel data.
そして、第2ラッチアレー(24)に含まれた2400 And, it included in the second latch array (24) 2400
個のラッチ等は、それぞれ第1ラッチアレー(22)の2400個のラッチ等からの画素データを同時に入力して、D−A変換器アレー(26)側に転送する。 Number of latches or the like, each input pixel data from the 2400 such as a latch in the first latch array (22) at the same time, transferred to the D-A converter array (26) side. そうすると、D−A変換器アレー(26)は、第2ラッチアレー(24)からの2400個の画素データの全てを画素信号に変換し、その変換された2400個の画素信号を出力増幅器アレー(28)に供給する。 Then, D-A converter array (26), all the 2400 pieces of pixel data from the second latch array (24) into pixel signals, the converted 2400 pixel signals output amplifier array was (28 ) to supply.

【0006】そのために、D−A変換器アレー(26) [0006] Therefore, D-A converter array (26)
は、図示されていないガンマ補正部からの一定個数(例えば5個)の変換ソース信号等を共通的に入力する24 Inputs the converted source signal or the like predetermined number from the gamma correction unit, not shown (for example, five) commonly 24
00個のD−A変換器等から構成される。 00 amino composed D-A converter. この2400 This 2400
個のD−A変換器等は、それぞれ第2ラッチアレー(2 Number of D-A converter, etc., each second latch array (2
4)の該当ラッチからの画素データの論理値に従って、 According to the logic value of the pixel data from the corresponding latch 4),
変換ソース信号等の一部または全部を加算することによって画素信号を発生するようになる。 So generating a pixel signal by adding some or all of such conversion source signal. 最後に、出力増幅器アレー(28)は、D−A変換器アレー(26)からの2400個の画素信号等を一定の増幅率で増幅し、その増幅された2400個の画素信号等を液晶表示パネル(10)の2400個のデータライン(DL1乃至DL Finally, the output amplifier array (28) amplifies the 2400 pixels signals from D-A converter array (26) at a fixed amplification factor, the liquid crystal display 2400 of the pixel signal or the like which is amplified panel 2400 of the data line (DL1 to DL (10)
2400)に分散供給する。 Distributed supplies to 2400). そのために、出力増幅器アレー(28)も、D−A変換器アレー(26)の240 Therefore, 240 of the output amplifier array (28) also, D-A converter array (26)
0個のD−A変換器等に分散接続された2400個の出力増幅器等を備える。 0 of dispersed connected to D-A converter or the like comprising a 2400 output amplifier or the like.

【0007】以上のごとく、従来のデジタル方式の液晶表示パネル駆動回路は、液晶表示パネル上の1水平ライン分の画素等を同時に駆動し、画素別の信号供給時間を十分に確保することができた。 [0007] As described above, the liquid crystal display panel driving circuit of a conventional digital drives one pixel of horizontal line or the like on the liquid crystal display panel at the same time, it is possible to sufficiently ensure a different signal supply time pixel It was. しかし、従来のデジタル方式の液晶表示パネル駆動回路では、液晶表示パネルの水平ラインに含まれた画素数に該当するD−A変換器等と出力増幅器等が使用されなければならないので、その回路構成が複雑となることは言うまでもなく、その嵩も大きくなる。 However, in the liquid crystal display panel driving circuit of a conventional digital system, since D-A converter and the like and an output amplifier or the like corresponding to the number of pixels included in the horizontal lines of the liquid crystal display panel must be used, the circuit configuration it goes without saying that becomes complicated, the bulk is also increased. 併せて、従来のデジタル方式の液晶表示パネル駆動回路では、多数のD−A変換器等と出力増幅器等とが同時に駆動されなければならなかったので、瞬間の電力消費が非常に大きくなる。 In addition, in the liquid crystal display panel driving circuit of a conventional digital system, since the number of D-A converter and the like and an output amplifier or the like had to be driven at the same time, the instantaneous power consumption is very large.

【0008】 [0008]

【発明が解決しようとする課題】従って、本発明の目的は、回路構成を簡素化することができ、瞬間の電力消費を減少させることができるデジタル方式の液晶表示パネル駆動回路を提供することにある。 OBJECTS OF THE INVENTION It is therefore an object of the present invention is to provide a liquid crystal display panel driving circuit of a digital system can be able to simplify the circuit configuration, reduce the instantaneous power consumption is there.

【0009】本発明の他の目的は、液晶表示パネルの引出ラインの数を減少させることができる、デジタル方式の液晶表示パネル駆動回路を提供することにある。 Another object of the present invention can reduce the number of the lead lines of the liquid crystal display panel to provide a liquid crystal display panel driving circuit of a digital system.

【0010】 [0010]

【課題を解決するための手段】前記の目的を達成するために、本発明によるデジタル方式の液晶表示パネル駆動回路は、n個のデジタル画素データからk個のデジタル画素データを選択するためのマルチプレクサアレーと、 To SUMMARY OF THE INVENTION To achieve the above object, a liquid crystal display panel driving circuit of a digital system according to the present invention, a multiplexer for selecting the k pieces of digital pixel data from the n digital pixel data and the array,
前記マルチプレクサアレーからのk個のデジタル画素データをk個のアナログ画素信号に変換するためのデジタル−アナログ変換器アレーと、n個のデータラインに接続され、前記n個のデータラインの中からk個を選択すると同時に、前記のデジタル−アナログ変換器アレーからのk個のアナログ画素信号を、前記選択されたk個のデータラインに転送するためのディマルチプレクサアレーとを備える。 Digital to convert the k number of digital pixel data from said multiplexer array into k analog pixel signals - analog converter array, is connected to n data lines, k from among the n data lines simultaneously selecting pieces, the digital - and a k number of analog pixel signals from the analog transducer array, demultiplexers array for transfer to k data lines said selected.

【0011】本発明によるデジタル方式の液晶表示パネルの駆動方法は、n個のデジタル画素データからk個のデジタル画素データを選択する段階と、マルチプレクサアレーからの前記k個のデジタル画素データをk個のアナログ画素信号に変換する段階と、n個のデータラインの中からk個を選択する段階と、デジタル−アナログ変換器からの前記k個のアナログ画素信号を、前記選択されたk個のデータラインに転送する段階とを含む。 [0011] The driving method of the liquid crystal display panel of a digital system according to the present invention includes the steps of the n digital pixel data to select k pieces of digital pixel data, the k the k pieces of digital pixel data from the multiplexer array and converting the analog pixel signal, and selecting the k pieces out of n data lines, digital - the k pieces of analog pixel signals from the analog converter, the selected k data and a step of transferring to the line.

【0012】本発明によるデジタル方式の液晶表示パネル駆動回路では、マルチプレクサアレーが液晶表示パネルに搭載されるようにして、液晶表示パネルの引出ライン数を最少化する。 [0012] In the liquid crystal display panel driving circuit of a digital system according to the present invention, the multiplexer array is to be mounted on a liquid crystal display panel, minimize the number of lead lines of the liquid crystal display panel. 本発明によるデジタル方式の液晶表示パネル駆動回路は、1ライン分の画素データを一時的に保管するラッチアレーと、画素データを画素信号に変換するD−A変換器アレーとの間にディマルチプレクサアレーを、そして出力増幅器アレーと液晶表示パネルのデータライン等との間にマルチプレクサを設置することによって、D−A変換器と出力増幅器の個数をデータライン数の半分、3分の1またはその以下に減少させることができる。 The liquid crystal display panel driving circuit of a digital system according to the present invention, a temporarily storing latch array of pixel data for one line, a demultiplexer array between the D-A converter array for converting the pixel data into the pixel signal and reduced by placing a multiplexer between the data line and the output amplifier array and the liquid crystal display panel, the number of the output amplifier D-a converter half the number of data lines, 1 or in the following three minutes it can be. これによって、本発明によるデジタル方式の液晶表示パネル駆動回路は、回路構成の簡素化を達成することは勿論、瞬間の電力消費量を減少させることもできる。 Thus, the liquid crystal display panel driving circuit of a digital system according to the present invention is to achieve a simplified circuit configuration, of course, also possible to reduce the instantaneous power consumption. 併せて、本発明によるデジタル方式の液晶表示パネル駆動回路は、マルチプレクサを液晶表示パネルに搭載させ、液晶表示パネルの引出ラインの数量を減少させることができる。 In addition, the liquid crystal display panel driving circuit of a digital system according to the present invention, the multiplexer is mounted on a liquid crystal display panel, it is possible to reduce the number of lead lines of the liquid crystal display panel.

【0013】 [0013]

【発明の実施の形態】前記の目的以外に本発明の他の目的及び利点等は、添付図面を参照した下記の好ましい実施の形態に対する詳細な説明を通して明らかになる。 The objects and advantages, such as another of the present invention except to provide [MODE CARRYING OUT THE INVENTION Said become apparent through the detailed description of the preferred embodiments described below with reference to the accompanying drawings.

【0014】図2を参照すると、本発明の実施の形態によるデジタル方式の液晶表示パネル駆動回路を含む液晶表示装置が図示されている。 Referring to FIG. 2, a liquid crystal display device including a liquid crystal display panel driving circuit of a digital scheme according to the present invention is shown. 図2において、液晶表示装置は、液晶表示パネル(30)に接続された液晶表示パネル駆動回路(40)を備える。 2, the liquid crystal display device includes a liquid crystal display panel driving circuit connected to the liquid crystal display panel (30) (40). 液晶表示パネル(3 The liquid crystal display panel (3
0)は、それぞれ垂直方向に配列された600個の画素等に共通的に接続された2400個のデータライン(D 0), 2400 data lines (D that is commonly connected to the 600 pixels or the like which is arranged in the vertical direction, respectively
L1乃至DL2400)を備える。 It comprises L1 to DL2400).

【0015】一方、液晶表示パネル(30)上の600 [0015] On the other hand, 600 on the liquid crystal display panel (30)
×2400個の画素等を駆動するための駆動回路(4 × driving circuit for driving a 2400 pixels such as (4
0)は、第1乃至第3データバス(DB1乃至DB3) 0), the first to third data buses (DB1 to DB3)
に接続された第1ラッチアレー(42)と、この第1ラッチアレー(42)に縦属接続された第2ラッチアレー(44)、マルチプレクサアレー(46)及びD−A変換器アレー(48)とを備える。 Comprising the connected first latch array (42), a second latch array is cascaded to the first latch array (42) (44), a multiplexer array (46) and D-A converter array (48) to . 第1及び第2ラッチアレー(42,44)は、それぞれ2400個のラッチ等から構成される。 First and second latch array (42, 44) is composed of each 2400 such as a latch. 第1ラッチアレー(42)に含まれた2400個のラッチ等は800個づつ区分され、第1乃至第3データバス(DB1乃至DB3)に分散接続される。 2400 such as a latch included in the first latch array (42) is divided 800 by one, they are dispersed connected to the first to third data buses (DB1 to DB3). 併せて、第1ラッチアレー(42)に含まれた24 In addition, it included in the first latch array (42) 24
00個のラッチ等は3個づつ順次的に駆動され、第1乃至第3データバス(DB1乃至DB3)から1水平ライン分のR、G及びB画素データを入力する。 00 latches the like driven three increments sequential manner, first to third data bus (DB1 to DB3) for one horizontal line R, inputs the G and B pixel data. そして、第2ラッチアレー(44)に含まれた2400個のラッチ等は、それぞれ第1ラッチアレー(42)の2400個のラッチ等からの画素データを同時に入力してマルチプレクサアレー(46)側に転送する。 Then, 2400 such as a latch included in the second latch array (44) is transferred to the 2400 multiplexer array (46) side by simultaneously input pixel data from the latch or the like of each of the first latch array (42) .

【0016】マルチプレクサアレー(46)は、第2ラッチアレー(44)からの2400個の画素データを8 [0016] Multiplexer array (46), a 2400 pixel data from the second latch array (44) 8
00個づつ区分して、3回にかけてD−A変換器アレー(48)側に転送する。 00 pieces at a time by dividing, transferred to D-A converter array (48) side to the 3 times. そのために、マルチプレクサアレー(46)は、それぞれ第1乃至第3制御ライン(S Therefore, the multiplexer array (46), each of the first to third control lines (S
L1乃至SL3)からの第1乃至第3切換制御信号(S The first to third switching control signals from L1 to SL3) (S
WS1乃至SWS3)を入力する800個のマルチプレクサ等(MP1乃至MP800)から構成される。 Composed of 800 pieces of multiplexers for inputting the WS1 to SWS3) (MP1 to MP800). この800個のマルチプレクサのそれぞれは、図3でのように1水平周期の間順次的に“1”の論理値を有するようになる前記の第1乃至第3切換制御信号(SWS1乃至SWS3)により、第2ラッチアレー(44)の3個のラッチ等からの3個の画素データを順次的にD−A変換器アレー(48)側に転送する。 Each of the 800 of the multiplexer, the first to third switching control signals (SWS1 to SWS3) which will have a logic value of 1 during the horizontal period-sequentially "1" as in FIG. 3 , sequentially transferred to the D-a converter array (48) side three pixel data from three latch or the like of the second latch array (44). そのために、800個のマルチプレクサ等(MP1乃至MP800)のそれぞれは、第1乃至第3切換制御信号(SWS1乃至SWS Therefore, 800 pieces of each of the multiplexers such as (MP1 to MP800), first to third switching control signals (SWS1 to SWS
3)をゲート側にそれぞれ受ける3組のMOSトランジスタ(MF)から構成される。 Receiving respectively 3) to the gate side composed of three pairs of MOS transistors (MF). ここにおいて、3組のM In this case, three sets of M
OSトランジスタ(MF)は、画素データが5ビットの場合15個でなければならないが、便宜上3個に表現されている。 OS transistor (MF) must be a 15 if the pixel data are 5 bits, are conveniently represented in three. 1つのマルチプレクサ(MP)に含まれた3 Contained in one multiplexer (MP) 3
組のMOSトランジスタ(MF)のソース等は、第2ラッチアレー(44)に含まれた3個のラッチにそれぞれ接続され、そしてこの3組のMOSトランジスタ(M Source such as a set of MOS transistors (MF) are connected respectively to the three latch included in the second latch array (44), and the three sets of MOS transistors (M
F)のドレーン等は、画素データのビット別に共通的に接続される。 Drain etc. F) are commonly connected by bit pixel data. 併せて、1つのマルチプレクサ(MP)に含まれた3組のMOSトランジスタ(MF)は、第1乃至第3切換制御信号(SWS1乃至SWS3)により1 In addition, 1 by one multiplexer (MP) in the included three groups of MOS transistors (MF), the first to third switching control signals (SWS1 to SWS3)
水平期間の間互いに順次的にターンオンされ、第2ラッチアレー(44)の該当ラッチからの画素データをD− Are sequentially turned on one another during the horizontal period, the pixel data from the corresponding latch of the second latch array (44) D-
A変換器アレー(46)側に転送する。 Transferred to the A transducer array (46) side. そうすると、D Then, D
−A変換器アレー(48)は、マルチプレクサアレー(46)からの800個の画素データの全てを画素信号に変換する。 -A transducer array (48) converts all 800 pieces of pixel data from the multiplexer array (46) to the pixel signal. そのために、D−A変換器アレー(48) Therefore, D-A converter array (48)
は、ガンマ補正部(50)からの少なくとも一定個数(例えば5個)の変換ソース信号を共通的に受ける80 Receives the converted source signal at least predetermined number from the gamma correction unit (50) (for example, five) in common 80
0個のD−A変換器から構成される。 And zero amino D-A converter. この800個のD The 800 pieces of D
−A変換器等のそれぞれは、該当マルチプレクサ(M Each such -A converter, corresponding multiplexer (M
P)からの画素データの論理値に対し、ガンマ補正部(50)からの一定個数の変換ソース信号の全てまたは一部を選択的に加算することによって、画素データをアナログ画素信号に変換する。 To the logical value of the pixel data from P), by selectively adding all or part of the conversion source signal of a predetermined number from the gamma correction unit (50), converts the pixel data into analog pixel signals. 結果的に、800個のD− As a result, 800 of the D-
A変換器等のそれぞれは、1水平走査期間に3個の画素データをアナログ画素信号に変換するようになる。 Each of such A converter, comprising three pixel data in one horizontal scanning period so as to convert an analog pixel signal.

【0017】また、駆動回路(40)はD−A変換器アレー(48)と液晶表示パネル(30)のデータライン等(DL1乃至DL2400)の間に直列接続された出力増幅器アレー(52)とディマルチプレクサアレー(54)とを備える。 Further, the drive circuit (40) is a D-A converter array (48) connected in series to an output amplifier array (52) between the data lines of the liquid crystal display panel (30) (DL1 to DL2400) and a de-multiplexer array (54). 出力増幅器アレー(52)は、D Output amplifier array (52), D
−A変換器アレー(48)からの800個の画素信号等を一定の増幅率で増幅し、その増幅された800個の画素信号等をディマルチプレクサアレー(54)側に出力する。 800 pixels signals from -A transducer array (48) was amplified with a constant amplification factor, and outputs a 800 pixel signals or the like which is amplified in the demultiplexer array (54) side. そのために、出力増幅器アレー(52)もD−A Therefore, the output amplifier array (52) is also D-A
変換器アレー(48)の800個のD−A変換器等に分散接続された800個の出力増幅器等から構成される。 Composed of transducer array (48) 800 of the output amplifier or the like dispersed connected to 800 of the D-A converter or the like.
最後に、ディマルチプレクサアレー(54)は、出力増幅器アレー(52)からの800個の増幅された画素信号を、2400個のデータライン(DL1乃至DL24 Finally, de-multiplexer array (54), the 800 amplified pixel signal from the output amplifier array (52), 2400 data lines (DL1 to the DL24
00)に、800個のデータラインづつ3回にかけて順次的に転送する。 To 00), sequentially to transfer over the 800 pieces of the data line at a time three times. そのために、ディマルチプレクサアレー(54)は、それぞれ第1乃至第3制御ライン(SL Therefore, de-multiplexer array (54), each of the first to third control line (SL
1乃至SL3)からの第1乃至第3切換制御信号(SW The first to third switching control signals from 1 to SL3) (SW
S1乃至SWS3)を受ける800個のディマルチプレクサ等(DMP1乃至DMP800)から構成される。 Composed of 800 amino demultiplexor such as undergoing S1 to SWS3) (DMP1 to DMP800).
この800個のディマルチプレクサ(DMP1乃至DM The 800 pieces of the demultiplexer (DMP1 or DM
P800)のそれぞれは、図3のように1水平周期の間順次的に“1”の論理値を有するようになる前記の第1 Each P800), the said made to have a logical value of 1 during the horizontal period-sequentially "1" as shown in FIG. 3 1
乃至第3切換制御信号(SWS1乃至SWS3)により、出力増幅器アレー(52)からの画素信号を3個のデータライン(DL)に順次的に転送する。 To the third switching control signal (SWS1 to SWS3), sequentially transfers the pixel signal from the output amplifier array (52) to the three data lines (DL). そのために、800個のディマルチプレクサ等(DMP1乃至D To that end, such as 800 of the demultiplexer (DMP1 or D
MP800)のそれぞれは、第1乃至第3切換制御信号(SWS1乃至SWS3)をゲート側にそれぞれ受ける3個のMOSトランジスタ(MS)から構成される。 MP800) each is composed of three MOS transistors receiving respective first to third switching control signals (SWS1 to SWS3) to the gate side (MS). 1
つのディマルチプレクサ(DMP)に含まれた3個のM One of the included in the demultiplexer (DMP) 3 pieces of M
OSトランジスタ(MS)のソース等は、出力増幅器アレー(52)に含まれた1つの出力増幅器の出力端子に共通的に接続され、このドレーン等は3個のデータライン(DL)に分散接続される。 Source such as an OS transistor (MS) is commonly connected to the output terminal of one output amplifier included in the output amplifier array (52), the drain or the like is dispersed connected to three data lines (DL) that. 併せて、1つのディマルチプレクサ(DMP)に含まれた3個のMOSトランジスタ(MS)は、第1乃至第3切換制御信号(SWS1 In addition, one included in the demultiplexer (DMP) 3 pieces of MOS transistors (MS), the first to third switching control signals (SWS1
乃至SWS3)により1水平期間の間互いに順次的にターンオンされ、出力増幅器アレー(52)に含まれた該当出力増幅器からの画素信号等を3個のデータライン(DL)に分散供給する。 To SWS3) by being sequentially turned on each other for one horizontal period, dispersing supplies a pixel signal or the like to the three data lines (DL) from the included corresponding output amplifier to the output amplifier array (52).

【0018】 [0018]

【発明の効果】上述のごとく、本発明によるデジタル方式の液晶表示パネル駆動回路は、1ライン分の画素データを一時的に保管するラッチアレーと、画素データを画素信号に変換するD−A変換器アレーとの間にマルチプレクサアレーを、そして出力増幅器アレーと液晶表示パネルのデータライン等との間にディマルチプレクサを設置することによって、D−A変換器と出力増幅器の個数をデータライン数の半分、3分の1またはそれ以下に減少させることができる。 As described above, according to the present invention, a liquid crystal display panel driving circuit of a digital system according to the present invention, a temporarily storing latch array of pixel data for one line, D-A converter for converting the pixel data into the pixel signal half by placing the demultiplexer, the number of the output amplifier D-a converter of the number of data lines between the multiplexer array, and the data lines and the output amplifier array and the liquid crystal display panel between the array, it can be reduced to 1 or less 3 minutes. それによって、本発明によるデジタル方式の液晶表示パネル駆動回路は、回路構成の簡素化を達成することは勿論、瞬間の電力消費量を減少させることもできる。 Thereby, the liquid crystal display panel driving circuit of a digital system according to the present invention is to achieve a simplified circuit configuration, of course, also possible to reduce the instantaneous power consumption. 併せて、本発明によるデジタル方式の液晶表示パネル駆動回路はマルチプレクサを液晶表示パネルに搭載させ、液晶表示パネルの引出ラインの数量を減少させることができる。 In addition, the liquid crystal display panel driving circuit of a digital system according to the present invention is equipped with a multiplexer on the liquid crystal display panel, it is possible to reduce the number of lead lines of the liquid crystal display panel.

【0019】以上において説明した内容を通して、当業者であれば本発明の技術思想から逸脱しない範囲内で多様な変更及び修正が可能であることが分かる。 [0019] Through the contents described in the above, it is understood that that various modifications and variations can be within a range not departing from the spirit of the present invention by those skilled in the art. 従って、 Therefore,
本発明の技術的範囲は、明細書の詳細な説明に記載された内容に限定されるものでなく、特許請求の範囲により定めなければならない。 The technical scope of the present invention is not limited to the contents described in the detailed description of the specification shall be defined by the claims.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】従来のデジタル映像信号用の液晶表示パネル駆動回路が適用された液晶表示装置を図示する図面である。 1 is a view liquid crystal display panel driving circuit for a conventional digital video signal is shown a liquid crystal display device is applied.

【図2】本発明の実施の形態によるデジタル方式の液晶表示パネル駆動回路が適用された液晶表示装置を図示する図面である。 Is a view illustrating a liquid crystal display device having a liquid crystal display panel driving circuit is applied a digital type according to the embodiment of the present invention; FIG.

【図3】図2に示された駆動回路の各部分の動作タイミング図である。 3 is an operation timing diagram of portions of the illustrated drive circuit in FIG.

【符号の説明】 DESCRIPTION OF SYMBOLS

10,30:液晶表示パネル 20,40:液晶表示パネル駆動回路 22,42:第1ラッチアレー 24,44:第2ラッチアレー 26,48:D−A変換器アレー 28,52:出力増幅器アレー 46:マルチプレクサアレー 50:ガンマ補正部 54:ディマルチプレクサアレー 10, 30: liquid crystal display panel 20 and 40: liquid crystal display panel driving circuit 22, 42: first latch array 24, 44: second latch array 26, 48: D-A converter array 28,52: Output amplifier array 46: Multiplexer array 50: gamma correction unit 54: de-multiplexer array

Claims (11)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 n個のデジタル画素データからk個のデジタル画素データを選択するためのマルチプレクサアレーと、前記マルチプレクサアレーからのk個のデジタル画素データを、k個のアナログ画素信号に変換するためのデジタル−アナログ変換器アレーと、n個のデータラインに接続され、前記n個のデータラインの中からk個を選択するとともに、前記デジタル−アナログ変換器アレーからのk個のアナログ画素信号を、前記選択されたk個のデータラインに転送するためのディマルチプレクサアレーとを備えるデジタル方式の液晶表示パネル駆動回路。 1. A multiplexer array for selecting k pieces of digital pixel data from the n digital pixel data, the k pieces of digital pixel data from said multiplexer array, for converting the k analog pixel signal digital - analog converter array, is connected to n data lines, as well as select k pieces from among the n data lines, wherein the digital - the k pieces of analog pixel signals from the analog transducer array the liquid crystal display panel driving circuit of a digital system and a de-multiplexer array for transfer to k data lines said selected.
  2. 【請求項2】 水平方向に並んで配列され、垂直方向に配列されたm個の画素に共通に接続されたn個のデータラインを備えることを特徴とする請求項1記載のデジタル方式の液晶表示パネル駆動回路。 2. A are arranged side by side in the horizontal direction, of the digital system according to claim 1, characterized in that it comprises n data lines connected in common to the m pixels arranged in the vertical direction LCD display panel drive circuit.
  3. 【請求項3】 前記ディマルチプレクサアレーは、液晶表示パネルに搭載されたことを特徴とする請求項2記載のデジタル方式の液晶表示パネル駆動回路。 Wherein the de-multiplexer array, a liquid crystal display panel driving circuit of a digital system according to claim 2, characterized in that mounted on the liquid crystal display panel.
  4. 【請求項4】 入力されたn個のデジタル画素データを一時的に貯蔵するとともに、前記n個のデジタル画素データを、前記のマルチプレクサアレーに入力するための記憶手段を備えることを特徴とする請求項1記載のデジタル方式の液晶表示パネル駆動回路。 Wherein while temporarily storing the inputted n digital pixel data, according to the n digital pixel data, characterized in that it comprises memory means for input to the multiplexer array the liquid crystal display panel driving circuit of a digital system in claim 1.
  5. 【請求項5】 前記のデジタル−アナログ変換器アレーと、前記のディマルチプレクサアレーとの間に備えられた出力増幅器アレーを備えることを特徴とする請求項1 Wherein said digital - claim to analog converter array, comprising: a power amplifier array provided between said demultiplexor array 1
    記載のデジタル方式の液晶表示パネル駆動回路。 The liquid crystal display panel driving circuit of the digital method described.
  6. 【請求項6】 前記のマルチプレクサアレーと前記のディマルチプレクサアレーがMOSトランジスタから構成されることを特徴とする請求項1記載のデジタル方式の液晶表示パネル駆動回路。 6. A liquid crystal display panel driving circuit of a digital system according to claim 1, characterized in that said multiplexer array and said demultiplexor array is composed of MOS transistors.
  7. 【請求項7】 前記ディマルチプレクサの選択時間がk 7. The selection time of the de-multiplexer k
    /nに該当することを特徴とする請求項1記載のデジタル方式の液晶表示パネル駆動回路。 The liquid crystal display panel driving circuit of a digital system according to claim 1, characterized in that corresponding to / n.
  8. 【請求項8】 n個のデジタル画素データからk個のデジタル画素データを選択する段階と、選択された前記k From 8. n digital pixel data and selecting the k pieces of digital pixel data, the k selected
    個のデジタル画素データをk個のアナログ画素信号に変換する段階と、n個のデータラインの中からk個を選択する段階と、変換された前記k個のアナログ画素信号を、前記選択されたk個のデータラインに転送する段階とを含むデジタル方式の液晶表示パネル駆動方法。 And converting pieces of the digital pixel data into k analog pixel signal, and selecting the k pieces out of n data lines, the converted the k pieces of analog pixel signals and said selected the liquid crystal display panel driving method for a digital system comprising the steps of transferring the k data lines.
  9. 【請求項9】 n個のデジタル画素データを一時的に貯蔵する段階とを備え、前記貯蔵されたデータを前記n個のデジタル画素データとすることを特徴とする請求項8 9. claims of n and a step for temporarily storing the digital pixel data, characterized in that the stored data to said n digital pixels data 8
    記載のデジタル方式の液晶表示パネル駆動方法。 The liquid crystal display panel driving method for a digital method described.
  10. 【請求項10】 変換された前記k個のアナログ画素信号を増幅する段階を含むことを特徴とする請求項8記載のデジタル方式の液晶表示パネル駆動方法。 10. A transformed the k-number of the liquid crystal display panel driving method for a digital system according to claim 8, characterized in that it comprises a step of amplifying the analog pixel signal.
  11. 【請求項11】 前記n個のデータラインの中からk個を選択する段階が、k/nに該当する時間の間、n個のデータラインの中からk個を選択することを特徴とする請求項8記載のデジタル方式の液晶表示パネル駆動方法。 11. step of selecting the k pieces among the n data lines, during the time corresponding to k / n, and selects k pieces out of n data lines the liquid crystal display panel driving method for a digital system according to claim 8.
JP12838698A 1997-05-17 1998-05-12 Liquid crystal display panel driving circuit of digital system Pending JPH10319924A (en)

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DE19821914A1 (en) 1998-11-19
GB9810599D0 (en) 1998-07-15

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