CN104079265A - High-speed clock duty ratio detection system - Google Patents
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Abstract
The invention discloses a high-speed clock duty ratio detection system. The high-speed clock duty ratio detection system comprises a first detection loop and a second detection loop. The first detection loop comprises a first sampler, a first multiphase clock generator and a digital logic circuit. The first multiphase clock generator generates n-phase clock pulses according to a high-speed clock to be detected, the first sampler samples the high-speed clock to be detected according to the n-phase clock pulses, and the digital logic circuit counts input duty ratios of first high-speed clock signals. The second detection loop is connected between the first multiphase clock generator and the digital logic circuit and generates m-phase clock pulses according to a pair of adjacent clocks output by the first multiphase clock generator, and samples the high-speed clock to be detected under the m-phase clock pulses, and the digital logic circuit counts duty ratios of input second high-speed clock signals. Through the duty ratio detection system, the duty ratios of the high-speed clock to be detected can be fast detected, and the high-speed clock duty ratio detection system is accurate in detection result, high in precision, small in occupied layout area, low in power consumption and wide in application range.
Description
Technical field
The present invention relates to integrated circuit fields, relate more specifically to a kind of high-frequency clock duty ratio detection system.
Background technology
High speed integrated circuit design is more and more higher to the quality of clock signal.Clock signal quality is except traditional clock jitter, and clock duty cycle more and more becomes the key factor that affects high speed integrated circuit performance.So it is very important that the duty ratio of high-frequency clock is carried out detecting in real time.
But, the mode that detects at present the duty ratio of high-frequency clock in integrated circuit is to introduce a high-frequency clock in chip periphery, high-frequency clock to be measured is repeatedly sampled, but the much more peripheral high-frequency clocks of introducing are generally the twice of high-frequency clock frequency to be measured or more, impact due to factors such as chip package, testing equipments, easily cause the duty ratio of the high-frequency clock of introducing, the variation of frequency, thereby make to detect the duty ratio result inaccuracy obtaining.
Therefore, be necessary to provide a kind of improved high-frequency clock duty ratio detection system to overcome above-mentioned defect.
Summary of the invention
The object of this invention is to provide a kind of high-frequency clock duty ratio detection system, duty ratio detection system of the present invention can detect the duty ratio of high-frequency clock to be measured rapidly, and testing result is accurate, precision is high, and the shared chip area of detection system of the present invention is little, low in energy consumption, applied widely.
For achieving the above object, the invention provides a kind of high-frequency clock duty ratio detection system, it comprises the first detection loop and the second detection loop, described the first detection loop comprises the first sampler, the first multiphase clock generator and Digital Logical Circuits, described the first multiphase clock generator produces the pulse of n phase clock according to high-frequency clock to be measured, and the n phase clock pulse of generation is inputed to described the first sampler, n is more than or equal to 3 natural number, described the first sampler is sampled to the high-frequency clock to be measured of input according to the n phase clock pulse receiving, described the first sampler is inputted described Digital Logical Circuits by the first high-speed clock signal after sampling, the duty ratio of the first high-speed clock signal of described Digital Logical Circuits counting input is also exported the first count results, described the second detection loop is connected between described the first multiphase clock generator and described mathematical logic circuit, the adjacent clock that described the second detection loop changes according to a pair of rising edge/trailing edge of described the first multiphase clock generator output produces the pulse of m phase clock, m is more than or equal to 3 natural number, and under the pulse of described m phase clock, described high-frequency clock to be measured is sampled, and the second high-speed clock signal after sampling is inputed to described Digital Logical Circuits, the duty ratio of the second high-speed clock signal of described Digital Logical Circuits counting input is also exported the second count results.
Preferably, described the second detection loop comprises edge logic judging circuit, clock selector, the second multiphase clock generator and the second sampler, described edge logic judging circuit judges that the rising edge/trailing edge of the first high-speed clock signal of described the first sampler output changes, the adjacent two phase clock that described clock selector selects rising edge/trailing edge to change according to the judged result of described edge logic judging circuit in the n phase clock pulse of described the first multiphase clock generator output, and this two phase clock is inputed to described the second multiphase clock generator, described the second multiphase clock generator produces the pulse of m phase clock between the phase place of this adjacent two phase clock, described the second sampler is sampled to the high-frequency clock to be measured of input according to the m phase clock pulse receiving, and the second high-speed clock signal after sampling is inputed to described Digital Logical Circuits, the duty ratio of the second high-speed clock signal of described Digital Logical Circuits counting input is also exported the second count results.
Preferably, the pulse of described m phase clock comprises the adjacent two phase clock pulse of described clock selector output, and the first-phase clock pulse of described m phase clock pulse is the forward phase clock pulse of phase place in described adjacent two phase clock pulse, last phase clock pulse of described m phase clock pulse is the phase clock pulse of phase place after leaning in described adjacent two phase clock pulse.
Preferably, described the first sampler carries out n sampling to described high-frequency clock to be measured within a clock cycle of described high-frequency clock to be measured.
Preferably, described edge logic judging circuit carries out to the first high-speed clock signal of described the first sampler output the judgement that rising edge/trailing edge changes within a clock cycle of described high-frequency clock to be measured.
Compared with prior art, high-frequency clock duty ratio detection system of the present invention is owing to comprising the first detection loop and the second detection loop, described the first detection loop and the second detection loop are all detected the duty ratio of high-frequency clock to be measured, draw respectively the first count results and the second count results, and described the second detection loop is selected the adjacent clock that a pair of rising edge/trailing edge changes and is produced the pulse of m phase clock among the n phase clock pulse of the first detection loop sampling, under this m phase clock pulse, again high-frequency clock to be measured is sampled, thereby the duty ratio that again detects described high-frequency clock to be measured detects, therefore high-frequency clock duty ratio detection system testing result of the present invention is accurate, precision is high, and shared chip area is little, low in energy consumption, applied widely.
By following description also by reference to the accompanying drawings, it is more clear that the present invention will become, and these accompanying drawings are used for explaining the present invention.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of high-frequency clock duty ratio detection system of the present invention.
Fig. 2 is the working timing figure of high-frequency clock duty ratio detection system.
Embodiment
With reference now to accompanying drawing, describe embodiments of the invention, in accompanying drawing, similarly element numbers represents similar element.As mentioned above, the invention provides a kind of high-frequency clock duty ratio detection system, duty ratio detection system of the present invention can detect the duty ratio of high-frequency clock to be measured rapidly, and testing result is accurate, precision is high, the shared chip area of detection system of the present invention is little, low in energy consumption, applied widely.
Please refer to Fig. 1, Fig. 1 is the structured flowchart of high-frequency clock duty ratio detection system of the present invention.As shown in the figure, high-frequency clock duty ratio detection system of the present invention, comprises the first detection loop and the second detection loop, and described the first detection loop and the second detection loop all detect the duty ratio of high-frequency clock to be measured.Described the first detection loop comprises the first sampler, the first multiphase clock generator and Digital Logical Circuits; High-frequency clock CLK to be measured inputs to described the first multiphase clock generator, described the first multiphase clock generator produces the pulse of n phase clock (CLKO1, CLKO2 according to high-frequency clock CLK to be measured ... CLKOn), and by the clock pulse (CLKO1, the CLKO2 that produce ... CLKOn) input to described the first sampler, wherein, the pulse of n phase clock (CLKO1, CLKO2 ... CLKOn), except phase place is different from high-frequency clock CLK to be measured, other parameter is all identical with high-frequency clock CLK to be measured; In the present invention, n is more than or equal to 3 natural number; Described the first sampler is according to the pulse of n phase clock (CLKO1, the CLKO2 that receive ... CLKOn) within a clock cycle of described high-frequency clock CLK to be measured, described high-frequency clock CLK to be measured is carried out to n sampling, thereby obtain the first high-speed clock signal (O1, O2 after sampling ... On), and by described the first high-speed clock signal (O1, O2 ... On) input described Digital Logical Circuits; The first high-speed clock signal (O1, the O2 of the input of described Digital Logical Circuits counting ... On) duty ratio is also exported the first count results A, and precision is 1/n, apparently, described the first high-speed clock signal (O1, O2 ... On) duty ratio of duty ratio and high-frequency clock CLK to be measured is identical, because described the first high-speed clock signal (O1, O2 ... On) phase parameter and the pulse of described n phase clock (CLKO1, CLKO2 ... CLKOn) phase parameter is identical, and only phase place has difference; At this, because the precision of described the first detection loop is 1/n, therefore the first count results A through the output of described Digital Logical Circuits counting is only the integer part in the duty ratio coarse adjustment interval of described high-frequency clock CLK to be measured.Described the second detection loop is connected between described the first multiphase clock generator and described mathematical logic circuit, described the second detection loop is exported according to described the first multiphase clock generator the adjacent clock that a pair of rising edge/trailing edge changes and is produced the pulse of m phase clock, m is more than or equal to 3 natural number, and under the pulse of described m phase clock, described high-frequency clock CLK to be measured is sampled, and obtain the second high-speed clock signal after sampling, and the second high-speed clock signal is inputed to described Digital Logical Circuits, the duty ratio of the second high-speed clock signal of described Digital Logical Circuits counting input is also exported the second count results, and the precision of sampled result is 1/m, because the pulse of described m phase clock is to produce according to a pair of adjacent clock of described the first multiphase clock generator output, therefore through described the second detection loop, detecting the duty ratio result obtaining is the integer part in the duty ratio fine tuning interval of described high-frequency clock CLK to be measured, thereby on the basis of described the first detection loop, described the second detection loop further detects counting to the integer part in the fine tuning interval of the duty ratio of described high-frequency clock CLK to be measured, and therefore, testing result is accurate, precision is high.
Particularly, described the second detection loop comprises edge logic judging circuit, clock selector, the second multiphase clock generator and the second sampler.Described edge logic judging circuit is the first high-speed clock signal (O1, the O2 to described the first sampler output within a clock cycle of described high-frequency clock CLK to be measured ... the variation of rising edge/trailing edge On) judges, also judge clock pulse (CLKO1, CLKO2 ... the variation of rising edge/trailing edge CLKOn), and judged result is inputed to described clock selector, described clock selector is the n phase clock pulse (CLKO1 in described the first multiphase clock generator output according to the judged result of described edge logic judging circuit, CLKO2 ... CLKOn) the adjacent two phase clock pulse of selecting rising edge/trailing edge to change in, and this two phase clock is inputed to described the second multiphase clock generator, when described edge logic judging circuit judges described the first high-speed clock signal (O1, O2 ... when rising edge/trailing edge of the clock signal On-x On) and clock signal O-x-1 (x is the natural number that is less than n) all changes, described clock selector is selected n phase clock pulse (CLKO1, CLKO2 ... CLKOn) two clock pulse CLKOn-x and CLKOn-x-1 of correspondence in, and this two clock pulse is inputed to described the second multiphase clock generator, at this, this two clock pulse CLKOn-x and CLKOn-x-1 are expressed as to CLKx1 and CLKx2 (as shown in Figure 1).Described the second multiphase clock generator produces the pulse of m phase clock (CLKP1, CLKP2 between this two phase clock pulse CLKx1 and the phase place of CLKx2 ... and input to described the second sampler CLKPm), described the second sampler is according to the pulse of m phase clock (CLKP1, the CLKP2 that receive ... CLKPm) the high-frequency clock CLK to be measured of input is sampled, described the second sampler is by the second high-speed clock signal (P1, P2 after sampling ... Pm) input described Digital Logical Circuits, the second high-speed clock signal (P1, the P2 of the input of described Digital Logical Circuits counting ... Pm) duty ratio is also exported the second count results B, apparently, described the second high-speed clock signal (P1, P2 ... Pm) duty ratio is identical with the two clock pulse CLKx1 that selected by described clock selector and the duty ratio of CLKx2, only phase place has difference, separately, as mentioned above, described two clock pulse CLKx1 and CLKx2 are only n phase clock pulse (CLKO1, CLKO2 ... CLKOn) adjacent two clock pulse that in, rising edge/trailing edge all changes, therefore through the second count results B of described Digital Logical Circuits counting output, be the integer part in the duty ratio fine tuning interval of described high-frequency clock CLK to be measured, its precision is 1/n*m.Therefore, the count results A exporting by described Digital Logical Circuits and B can accurately detect the duty ratio of described high-frequency clock CLK to be measured and tie, and testing result is accurate, precision is high.
In the preferred embodiment of the present invention, the m phase clock pulse (CLKP1 of described the second multiphase clock generator output, CLKP2 ... CLKPm) comprise adjacent two phase clock pulse CLKx1 and the CLKx2 of described clock selector output, and described m phase clock pulse (CLKP1, CLKP2 ... CLKPm) first-phase clock pulse is the forward phase clock pulse of phase place in described adjacent two phase clock pulse CLKx1 and CLKx2, last phase clock pulse of described m phase clock pulse is the phase clock pulse of phase place after leaning in described adjacent two phase clock pulse CLKx1 and CLKx2.That is, particularly, when the phase place of described clock pulse CLKx1 is ahead of the phase place of described clock pulse CLKx2, the pulse of m phase clock (CLKP1, CLKP2 ... CLKPm) the first-phase clock pulse CLKP1 in is clock pulse CLKx1; And when the phase place of described clock pulse CLKx2 lags behind the phase place of described clock pulse CLKx1, the pulse of m phase clock (CLKP1, CLKP2 ... CLKPm) last phase clock pulse CLKPm in is clock pulse CLKx; Vice versa.To guarantee the pulse of described m phase clock (CLKP1, CLKP2 ... CLKPm) phase place all drops between the two phase clock pulse CLKx1 and the phase place of CLKx2 of described clock selector selection, thereby has guaranteed the accuracy rate of the result B of described Digital Logical Circuits counting output.
Below in conjunction with Fig. 1 and Fig. 2, the operation principle of high-frequency clock duty ratio detection system of the present invention is described.The pulse of n phase clock (CLKO1, CLKO2 that described the first multiphase clock generator produces according to high-frequency clock CLK to be measured ... CLKOn) height of high-frequency clock CLK (low) level is sampled, as shown in Figure 2, and state the first sampler and sample within a clock cycle (Tp) of high-frequency clock CLK.Within this clock cycle (Tp), the pulse of n phase clock (CLKO1, CLKO2 ... CLKOn) be equivalent to high-frequency clock CLK to carry out n over-sampling of sampling, the precision of sampling is 1/n, and by the first high-speed clock signal (O1, the O2 of sample acquisition ... On) input to described edge logic judging circuit and Digital Logical Circuits.Described edge logic judging circuit is according to the first high-speed clock signal (O1, the O2 of described input ... On), within a clock cycle (Tp) of high-frequency clock CLK to adjacent two adjacent the first high-speed clock signal (O1, O2 ... On) judge the variation of rising edge/trailing edge, thereby show that judged result gives described clock selector, for choosing the needed adjacent clock pair of the second sampler sampling.Described clock selector is the n phase clock pulse (CLKO1 in described the first multiphase clock generator output according to the judged result of described edge logic judging circuit, CLKO2 ... CLKOn) in, select the adjacent two phase clock pulse that rising edge/trailing edge changes (adjacent clock to), and this two phase clock CLKx1 and CLKx2 (being illustrated in figure 2 clock pulse CLKO1 and CLKO2) are inputed to described the second multiphase clock generator, described the second multiphase clock generator produces m phase clock pulse (CLKP1 between this two phase clock pulse CLKx1 and the phase place of CLKx2, CLKP2 ... CLKPm), described the second sampler is according to the m phase clock pulse (CLKP1 receiving, CLKP2 ... CLKPm) the high-frequency clock CLK to be measured of input is sampled, and by the second high-speed clock signal (P1 after sampling, P2 ... Pm) input described Digital Logical Circuits.The result that described Digital Logical Circuits is exported according to the first sampler and the second sampler, within a clock cycle of high-frequency clock CLK, to sampled the first high-speed clock signal (O1, O2 ... On) count, draw the first count results A; To sampled the second high-speed clock signal (P1, P2 ... Pm) count, draw the second count results B.
By calculating, can obtain, the duty ratio DCD of high-frequency clock CLK to be measured is:
DCD＝A÷n+B÷n÷m
Wherein: n, the value of m can design according to actual conditions, notoriously, and n, m value is larger, and the precision of the above results is higher.In the present invention, the duty ratio accuracy of detection of described high-frequency clock CLK to be measured is 1/n*m, and testing result is accurate, precision is high.
Invention has been described for above combination most preferred embodiment, but the present invention is not limited to the embodiment of above announcement, and should contain the various modifications of carrying out according to essence of the present invention, equivalent combinations.
Claims (5)
1. a high-frequency clock duty ratio detection system, it is characterized in that, comprise the first detection loop and the second detection loop, described the first detection loop comprises the first sampler, the first multiphase clock generator and Digital Logical Circuits, described the first multiphase clock generator produces the pulse of n phase clock according to high-frequency clock to be measured, and the n phase clock pulse of generation is inputed to described the first sampler, n is more than or equal to 3 natural number, described the first sampler is sampled to the high-frequency clock to be measured of input according to the n phase clock pulse receiving, described the first sampler is inputted described Digital Logical Circuits by the first high-speed clock signal after sampling, the duty ratio of the first high-speed clock signal of described Digital Logical Circuits counting input is also exported the first count results, described the second detection loop is connected between described the first multiphase clock generator and described mathematical logic circuit, the adjacent clock that described the second detection loop changes according to a pair of rising edge/trailing edge of described the first multiphase clock generator output produces the pulse of m phase clock, m is more than or equal to 3 natural number, and under the pulse of described m phase clock, described high-frequency clock to be measured is sampled, and the second high-speed clock signal after sampling is inputed to described Digital Logical Circuits, the duty ratio of the second high-speed clock signal of described Digital Logical Circuits counting input is also exported the second count results.
2. high-frequency clock duty ratio detection system as claimed in claim 1, it is characterized in that, described the second detection loop comprises edge logic judging circuit, clock selector, the second multiphase clock generator and the second sampler, described edge logic judging circuit judges that the rising edge/trailing edge of the first high-speed clock signal of described the first sampler output changes, the adjacent two phase clock that described clock selector selects rising edge/trailing edge to change according to the judged result of described edge logic judging circuit in the n phase clock pulse of described the first multiphase clock generator output, and this two phase clock is inputed to described the second multiphase clock generator, described the second multiphase clock generator produces the pulse of m phase clock between the phase place of this adjacent two phase clock, described the second sampler is sampled to the high-frequency clock to be measured of input according to the m phase clock pulse receiving, and the second high-speed clock signal result after sampling is inputed to described Digital Logical Circuits, the duty ratio of the second high-speed clock signal of described Digital Logical Circuits counting input is also exported the second count results.
3. high-frequency clock duty ratio detection system as claimed in claim 2, it is characterized in that, the pulse of described m phase clock comprises the adjacent two phase clock pulse of described clock selector output, and the first-phase clock pulse of described m phase clock pulse is the forward phase clock pulse of phase place in described adjacent two phase clock pulse, last phase clock pulse of described m phase clock pulse is the phase clock pulse of phase place after leaning in described adjacent two phase clock pulse.
4. high-frequency clock duty ratio detection system as claimed in claim 2, is characterized in that, described the first sampler carries out n sampling to described high-frequency clock to be measured within a clock cycle of described high-frequency clock to be measured.
5. high-frequency clock duty ratio detection system as claimed in claim 2, it is characterized in that, described edge logic judging circuit carries out to the first high-speed clock signal of described the first sampler output the judgement that rising edge/trailing edge changes within a clock cycle of described high-frequency clock to be measured.
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| CN109981085A (en) * | 2017-12-26 | 2019-07-05 | 爱思开海力士有限公司 | Clock monitoring circuit |
| CN113300692A (en) * | 2021-05-08 | 2021-08-24 | 黑芝麻智能科技(上海)有限公司 | System and method for monitoring clock duty cycle |
| CN114155903A (en) * | 2020-09-07 | 2022-03-08 | 长鑫存储技术有限公司 | Test system and test method |
| CN117250480A (en) * | 2023-11-08 | 2023-12-19 | 英诺达(成都)电子科技有限公司 | Loop detection method, device, equipment and storage medium of combinational logic circuit |
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