CN112117995A - FPGA (field programmable Gate array) on-chip clock duty ratio test method and clock self-test FPGA - Google Patents

FPGA (field programmable Gate array) on-chip clock duty ratio test method and clock self-test FPGA Download PDF

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CN112117995A
CN112117995A CN202011061235.3A CN202011061235A CN112117995A CN 112117995 A CN112117995 A CN 112117995A CN 202011061235 A CN202011061235 A CN 202011061235A CN 112117995 A CN112117995 A CN 112117995A
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clock
output
signal
fpga
trigger
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贾楫
丛伟林
何相龙
孙海
蔡莹卓
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Chengdu Sino Microelectronics Technology Co ltd
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Chengdu Sino Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19—Monitoring patterns of pulse trains

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  • Nonlinear Science (AREA)
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Abstract

A method for testing the clock duty ratio in an FPGA chip and a clock self-testing FPGA relate to the integrated circuit technology. The invention discloses a clock self-test FPGA (field programmable gate array), which comprises an I/O (input/output) interface unit, a clock management circuit unit and a tested clock network, and is characterized by also comprising a D trigger, wherein the input end of the clock management circuit unit is connected with a clock source, the first output end of the clock management circuit unit is connected with the input end of the tested clock network, the output end of the tested clock network is connected to the D end of the D trigger, the second output end of the clock management circuit unit is connected with the input end of a sampling clock network, the output end of the sampling clock network is connected to the CLK (clock) end of the D trigger, the output end of the D trigger is connected to an output logic detection function circuit, the output logic detection function circuit is connected with the I/O interface unit, and a dynamic phase shift logic function control module is. The invention reduces the index requirement on the test instrument and equipment.

Description

FPGA (field programmable Gate array) on-chip clock duty ratio test method and clock self-test FPGA
Technical Field
The present invention relates to integrated circuit technology.
Background
It is the most common test method to input clock signals to the tested piece by using an I/O test interface of the FPGA and using an instrument device such as a pulse pattern generator and a signal source, and then using an oscilloscope to measure the duty cycle parameters of the output clock signals. By comparing the input clock signal with the output clock signal, the parameter performance variation of the clock signal duty ratio can be measured. The test method is easy to operate and record. However, the test under the high-precision condition needs to use an oscilloscope with an extremely high sampling rate, so that the test cost is increased. At the same time, the maximum achievable measurement frequency is limited by the performance of the I/O interface. The IBIS interface characteristics of the I/O interface may also have an effect on the duty cycle test results.
Disclosure of Invention
The invention aims to provide a low-cost on-chip clock signal testing technology.
The technical scheme adopted by the invention for solving the technical problems is that the method for testing the duty ratio of the clock in the FPGA chip is characterized by comprising the following steps:
1) processing a source clock signal by a FPGA on-chip clock circuit management unit to generate two paths of output clocks, wherein the first path of output clock is a phase fixed clock, and the second path of output clock is a phase-shifted clock;
2) the first path of output clock is input into a tested clock network in the FPGA chip, the output signal of the tested clock network is used as the D end input signal of the D trigger, and the second path of output clock is used as the CLK end input clock signal of the D trigger;
3) from the initial state, with the preset duration as a period, the phase of the second output clock is kept unchanged in each period, and a step value Ps is increased in phase in the next period until the test is terminated;
4) and taking the output square wave of the D trigger as a calculation basis, regarding a rising edge jitter area and a falling edge jitter area, taking the first signal edge in the jitter area as an equivalent signal edge, or taking the last signal edge in the jitter area as an equivalent signal edge to form an equivalent square wave signal, and calculating the duty ratio of the equivalent square wave as the duty ratio of an output signal of the measured clock network.
Further, the step 2) comprises:
and adjusting the frequency of the output clock to ensure that the frequency of the first output clock is M times of that of the second output clock, wherein the preset value of M is a positive integer greater than 1.
The clock self-testing FPGA comprises an I/O interface unit, a clock management circuit unit and a tested clock network and is characterized by further comprising a D trigger, wherein the input end of the clock management circuit unit is connected with a clock source, the first output end of the clock management circuit unit is connected with the input end of the tested clock network, the output end of the tested clock network is connected to the D end of the D trigger, the second output end of the clock management circuit unit is connected with the input end of a sampling clock network, the output end of the sampling clock network is connected to the CLK end of the D trigger, the output end of the D trigger is connected to an output logic detection function circuit, the output logic detection function circuit is connected with the I/O interface unit, and a dynamic phase shift logic function control module is connected with the clock management circuit unit.
The invention constructs the test function circuit by using the FPGA on-chip circuit resource, tests the on-chip clock signal in a more direct mode, simultaneously reduces the index requirement on test instrument equipment and effectively reduces the test cost.
The invention is feasible through actual measurement verification on an FPGA chip. The test results under the different test conditions are shown in fig. 6 and 7. Among them, the unstable output region (corresponding to 5001 of fig. 5) under the test condition corresponding to fig. 6 is narrow; the clock jitter increases under the test conditions corresponding to fig. 7, and thus the unstable output region (corresponding to 5001 of fig. 5) is wide. It can also be seen from fig. 7 that in the high and low stable output regions there is still a small amount of glitch signal, which is actually generated by the crosstalk signals present in the clock network inside the FPGA chip. That is, using this test method, not only the duty cycle of the clock signal can be measured, but also for observing the crosstalk signals present in the clock network.
Due to the adoption of the clock management circuit unit in the FPGA chip, the working frequency of a clock signal under the normal temperature condition can reach more than 1900MHz, and is far beyond the upper limit of the working frequency of a conventional level standard I/O interface. The requirements of the invention on test instruments and equipment are low, as shown in fig. 6 and 7, the test requirements can be met only by using an oscilloscope with the analog bandwidth of 300 MHz.
Drawings
Fig. 1 is a schematic diagram of the principle of the present invention.
Fig. 2 is a schematic diagram of the phase relationship of two output clocks.
Fig. 3 is a schematic diagram of the phase relationship change of two output clocks in the dynamic phase shift control mode.
Fig. 4 is a clock-triggered sampling schematic.
Fig. 5 is a diagram showing an actual waveform of the Q output of the D flip-flop.
Fig. 6 is a schematic (photograph) of oscilloscope output waveform 1.
Fig. 7 is a schematic (photo) of oscilloscope output waveform 2.
FIG. 8 is a schematic structural view of embodiment 1.
FIG. 9 is a schematic view of a phase shift control process in embodiment 2.
Fig. 10 is a schematic diagram of the initial phase state of embodiment 2.
Fig. 11 is a schematic diagram of phase state 1 of embodiment 2.
Fig. 12 is a schematic diagram of phase state 2 of embodiment 2.
Fig. 13 is a schematic diagram of phase state 3 of embodiment 2.
Fig. 14 is a schematic diagram of phase state 4 of embodiment 2.
Fig. 15 is a schematic diagram of phase state 5 of embodiment 2.
Fig. 16 is a schematic diagram of phase state 6 of embodiment 2.
Fig. 17 is a schematic diagram of the duty ratio calculation in embodiment 2.
Detailed Description
The invention takes a clock management circuit unit with a dynamic phase shift function in an FPGA chip as a basis, generates at least two paths of clock signals with a certain frequency and phase relation, performs continuous and stable phase shift control, samples the clock signals by a trigger circuit, and finally obtains the duty ratio parameters of the clock signals by analyzing and calculating the output waveform.
As an embodiment, the FPGA on-chip clock duty ratio test method of the invention comprises the following steps:
1) inputting an external clock signal to the FPGA;
2) processing an external clock signal by a FPGA on-chip clock circuit management unit to generate two paths of output clocks, wherein the first path of output clock is a phase fixed clock, and the second path of output clock is a phase-shifted clock;
3) the first path of output clock is input into a tested clock network in the FPGA chip, the output signal of the tested clock network is used as the D end input signal of the D trigger, and the second path of output clock is used as the CLK end input clock signal of the D trigger;
4) from the initial state, taking preset duration as a phase shift period, keeping the phase of the second output clock unchanged in each phase shift period, and increasing a step value Ps in the phase in the next phase shift period until the test is terminated; for example:
in the first phase shift period, the phase of the second output clock is consistent with that of the first output clock, the phase difference is 0,
in the second phase shift period, the phase difference between the second output clock and the first output clock is Ps,
in the third phase shift period, the phase difference between the second output clock and the first output clock is 2 times Ps,
in the fourth phase shift period, the phase difference between the second output clock and the first output clock is 3 times Ps,
and so on.
5) And taking the output square wave of the D trigger as a calculation basis, regarding a rising edge jitter area and a falling edge jitter area, taking the first signal edge in the jitter area as an equivalent signal edge, or taking the last signal edge in the jitter area as an equivalent signal edge to form an equivalent square wave signal, and calculating the duty ratio of the equivalent square wave as the duty ratio of an output signal of the measured clock network.
For example, in FIG. 5, 5001 shows the jitter region, which may also be referred to as an unstable output region, and FIG. 5 shows the first signal edge of the jitter regionAs equivalent signal edges, THIGHThe region being a high level region, TLOWThe region is a low level region, and this case is equivalent to the jitter region "converging forward", and similarly, the last signal edge of the jitter region may also be used as the equivalent signal edge, i.e. the jitter region "converging backward", and the principle is the same.
Further, the step 2) comprises: and adjusting the frequency of the output clock to ensure that the frequency of the first output clock is M times of that of the second output clock, wherein M is a positive integer greater than 1.
In this embodiment, an off-chip clock source is adopted, and obviously, as another embodiment, an on-chip clock source may be adopted, and the on-chip clock source provides a clock signal.
The minimum system architecture for testing the duty ratio of a clock signal is shown in fig. 1, and a test system at least comprises a clock management circuit unit (1002) with a dynamic phase shift function. Taking HWDSP series FPGA of chengdua microelectronics ltd as an example, its internal clock management circuit unit has a dynamic phase shift function, by which dynamic phase shift control of minimum phase adjustment stepping with a precision of up to fifty picoseconds can be realized. By using the dynamic phase shift function, the phase of the selected channel can be dynamically adjusted only under the condition of not changing the frequency and the duty ratio of each output clock of the clock management unit. The dynamic phase shift function belongs to the mature prior art, and the internal structure thereof is not described in detail.
Two output clocks (1003 and 1005) are respectively generated by a clock management circuit unit, and a 1 st clock signal is used as an input signal of a measured clock network (1004) and then is connected to a D input port of a trigger (1008). The duty ratio of the two output clocks can be flexibly set through software. Wherein, only one of the two output clocks is selected to start the attribute of the dynamic phase shift control function, so that the relative phase relation between the two output clocks can be controlled by the dynamic phase shift control function. Meanwhile, the frequencies of the two paths of output clock signals need to be kept consistent, or the frequency of the 1 st path of output clock signal is set to be integral multiple of the 2 nd path of output clock signal. The 2 nd output clock signal (1005) is used as the input signal to the sampling clock network (1007) and then coupled to the CLK input port of the flip-flop. And finally, outputting a Q output signal of the trigger through an I/O interface, and connecting the Q output signal to an oscilloscope or other forms of detection circuits for measurement and analysis.
The dynamic phase shift logic control function module (1006) is a logic circuit for performing dynamic phase shift control on the clock management circuit unit. The functional module can be realized by using logic resources in the FPGA chip; it may also be implemented using circuitry external to the FPGA, which then couples the dynamic phase shift control bus signals to the FPGA via the I/O interface.
The specific working principle of the present invention is shown in fig. 2, and in the initial state of dynamic phase shift, the relative phase relationship between the 1 st path output clock and the 2 nd path output clock is fixed and unchanged. After the dynamic phase shift control function of the dynamic phase shift logic control function module is started, the relative phase between the two output clocks changes by a fixed value at a fixed time interval. When the device continuously works in the state, the change situation of the phase relation between the two output clocks along with the time is shown in fig. 3, namely, the continuous and stable scanning type adjustment of the relative phase of the two output clocks is realized. Meanwhile, the phase change mode can be flexibly set, and can be set to be increased in an increasing mode or decreased in a decreasing mode.
After the two clock signals reach the flip-flop (1008) through different clock networks, the D and CLK input signals of the flip-flop are at the same frequency, and the flip-flop is a rising edge sampling for example. As shown in fig. 4, under this condition, the phase difference between each rising edge of the CLK signal and the rising edge of the D signal is the same value, PDELTA. Therefore, if other factors such as jitter and metastable state of the clock signal are not considered, ideally, the Q output signal of the flip-flop should be a fixed value, i.e., a stable high level or low level, when the phase relationship between D and CLK is not changed.
Under the continuous dynamic phase shift control state, the relative phase between the two output clocks changes by a fixed value at intervals of a fixed time length. In this case, according to the above test principle, the Q port of the flip-flop outputs a square wave signal with a stable duty ratio. And the duty cycle of the square wave signal is equal to the duty cycle of the sampled signal, i.e., the input signal of the flip-flop D.
Due to the jitter superimposed on the clock signal, the metastable state, the setup and hold time of the flip-flop, and other factors, the signal actually output by the flip-flop is not an ideal square wave signal, but is in a waveform state as shown in fig. 5. In the range of the gray shaded area, namely the unstable output area (5001), Q output of the flip-flop is unstable, and random high-low level jump can occur. The temporal width of each unstable output region (5001) is found to be approximately equal in most cases by oscilloscope measurements. Thus, the Q of the flip-flop outputs the duty cycle D of the signal via the I/O interfaceQCan be calculated according to the following formula, namely:
DQ＝THIGH/(THIGH+TLOW)
meanwhile, since the dynamic phase shift in the present invention is scanned at fixed phase adjustment time intervals and phase adjustment steps, the duty value D is setQAnd the duty ratio of the D port input clock of the trigger in the FPGA chip is equal to the duty ratio of the D port input clock of the trigger in the FPGA chip.
The duty ratio of the two clocks output by the clock management circuit unit (1002) can be set through software. By comparing the 1 st output clock (1003) with the duty ratio DQ measured by the method, the change of the duty ratio parameter after the clock signal passes through the measured clock network (1004) can be observed.
With reference to figure 17 of the drawings,
the high-level time width of the input signal of the flip-flop D is TD1, and the low-level time width is TD 2. The phase adjustment of the clock signal of the flip-flop CLK is stepped to Ps, so that the number of phase adjustments required to complete high-level scanning of the input signal of the flip-flop D by adjusting the phase of the clock signal of the flip-flop CLK is N1 ═ TD1/Ps, that is, corresponding to N1 clock dwells; the low level scan of the input signal of the flip-flop D is completed, and the required number of phase adjustments is N2 ═ TD2/Ps, i.e. corresponding to N2 clock dwell periods.
Wherein each clock dwell period corresponds to K flip-flop CLK clock periods (Tclk).
TQ1＝N1×(K×Tclk)＝(TD1/Ps)×(K×Tclk)；
TQ2＝N2×(K×Tclk)＝(TD2/Ps)×(K×Tclk)；
The duty cycle of the output clock of the flip-flop Q is:
DC_Q＝TQ1/(TQ1+TQ2)
＝(TD1/Ps)×(K×Tclk)/((TD1/Ps)×(K×Tclk)+(TD2/Ps)×(K×Tclk))
＝TD1/(TD1+TD2)
the duty cycle of the input signal of the flip-flop D is:
DC_D＝TD1/(TD1+TD2)
it can be seen that the duty cycle of the output clock of flip-flop Q is equal to the duty cycle of the input signal of flip-flop D. And the duty cycle of the output signal of the flip-flop Q can be measured using an oscilloscope.
Example 1
Referring to fig. 8, this embodiment may add an output logic detection function circuit based on the typical test system architecture of fig. 1, without using an oscilloscope.
The maximum working frequency which can be reached by the logic circuit resource in the FPGA chip is far lower than the upper frequency limit which can be reached by the clock management circuit unit. Therefore, the working clock frequency of the output logic detection function circuit (8009) cannot be too high, and the working clock frequency can be set to 200MHz or lower in general according to engineering application experience. In order to meet the requirement, the operating frequency of the 2 nd output clock (8005) can be reduced, the 1 st output clock and the 2 nd output clock are in integral multiple relation, and the operating frequency of the 2 nd output clock is lower than the operating clock frequency of the output logic detection function circuit (8009), so as to meet the requirement of practical engineering application.
The output logic detection function circuit can automatically identify the stable region and the unstable region of the output of the trigger (8008) and calculate DQAnd the duty ratio test result can be sent to the PC computer end through communication interfaces such as SPI, UART and USB. The test efficiency is further improved, and the hardware of the test system is simplified.
Example 2
This embodiment explains the phase shift control process in detail, referring to fig. 9 to 17.
As shown in fig. 9, Ps is set to a fixed phase adjustment step value throughout the duty cycle test, the CLK clock signal of the flip-flop is held for K clock cycles (K is an integer) in each phase state, the D input signal is sampled by the flip-flop, and the Q signal is output.
Fig. 10 to 16 show the principle of phase change of the CLK terminal input and the Q terminal output of the D flip-flop in a stepwise manner. The invention scans the duty ratio of the high-frequency clock signal in the chip by low-speed phase scanning, greatly reduces the testing cost and can ensure the testing precision of dozens of picoseconds.
The description and the drawings clearly illustrate the principle and the necessary technical content of the present invention, and the related functional modules are mature technologies, so that the ordinary skilled person can implement the present invention according to the disclosure of the present invention, and details such as the internal structure of the module and the like are not described again.

Claims (3)

  1. The method for testing the duty ratio of the clock in the FPGA chip is characterized by comprising the following steps of:
    1) processing a source clock signal by a FPGA on-chip clock circuit management unit to generate two paths of output clocks, wherein the first path of output clock is a phase fixed clock, and the second path of output clock is a phase-shifted clock;
    2) the first path of output clock is input into a tested clock network in the FPGA chip, the output signal of the tested clock network is used as the D end input signal of the D trigger, and the second path of output clock is used as the CLK end input clock signal of the D trigger;
    3) from the initial state, taking preset duration as a phase shift period, keeping the phase of the second output clock unchanged in each phase shift period, and increasing a step value Ps in the phase in the next phase shift period until the test is terminated;
    4) and taking the output square wave of the D trigger as a calculation basis, regarding a rising edge jitter area and a falling edge jitter area, taking the first signal edge in the jitter area as an equivalent signal edge, or taking the last signal edge in the jitter area as an equivalent signal edge to form an equivalent square wave signal, and calculating the duty ratio of the equivalent square wave as the duty ratio of an output signal of the measured clock network.
  2. 2. The FPGA on-chip clock duty cycle test method of claim 1, wherein the step 2) comprises:
    and adjusting the frequency of the output clock to ensure that the frequency of the first output clock is M times of that of the second output clock, wherein the preset value of M is a positive integer greater than 1.
  3. 3. The clock self-testing FPGA comprises an I/O interface unit, a clock management circuit unit and a tested clock network and is characterized by further comprising a D trigger, wherein the input end of the clock management circuit unit is connected with a clock source, the first output end of the clock management circuit unit is connected with the input end of the tested clock network, the output end of the tested clock network is connected to the D end of the D trigger, the second output end of the clock management circuit unit is connected with the input end of a sampling clock network, the output end of the sampling clock network is connected to the CLK end of the D trigger, the output end of the D trigger is connected to an output logic detection function circuit, the output logic detection function circuit is connected with the I/O interface unit, and a dynamic phase shift logic function control module is connected with the clock management circuit unit.
CN202011061235.3A 2020-09-30 2020-09-30 FPGA (field programmable Gate array) on-chip clock duty ratio test method and clock self-test FPGA Pending CN112117995A (en)

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Citations (6)

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US7107477B1 (en) * 2003-01-31 2006-09-12 Altera Corporation Programmable logic devices with skewed clocking signals
CN105759195A (en) * 2016-02-24 2016-07-13 复旦大学 Setup-hold time test system and setup-hold time test method based on fine phase modulation
CN108389225A (en) * 2018-01-10 2018-08-10 北京理工大学 A kind of TDC implementation methods based on FPGA
CN109918695A (en) * 2017-12-13 2019-06-21 英特尔公司 Distribution type programmable delay line in Clock Tree
CN111279614A (en) * 2017-10-19 2020-06-12 赛灵思公司 Quadrature clock correction circuit for transmitter
CN213637693U (en) * 2020-09-30 2021-07-06 成都华微电子科技有限公司 Clock self-testing FPGA

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7107477B1 (en) * 2003-01-31 2006-09-12 Altera Corporation Programmable logic devices with skewed clocking signals
CN105759195A (en) * 2016-02-24 2016-07-13 复旦大学 Setup-hold time test system and setup-hold time test method based on fine phase modulation
CN111279614A (en) * 2017-10-19 2020-06-12 赛灵思公司 Quadrature clock correction circuit for transmitter
CN109918695A (en) * 2017-12-13 2019-06-21 英特尔公司 Distribution type programmable delay line in Clock Tree
CN108389225A (en) * 2018-01-10 2018-08-10 北京理工大学 A kind of TDC implementation methods based on FPGA
CN213637693U (en) * 2020-09-30 2021-07-06 成都华微电子科技有限公司 Clock self-testing FPGA

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