CN114414874A - High-precision self-calibration synchronous triggering device and method - Google Patents
High-precision self-calibration synchronous triggering device and method Download PDFInfo
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Abstract
The invention relates to a synchronous trigger device, in particular to a high-precision self-calibration synchronous trigger device and a method, which solve the technical problems of low precision, slow leading edge and difficult calibration of a large-scale data acquisition synchronous trigger device in the existing large-scale pulse power device; the high-precision self-calibration synchronous trigger device comprises a preprocessing circuit, a fan-out circuit, a reference channel, n paths of calibration channels, a logic OR circuit, a calibration enable circuit and a calibration signal circuit, wherein n is more than or equal to 2; the output end of the preprocessing circuit is connected with the input end of the fan-out circuit; the reference channel and the n paths of calibration channels are connected in parallel at the output end of the fan-out circuit; the reference channel comprises a reference delay circuit and a reference driving circuit which are connected in sequence; each calibration channel comprises a calibration delay circuit, a calibration driving circuit, a comparison circuit and a delay driving circuit; the invention also provides a high-precision self-calibration synchronous triggering method based on the high-precision self-calibration synchronous triggering device.
Description
Technical Field
The invention relates to a synchronous trigger device, in particular to a high-precision self-calibration synchronous trigger device and an implementation method based on the high-precision self-calibration synchronous trigger device.
Background
With the rapid development of pulse power technology in recent years, the pulse power device has the characteristics of high power, large device and parallel operation of a plurality of pulse power devices; the 'PolyLong No. one' developed by the Chinese institute of engineering and physics uses an oscilloscope to construct a 300-path data acquisition system; when a large-scale oscilloscope system is used for data acquisition, all the oscilloscopes must be triggered simultaneously to ensure that all data have the same zero time.
The existing synchronous trigger device has two implementation modes, one mode is that commercial devices are used for construction, for example, a mode that a power divider DG535+ DG645+ is used in American Hermes III to complete the trigger of 65 oscilloscopes, and due to the problems that the timing precision (less than 1ns), the delay time (more than 85ns), the output channel is insufficient (8 channels) and the like of the DG535 and the DG645, large-scale data acquisition is carried out in a large-scale pulse power device, and the error is large when the acquisition time is zero; the other scheme is that high-voltage output is adopted, and a power divider is used for distribution to ensure consistency among output signals, but because the high-speed pulse power divider is usually a resistance power divider, insertion loss is large, the output voltage of one 64 power divider can only reach 1/64 of the input voltage, and the leading edge time is unchanged; the output leading edges of the common high-voltage output chips are all larger than 1ns, so that the problems of low output signal voltage and slow leading edge are caused.
For a high-precision data acquisition system, the synchronous trigger device can affect the parameters of an output chip by using factors such as temperature, humidity, aging rate and the like, and further affect the parameters of output jitter, delay and the like of the output chip, so that the synchronous trigger device needs to be calibrated at regular time after the equipment works for a period of time; and the data acquisition system of the large-scale pulse power device is huge, so that the workload of dismounting and mounting the synchronous trigger device is large, the synchronous trigger device needs to be stopped for a plurality of days for calibration, however, the machine time of the large-scale pulse power device is very precious, and the long-time shutdown maintenance task cannot be accepted, so that the synchronous trigger device is not feasible to be dismounted for inspection and calibration.
In summary, the synchronous trigger device for large-scale data acquisition in the existing large-scale pulse power device has the problems of low precision, slow leading edge and difficult calibration, and is difficult to meet the batch data acquisition requirement of the large-scale pulse power device.
Disclosure of Invention
The invention aims to solve the technical problems of low precision, slow leading edge and difficult calibration of a large-scale data acquisition synchronous trigger device in the conventional large-scale pulse power device, and provides a high-precision self-calibration synchronous trigger device and a high-precision self-calibration synchronous trigger method, which are used for realizing the high-precision, fast leading edge and self-calibration functions of the large-scale pulse power synchronous trigger device and meeting the requirement of large-scale pulse power device on batch data acquisition.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a high-precision self-calibration synchronous trigger device is characterized in that: the system comprises a preprocessing circuit, a fan-out circuit, a reference channel, n paths of calibration channels, a logic OR circuit, a calibration signal circuit and a calibration enable, wherein n is more than or equal to 2;
one input end of the preprocessing circuit is used for connecting an external trigger input, and the output end of the preprocessing circuit is connected with the input end of the fan-out circuit and used for generating n +1 paths of same square wave signals which are provided for the reference channel and the n paths of calibration channels;
the reference channel comprises a reference delay circuit and a reference driving circuit which are connected in sequence; the input end of the reference delay circuit is connected with one output end of the fan-out circuit; the output end of the reference driving circuit is used as a reference signal and is used for providing a calibration reference signal for the n paths of calibration channels;
each calibration channel comprises a calibration delay circuit, a calibration driving circuit, a comparison circuit and a delay driving circuit which are connected in sequence;
one input end of the calibration delay circuit is connected with the corresponding output end of the fan-out circuit, and the output end of the calibration delay circuit is connected with the input end of the calibration driving circuit; the output end of the calibration driving circuit is used as a calibration driving signal of a corresponding calibration channel and is used for synchronously triggering the corresponding oscillograph;
the calibration driving signal is connected with the non-inverting input end of the comparison circuit, and the inverting input end of the comparison circuit is connected with the reference signal; the output end of the comparison circuit is connected with one input end of the delay driving circuit and is simultaneously connected with the corresponding input end of the logic OR circuit;
the output end of the delay driving circuit is connected with the other input end of the calibration delay circuit and is used for controlling the output signal of the calibration delay circuit to increase by a step value;
the output end of the logic OR circuit is connected with one input end of the calibration signal circuit and used for providing a calibration signal source for the preprocessing circuit during calibration;
the output end of the calibration signal circuit is connected with the other input end of the preprocessing circuit;
the output end of the calibration enable is connected with the other input end of the calibration signal circuit, and is simultaneously connected with the other input ends of the n delay driving circuits, and is used for providing a calibration enable signal.
Furthermore, the output signal width of the calibration driving circuit is larger than or equal to the output signal width of the calibration driving circuit plus the step value of the output signal of the calibration driving circuit.
Furthermore, the reference delay circuit adopts a delay line + RC delay mode to realize broadening delay of the reference signal; the calibration delay circuit adopts an RC circuit.
Further, the fan-out circuit comprises one or more stages of same fan-out structures for fan-out.
The invention also provides a high-precision self-calibration synchronous triggering method based on the high-precision self-calibration synchronous triggering device, which is characterized by comprising the following steps of:
step 2.1: turning on a calibration enable, and sending a calibration signal source to the preprocessing circuit by the calibration signal circuit;
step 2.2: triggering a preprocessing circuit to generate a preprocessing square wave, wherein the preprocessing square wave is fanned out n +1 paths of same square wave signals by a fan-out circuit and respectively provided for a reference channel and n paths of calibration channels;
step 2.3: the square wave signal of the reference channel is widened by the reference delay circuit and amplified by the reference driving circuit to output a reference signal; the square wave signals of the n paths of calibration channels are respectively delayed by the calibration delay circuit and then output calibration delay signals, and the calibration delay signals are amplified by the calibration driving circuit and then output n paths of calibration driving signals;
step 2.4: respectively inputting the reference signals into the inverting input ends of the comparison circuits, and respectively inputting the n paths of calibration driving signals into the non-inverting input ends of the corresponding comparison circuits for comparison to obtain n paths of comparison outputs;
and simultaneously judging whether the comparison output of the n paths of calibration channels is 1:
if yes, increasing a step value for the calibration delay signal output by the corresponding calibration delay circuit;
otherwise, the corresponding calibration channel is calibrated;
step 2.5: carrying out logical OR operation on the n paths of comparison output to obtain a logical control signal, and judging whether the logical control signal is 1;
if yes, the calibration signal circuit sends a calibration signal source to the preprocessing circuit again, and the step 2.2 is returned;
if not, finishing the calibration of the reference signal and the n paths of calibration driving signals, and executing the step 3;
and step 3: synchronous trigger oscilloscope
And turning off the calibration enable, triggering the preprocessing circuit by an external trigger input signal, outputting n paths of calibration driving signals by a square wave signal generated by the preprocessing circuit through the fan-out circuit and the n paths of calibration channels, synchronously triggering the oscilloscope by the n paths of calibration driving signals, and simultaneously acquiring an output signal of the pulse power device by the oscilloscope.
Further, the fan-out circuit may fan out through one or more stages of the same fan-out structure.
Further, in step 2.5, the calibration delay circuit stores the delay adjustment parameter.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that:
1. the invention relates to a high-precision self-calibration synchronous trigger device, which adopts a mode of high-speed fan-out, calibration delay and drive delay of a fan-out circuit, a reference channel and n calibration channels to realize that n trigger signals output synchronous trigger signals simultaneously, has the advantages of multiple output channels (the fan-out of 2 levels can reach 64 channels), fast front edge (can be lower than 300ps), small dispersion among channels (can reach ten ps magnitude), small transmission delay (ten ns magnitude) and ns magnitude of complete machine delay, and solves the problems of low precision and slow front edge of the synchronous trigger device disturbing a large-scale data acquisition system.
2. The high-precision self-calibration synchronous trigger device adopts the comparison circuit and the delay driving circuit, automatically realizes the self-calibration function of output signals of the reference channel and the n-channel calibration channel by a method of comparison and delay adjustment, can finish ps-level automatic calibration without an external instrument, has the characteristics of high precision, convenience and quickness in calibration and high reliability, and can be applied to various large-scale data acquisition systems and data acquisition systems with higher requirements on synchronism.
Drawings
FIG. 1 is a schematic diagram of a batch data acquisition system for a large pulse power device;
FIG. 2 is a circuit diagram of a reference channel and n calibration channels in a high-precision self-calibration synchronous triggering device according to the present invention;
fig. 3(a) is a schematic diagram of a first timing sequence of a comparison circuit in the high-precision self-calibration synchronous trigger device of the present invention, where a is a square wave signal output by a calibration channel, B is a square wave signal output by a reference channel, and C is a logic result "1" output by the comparison circuit;
fig. 3(B) is a second timing diagram of the comparison circuit in the high-precision self-calibration synchronous trigger device of the present invention, wherein a is the square wave signal output by the calibration channel, B is the square wave signal output by the reference channel, and C is the logic result "0" output by the comparison circuit;
FIG. 4 is a schematic diagram of a reference delay circuit in a high-precision self-calibrated synchronous trigger device according to the present invention after a square wave is widened;
FIG. 5 is a flow chart of a high-precision self-calibration synchronous triggering method of the present invention, wherein a synchronous triggering device employs a reference channel and n calibration channels;
the reference numbers in the figures are:
1-synchronous trigger device, 2-oscilloscope, 3-pulse power device;
11-preprocessing circuit, 12-fan-out circuit, 13-reference channel, 131-reference delay circuit, 132-reference driving circuit, 14-n calibration channels, 141-calibration delay circuit, 142-calibration driving circuit, 143-comparison circuit, 144-delay driving circuit, 15-logical OR circuit, 16-calibration signal circuit and 17-calibration enable.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1, in a large-scale pulse power device 3 batch pulse data acquisition system, an oscilloscope 2 and a synchronous trigger device 1 are core parts of the batch pulse data acquisition system, an output pulse signal of the large-scale pulse power device 3 or an experimental object is transmitted to an analog signal input channel of the oscilloscope 2 and an input end of the synchronous trigger device 1 through a coaxial cable, and an external trigger channel of the oscilloscope 2 is connected to an output end of the synchronous trigger device 1 through a coaxial cable with equal length. When the large pulse power device 3 is in operation, tens or hundreds of oscilloscopes 2 are needed to monitor the pulse signals of the large pulse power device 3; to analyze the operation of a large pulse power device 3 and the development of experiments, all pulse data should have the same zero time in time, which requires that all oscilloscopes 2 start to acquire at the same time.
The invention discloses a high-precision self-calibration synchronous trigger device, which comprises a preprocessing circuit 11, a fan-out circuit 12, a reference channel 13, n paths of calibration channels 14, a logic OR circuit 15, a calibration signal circuit 16 and a calibration enable 17, wherein n is more than or equal to 2;
one input end of the preprocessing circuit 11 is used for connecting an external trigger input, and the output end is connected with the input end of the fan-out circuit 12 and used for generating n +1 paths of same square wave signals and providing the same square wave signals to the reference channel 13 and the n paths of calibration channels 14; the reference channel 13 includes a reference delay circuit 131 and a reference driving circuit 132 connected in sequence; the input end of the reference delay circuit 131 is connected with one output end of the fan-out circuit 12; the output end of the reference driving circuit 132 is used as a reference signal for providing a calibration reference signal for the n calibration channels 14;
each calibration channel comprises a calibration delay circuit 141, a calibration driving circuit 142, a comparison circuit 143 and a delay driving circuit 144; an input end of the calibration delay circuit 141 is connected to a corresponding output end of the fan-out circuit 12, and an output end thereof is connected to an input end of the calibration driving circuit 142; the output end of the calibration driving circuit 142 is used as a calibration driving signal of the corresponding calibration channel 14 for synchronously triggering the corresponding oscilloscope 2; the calibration driving signal is connected with the non-inverting input end of the comparison circuit 143, and the inverting input end of the comparison circuit 143 is connected with the reference signal; the output terminal of the comparison circuit 143 is connected to one input terminal of the delay driver circuit 144, and is also connected to the corresponding input terminal of the or circuit 15; the output end of the delay driving circuit 144 is connected to the other input end of the calibration delay circuit 141, and is used for controlling the output signal of the calibration delay circuit 141 to increase by one step; the output end of the logic or circuit 15 is connected with one input end of the calibration signal circuit 16; the output end of the calibration signal circuit 16 is connected to the other input end of the preprocessing circuit 11, and is used for providing a calibration signal source for the preprocessing circuit 11 during calibration; an output terminal of the calibration enable 7 is connected to another input terminal of the calibration signal circuit 16, and to another input terminals of the n delay driver circuits 144, for providing calibration enable signals.
In this embodiment, the preprocessing circuit 11 can realize the selection, discrimination, shaping, and holding of the pulse input signal of the large-scale pulse power device 3; the method comprises the following steps: first signal shaping: a high-pass filtering and hysteresis comparator mode is adopted, so that false triggering caused by signal interference is avoided; second comparison level adjustment: adjusting to a reasonable comparison level according to needs, and reducing local noise interference; the third pulse width forms: forming a square wave signal with a certain width by an RC time delay method; fourthly, the single square wave signal can be output after one or more trigger signal inputs are received and logical operation or conditional operation is adopted; fifthly, the trigger suppression function is realized, and repeated triggering in a short time is prevented; through the above five measures, the preprocessing circuit 11 can convert a signal with glitch into a square wave signal with a specified pulse width.
The input terminal of the fan-out circuit 12 is connected to the output terminal of the preprocessing circuit 11 for indiscriminately fanning out the square wave signal generated by the preprocessing circuit 11. The high-speed fan-out chip adopted by the invention can fan out through a one-stage or multi-stage fan-out structure, and the fan-out structures of all channels are the same so as to meet the requirement that all output signals are consistent in shaking; taking 64-channel output as an example, a two-stage fan-out structure can be selected, and the first stage selects 1: 8 fan-out structures, the second level chooses for use 1: 8, fan-out of the structure; the fan-out channels have small delay, the rising edge of the output square wave is fast, the jitter is small, and compared with the fan-out of a power divider, the fan-out of the high-speed chip has the characteristics of strong driving capability and fast output front edge under the same Vpp condition; if the power divider is used for fanning out 64 channels, the output voltage is only 1/64 of the input voltage; if the preprocessing circuit 11 outputs 2.4V, the fan-out signal is only 0.04V, the signal-to-noise ratio is low, and the requirement of multi-channel output cannot be met.
The reference delay circuit 131 is configured to implement broadening delay of a reference signal on the reference channel 13, where a value of the broadening delay is a fixed value and is not adjusted after leaving a factory; usually, a delay line + RC delay manner is adopted. The delay line can adopt PCB wiring, and the electrical length of the delay line ensures that a signal can be delayed by a specified value (usually 1 ns); the resistance R and the capacitance C of the time delay RC are fixed.
The reference driving circuit 132 is configured to output a reference signal; the reference signal broadening can be achieved by lowering the comparator comparison voltage: because the reference signal forms a charge-discharge waveform after being delayed by the RC of the reference delay circuit 131, the maximum width is 2 times the width of the reference signal; the reference signal is widened and then compared with the reference voltage, the output of square waves with different widths can be obtained by adjusting the value of the reference voltage, the purpose of widening the reference signal is to enable the width of the output signal of the reference driving circuit 132 to be not less than the time width of the output signal width of the calibration driving circuit 142 plus the step value of the output signal of the calibration driving circuit 142, so that at least one adjustment process is ensured when the calibration delay circuit 141 is adjusted, the width of the output signal of the reference driving circuit 132 completely covers the output signal of the calibration driving circuit 142, namely the logical relation of the comparison circuit 143 is met, if the reference channel is greater than the calibration channel, the output of the comparison circuit 143 is always zero, and one calibration is completed; taking the 64-channel synchronous trigger device 1 as an example, an RC integrating circuit is used for adjustment, wherein the R value of the resistor is fixed to be 20 Ω, the C value of the capacitor is 0.424pF to 13.33pF, and by adjusting the C value of the capacitor and matching with a signal output module, the delay adjustment of the calibration delay circuit 141 with the step length of 4.2ps to 133ps and the step length of 4.2ps can be realized.
The calibration delay circuit 141 is used for realizing the delay adjustment of the calibration channel square wave signal; the delay adjustment can be carried out by adopting an RC delay method, wherein one element parameter is unchanged, the other element parameter can be adjusted through a chip, and the time constant of the other element parameter is controlled to change so as to realize the fine adjustment of the delay time.
The calibration driver circuit 142 is used to implement signals whose output leading edge, output amplitude, and output impedance meet the trigger requirements. Comparing the calibration driving signal output by the calibration driving circuit 142 with the reference signal output by the reference driving circuit 132 to realize the synchronous output of n paths of calibration driving signals; the standard voltage sources of all the calibration channels are the same voltage source; taking the 64-channel synchronous trigger device 1 as an example, the output signal is positive, the output leading edge is 300ps, the output level is 3.3V, the output impedance is 50 Ω, and the calibration driving circuit 142 further includes a signal distribution function, and normally outputs when in normal operation; when calibration is performed, the output signal of the calibration driving circuit 142 may be fed back to the comparison circuit 143 for adjusting the delay of the calibration channel.
The comparison circuit 143 is configured to compare the "reference channel — calibration channel" and output a comparison result; the logic of the comparison circuit 143 is: when the reference signal output by the reference driving circuit 132 and the calibration driving signal output by the calibration driving circuit 142 satisfy the logical relationship of the comparison circuit 143, the comparison circuit 143 outputs a logical "0" (including that when the calibration driving signal output by the calibration channel 14 and the reference signal output by the reference channel 13 completely reach the comparison circuit 143 at the same time, the output logic of the comparison circuit 143 is satisfied, and the output signal of the comparison circuit 143 is "0"), the n-way comparison output is logically or-operated to obtain a logical control signal, and if the logical control signal is 0, the calibration of the reference signal and the n-way calibration driving signal is completed; and (3) closing the calibration enable 17, triggering the preprocessing circuit 11 by an external trigger input signal, outputting n paths of calibration driving signals by the square wave signal generated by the preprocessing circuit 11 through the fan-out circuit 12 and the n paths of calibration channels 14, synchronously triggering the oscilloscope 2, and simultaneously acquiring the output signal of the pulse power device 3 by the oscilloscope 2.
When the reference signal output by the reference driving circuit 132 and the calibration driving signal output by the calibration driving circuit 142 do not satisfy the logical relationship of the comparison circuit 143, and the comparison circuit 143 outputs a logical "1" (i.e. the calibration channel > the reference channel, as long as the calibration driving signal output by the calibration channel reaches the comparison circuit 143 before the reference signal output by the reference channel, the output logic of the comparison circuit 143 is not satisfied, and the output signal of the comparison circuit 143 will be a digital "1"), the delay driving circuit 144 increases a step length, and controls the calibration delay circuit 141 to perform delay adjustment (i.e. increase a step length value), and at the same time, the or circuit 15 triggers the calibration signal circuit 16 to give a calibration signal source again to the preprocessing circuit 11, and continues calibration until the reference signal output by the reference driving circuit 132 and the calibration driving signal output by the calibration driving circuit 142 satisfy the logical relationship of the comparison circuit 143, the comparison circuit 143 outputs a logic "0", performs logical or operation on the n-way comparison output to obtain a logic control signal, and if the logic control signal is 0, completes calibration of the reference signal and the n-way calibration driving signal; and (3) closing the calibration enable 17, triggering the preprocessing circuit 11 by an external trigger input signal, outputting n paths of calibration driving signals by the square wave signal generated by the preprocessing circuit 11 through the fan-out circuit 12 and the n paths of calibration channels 14, synchronously triggering the oscilloscope 2, and simultaneously acquiring the output signal of the pulse power device 3 by the oscilloscope 2.
Taking a high-speed comparator as an example, the calibration channel 14 is connected to the non-inverting terminal of the comparator, and the reference channel 13 is connected to the inverting terminal of the comparator; when the input signal does not arrive, the voltages of the calibration channel 14 and the reference channel 13 are both 0V, and the comparison result is 0V; as shown in fig. 3(a), the calibration signal source input signal triggers the preprocessing circuit 11, after fanning out by the fanning-out circuit 12, the square wave signal of the calibration signal source first appears in the calibration channel 14, so that the comparison result outputs a digital "1", the delay driving circuit 144 outputs a control signal to the calibration delay circuit 141, the output signal of the calibration delay circuit 141 is driven to perform delay adjustment (increase a step value), the comparison circuit 143 is controlled to trigger the logical or circuit 15, the logical or circuit 15 controls the calibration signal circuit 16 to give out a calibration signal source again until the reference signal and the n calibration driving signals satisfy the logical relationship of the comparison circuit 143, and the comparison circuit 143 outputs a logical "0", and calibration of the reference signal and the n calibration driving signals is completed; as shown in fig. 3(b), when the square wave signal of the calibration signal source first appears in the reference channel 13, the comparison result outputs a digital "0", and the calibration of the reference signal and the n paths of calibration driving signals is completed; and if the reference channel and the calibration channel are simultaneously output, the comparison result is always kept to be 0, and the calibration of the reference signal and the n paths of calibration driving signals is completed.
The delay driving circuit 144 is an adapter for the comparison circuit 143 and the calibration delay circuit 141, and is configured to monitor an output result of the comparison circuit 143 and generate a periodic pulse to increase a delay time of the calibration delay circuit 141 by a step value; the delay driver circuit 144 increases the delay time of the calibration delay circuit 141 by a step value every time it receives a "1" signal from the output of the comparator circuit 143.
The calibration signal circuit 16 is used for generating a calibration signal source, namely a single square wave signal, and is used for driving the preprocessing circuit 11 and subsequent circuits; when the calibration signal circuit 16 receives the trigger signal output by the calibration enable 17, a single square wave signal is also generated, and one-time calibration is realized.
A high-precision self-calibration synchronous triggering method is based on a high-precision self-calibration synchronous triggering device 1 and comprises the following steps:
step 2.1: turning on the calibration enable 17, the calibration signal circuit 16 sends a calibration signal source to the preprocessing circuit 11;
step 2.2: triggering a preprocessing circuit 11 to generate a preprocessing square wave, wherein the preprocessing square wave is fanned out n +1 paths of same square wave signals by a fan-out circuit 12 and respectively provided for a reference channel 13 and an n path of calibration channels 14;
step 2.3: the square wave signal of the reference channel 13 is widened by the reference delay circuit 131 and amplified by the reference driving circuit 132 to output a reference signal; the square wave signals of the n paths of calibration channels 14 are respectively delayed by the calibration delay circuit 141 and then output calibration delay signals, and then are amplified by the calibration driving circuit 142 and output n paths of calibration driving signals;
step 2.4: inputting the reference signals into the inverting input terminals of the comparison circuits 143, and inputting the n paths of calibration driving signals into the non-inverting input terminals of the corresponding comparison circuits 143 for comparison to obtain n paths of comparison outputs;
and simultaneously judging whether the comparison output of the n paths of calibration channels is 1:
if yes, the calibration delay signal output by the corresponding calibration delay circuit 141 is increased by a step value;
otherwise, the corresponding calibration channel 14 is calibrated;
step 2.5: carrying out logical OR operation on the n paths of comparison output to obtain a logical control signal, and judging whether the logical control signal is 1;
if the logic control signal is 1, the calibration signal circuit 16 sends a calibration signal source to the preprocessing circuit 11 again, and the step 2.2 is returned;
if the logic control signal is 0, finishing the calibration of the reference signal and the n paths of calibration driving signals, and executing the step 3;
And (3) closing the calibration enable 17, triggering the preprocessing circuit 11 by an external trigger input signal, outputting n paths of calibration driving signals by a square wave signal generated by the preprocessing circuit 11 through the fan-out circuit 12 and the n paths of calibration channels 14, synchronously triggering the oscilloscope 2 by the n paths of calibration driving signals, and simultaneously acquiring an output signal of the pulse power device 3 by the oscilloscope 2.
In order to better illustrate the technical solution of the present invention, this embodiment will illustrate the method, specifically as follows:
step 2.1: turning on the calibration enable 17, the calibration signal circuit 16 sends a calibration signal source to the preprocessing circuit 11;
step 2.2: triggering a preprocessing circuit 11 to generate 100ns preprocessed square waves, wherein the 100ns preprocessed square waves are fanned out 64 paths of same 100ns square wave signals by a fanout circuit 12 and are respectively provided for a reference channel 13 and an n-path calibration channel 14;
step 2.3: one 100ns square wave signal is widened by the reference delay circuit 131 and amplified by the reference driving circuit 132, and then a 102ns reference signal is output;
the other 63 paths of 100ns calibration driving signals are respectively delayed by 0ns through the calibration delay circuit 141, then calibration delay signals are output, and the 63 paths of 100ns calibration driving signals are output after the amplification processing of the calibration driving circuit 142;
step 2.4, inputting one path of 102ns reference signals into the inverting input end of the comparison circuit 143, and simultaneously inputting 63 paths of 100ns calibration driving signals into the non-inverting input end of the corresponding comparison circuit 143 for comparison to obtain 63 paths of comparison output;
meanwhile, whether the comparison output of the 63 calibration channels 14 is 1 is judged:
if yes, the calibration delay signal output by the corresponding calibration delay circuit 141 is increased by a step value;
otherwise, the corresponding calibration channel 14 is calibrated;
step 2.5: performing logical OR operation on the 63 paths of comparison output to obtain a logical control signal, and judging whether the logical control signal is 1;
if the logic control signal is 1, the calibration signal circuit 16 sends a calibration signal source to the preprocessing circuit 11 again, and the step 2.2 is returned;
if the logic control signal is 0, completing the calibration of one path of 102ns reference signal and 63 paths of 100ns calibration driving signals, and executing the step 3;
and 3, turning off the calibration enable 17, triggering the preprocessing circuit 11 by an external trigger input signal, outputting 63 paths of 100ns calibration driving signals by the square wave signal generated by the preprocessing circuit 11 through the fan-out circuit 12 and the 63 paths of calibration channels 14, synchronously triggering 63 oscilloscopes 2 by the 63 paths of 100ns calibration driving signals, and simultaneously acquiring the output signal of the pulse power device 3 by the 63 oscilloscopes 2.
Claims (7)
1. A high accuracy self calibration synchronization trigger device which characterized in that: the device comprises a preprocessing circuit (11), a fan-out circuit (12), a reference channel (13), n paths of calibration channels (14), a logic OR circuit (15), a calibration signal circuit (16) and a calibration enable circuit (17), wherein n is more than or equal to 2;
one input end of the preprocessing circuit (11) is used for being connected with an external trigger input, and the output end of the preprocessing circuit is connected with the input end of the fan-out circuit (12) and used for generating n +1 paths of same square wave signals to be supplied to a reference channel (13) and n paths of calibration channels (14);
the reference channel (13) comprises a reference delay circuit (131) and a reference driving circuit (132) which are connected in sequence; the input end of the reference delay circuit (131) is connected with one output end of the fan-out circuit (12); the output end of the reference driving circuit (132) is used as a reference signal and is used for providing a calibration reference signal for the n paths of calibration channels (14);
each calibration channel (14) comprises a calibration delay circuit (141), a calibration driving circuit (142), a comparison circuit (143) and a delay driving circuit (144);
one input end of the calibration delay circuit (141) is connected with the corresponding output end of the fan-out circuit (12), and the output end of the calibration delay circuit is connected with the input end of the calibration driving circuit (142); the output end of the calibration driving circuit (142) is used as a calibration driving signal of a corresponding calibration channel (14) and is used for synchronously triggering the corresponding oscilloscope (2);
the calibration driving signal is connected with a non-inverting input end of the comparison circuit (143), and an inverting input end of the comparison circuit (143) is connected with the reference signal; the output end of the comparison circuit (143) is connected with one input end of the delay driving circuit (144) and is simultaneously connected with the corresponding input end of the logic OR circuit (15);
the output end of the delay driving circuit (144) is connected with the other input end of the calibration delay circuit (141) and is used for controlling the output signal of the calibration delay circuit (141) to increase by a step value;
the output end of the logic OR circuit (15) is connected with one input end of the calibration signal circuit (16);
the output end of the calibration signal circuit (16) is connected with the other input end of the preprocessing circuit (11) and is used for providing a calibration signal source for the preprocessing circuit (11) during calibration;
the output end of the calibration enable (17) is connected with the other input end of the calibration signal circuit (16) and is simultaneously connected with the other input ends of the n delay driving circuits (144) for providing calibration enable signals.
2. A high precision self-calibrating synchronous trigger device according to claim 1, characterized in that: the output signal width of the reference driving circuit (132) is not less than the output signal width of the calibration driving circuit (132) and the step value of the output signal of the calibration driving circuit (142).
3. A high precision self-calibrating synchronous triggering device according to claim 1 or 2, characterized in that: the reference delay circuit (131) adopts a delay line + RC delay mode to realize broadening delay of a reference signal;
the calibration delay circuit (141) adopts an RC circuit.
4. A high precision self-calibrating synchronous trigger device according to claim 5, characterized in that: the fan-out circuit (12) includes one or more stages of identical fan-out structures.
5. A high-precision self-calibration synchronous triggering method is based on a high-precision self-calibration synchronous triggering device and is characterized by comprising the following steps:
step 1, setting n paths of calibration channels (14) to zero;
step 2, calibrating the n paths of calibration channels (14):
step 2.1: turning on a calibration enable (17), a calibration signal circuit (16) sends a calibration signal source to the preprocessing circuit (11);
step 2.2: triggering a preprocessing circuit (11) to generate a preprocessing square wave, wherein the preprocessing square wave is fanned out n +1 paths of same square wave signals by a fan-out circuit (12) and respectively provided for a reference channel (13) and n paths of calibration channels (14);
step 2.3: the square wave signal of the reference channel (13) is widened by a reference delay circuit (131) and amplified by a reference driving circuit (132) to output a reference signal; the square wave signals of the n paths of calibration channels (14) are respectively delayed by the calibration delay circuit (141) and then output calibration delay signals, and then the calibration delay signals are amplified by the calibration driving circuit (142) and then output n paths of calibration driving signals;
step 2.4: respectively inputting the reference signals into the inverting input ends of the comparison circuits (143), and simultaneously respectively inputting the n paths of calibration driving signals into the non-inverting input ends of the corresponding comparison circuits (143) for comparison to obtain n paths of comparison outputs;
and simultaneously judging whether the comparison output of the n paths of calibration channels is 1:
if yes, the calibration delay signal output by the corresponding calibration delay circuit (141) is increased by a step value;
otherwise, the corresponding calibration channel (14) is calibrated;
step 2.5: carrying out logical OR operation on the n paths of comparison output to obtain a logical control signal, and judging whether the logical control signal is 1;
if yes, the calibration signal circuit (16) sends a calibration signal source to the preprocessing circuit (11) again, and the step 2.2 is returned;
if not, finishing the calibration of the reference signal and the n paths of calibration driving signals, and executing the step 3;
step 3, synchronous trigger oscillograph (2)
And (2) closing the calibration enable (17), triggering the preprocessing circuit (11) by an external trigger input signal, outputting n paths of calibration driving signals by a square wave signal generated by the preprocessing circuit (11) through the fan-out circuit (12) and the n paths of calibration channels (14), synchronously triggering the oscilloscope (2) by the n paths of calibration driving signals, and simultaneously acquiring an output signal of the pulse power device (3) by the oscilloscope (2).
6. The high-precision self-calibration synchronous triggering method according to claim 5, characterized in that: the fan-out circuit (12) may fan out through one or more stages of the same fan-out structure.
7. A high-precision self-calibration synchronous triggering method according to claim 5 or 6, characterized in that: in step 2.5, the calibration delay circuit (141) saves the delay adjustment parameter.
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