CN1713155A

CN1713155A - PCI test card and test thereof

Info

Publication number: CN1713155A
Application number: CN 200410025337
Authority: CN
Inventors: 杜春艳; 张�林; 王玉杰; 周传国
Original assignee: Shanghai Huanda Computer Technology Co Ltd
Current assignee: Shanghai Huanda Computer Technology Co Ltd
Priority date: 2004-06-22
Filing date: 2004-06-22
Publication date: 2005-12-28
Anticipated expiration: 2024-06-22
Also published as: CN100583052C

Abstract

A PCI test card is featured as using signal generator to create signal required by test, outputting signal after it is delayed by delay gate array, using display unit to display numbers of gate delay passed by signal currently, and controlling signal generation and numbers of passed gate delay by control circuit.

Description

PCI test card and method of testing thereof

Technical field

The present invention relates to computing machine peripheral equipment field, particularly relevant a kind of PCI test card and method of testing thereof.

Background technology

In the current Circuits System (as mainboard), because the difference of chip selection, design philosophy and device difference, be different with the tolerance limit of retention time the Time Created of each Circuits System signal, and these parameters have important directive significance for the stability of weighing system.

Existing P CI (Peripheral component interconnection) test card is often tested at the PCI agreement, measure pci signal and whether satisfy agreement, and can on oscillograph, demonstrate the situation of change of signal, as the batch testing device in No. the 02117679th, the Chinese patent.Perhaps as test chart, as the single step error correction device in No. the 00134858th, the Chinese patent, whether the investigation system moves when power-on self-test normally.These methods for designing all can not detect the tolerance limit of some time parameter of pci signal.

For the tolerance limit of the Time Created and retention time of under existence conditions, measuring each Circuits System signal, generally adopt the oscillograph test, and its waveform signal is understood calculating, draw the time tolerance parameter.But this need of work has special technician to calculate the deciphering waveform, and in general the staff to read oscillographic waveform accurate inadequately, if adopt the oscillograph of advanced high precision then the price comparison costliness, adopt the human interpretation waveform to calculate the method for Time Created, retention time tolerance limit in a word at present, waste time and energy and cost dearly.

Summary of the invention

The object of the present invention is to provide a kind of PCI test card,, solve prior art and can't directly measure the problem of pci signal time to overcome above-mentioned the deficiencies in the prior art.

For achieving the above object, the invention provides a kind of PCI test card, it is characterized in that it comprises: signal generator, time-delay gate array, control circuit and display unit, wherein signal generator produces the required signal of test, the time-delay gate array carries out signal exporting after the time-delay of different gate delay numbers, display unit shows the number of the gate delay of current signal institute warp, the generation of control circuit control signal and through the number of gate delay.

Wherein, the required signal of test of described signal generator generation comprises clock signal and test signal; Control circuit can be controlled by the computer system that installs application software additional by the user; Display unit can be converted into the number of gate delay time delay and the direct display delay time; Described signal generator and control circuit are made of programmable logic device (PLD), and this programmable logic device (PLD) is FPGA (Field programmable Gates Array, a field programmable gate array); Described time-delay gate array is made of CPLD (Complex programmableLogic Device, CPLD); Described display unit is LED (light-emitting diode, a light emitting diode).

Another object of the present invention is to provide a kind of method of testing of pci system, solve prior art and can't directly measure the problem of the Time Created of pci signal.

For achieving the above object, the method for testing that the invention provides a kind of pci system may further comprise the steps: a. provides test signal and clock signal; B. add gate delay to test signal, increase a gate delay, at every turn till test signal is invalid; The number of the gate delay of the test signal institute warp when c. tracer signal is invalid.

The time that the number of the gate delay of the test signal institute warp when further, utilizing test signal invalid multiply by each gate delay can calculate tolerance limit Time Created of signal; Calculate test signal point ineffective time apart from the time period between the next rising edge of clock signal, income value is the minimum Time Created of signal.

A further object of the present invention is to provide a kind of method of testing of pci system, solves prior art and can't directly measure the problem of the retention time of pci signal.

For achieving the above object, the invention provides a kind of method of testing of pci system, may further comprise the steps: a. provides test signal and clock signal; Add gate delay b. for the pci clock signal, increase a gate delay, at every turn till test signal is invalid; C. write down the number of the gate delay of the clock signal institute warp of test signal when invalid.

The time that the number of the gate delay of the clock signal institute warp when further, utilizing test signal invalid multiply by each gate delay can calculate the retention time tolerance limit of signal; Calculate test signal point ineffective time apart from the time period between the negative edge of current test signal, income value is the minimum hold time of signal.

The present invention is by carrying out tolerance limit and minimum Time Created and the minimum hold time of gate delay with the Time Created that records signal and retention time to signal.The present invention does not need special technician's operation, and measuring accuracy is higher, and the result need not complicated deciphering and calculates, and can read from instrument, thereby have higher testing efficiency.In addition, test card according to the present invention is simple in structure, has preferable reliability, and equipment price is also relatively more cheap.

The present invention is further illustrated below in conjunction with accompanying drawing and embodiment.

Description of drawings

Fig. 1 is the structural representation of one embodiment of the present of invention.

Fig. 2 is the structural representation of the time-delay gate array of one embodiment of the present of invention.

Fig. 3 is the test philosophy synoptic diagram of tolerance limit Time Created.

Fig. 4 is the test philosophy synoptic diagram of retention time tolerance limit.

Embodiment

Relevant detailed description of the present invention and technology contents, existing as follows with regard to accompanying drawings: at first consult Fig. 1, Fig. 1 is the structural representation of one embodiment of the present of invention.PCI test card in the present embodiment, signal generator and control circuit are made of a slice FPGA, the programmable logic device (CPLD) that employing has the fixed gate delay time gate array that is used as delaying time carries out signal exporting after the time-delay of different gate delay numbers, and display unit is a slice LED.This PCI test card is inserted in the PCI slot of computer system in use.The user can control FPGA by the application program in the computer system and produce test required clock signal and test signal, the suitable PCI equipment of FPGA here, another function of FPGA is to trigger the gate delay function of CPLD, and steering order CPLD is to the time-delay of signal.Display unit shows the number of the gate delay of current signal institute warp, also the number of gate delay can be converted into time delay and the direct display delay time.

The CPLD that is adopted in the present embodiment has multichannel output as shown in Figure 2, and each road is provided with the gate delay of respective number, has a gate delay as the first via, and the second the tunnel has two gate delays, has N gate delay until the N road.The input end of CPLD has a selector switch that is subjected to the control of FPGA, can select to import through a certain road or the output of a few road.

In test, the tester can come the enabling gate delay function by application program, and the PC system informs that through CPLD FPGA begins to carry out the gate delay test by pci bus.FPGA informs that on the one hand CPLD begins to enable gate delay, begins on the other hand ceaselessly to send data to the PC system.Application program can postpone a door to measured signal earlier, increases one by one one by one afterwards.LED can show the number of current gate delay.When the time of measured signal tolerance limit during less than the requiring of PCI agreement, system can work as machine automatically, and pci bus quits work.LED shows the number of gate delay when machine always.

Present embodiment satisfies the PCI agreement with the hardware description language programming in FPGA, so the pci card of design can directly be inserted in the PCI slot, signal is sent by FPGA, realize gate delay through CPLD, under the situation of test signal delay or clock signal delay test signal has appearred by effectively becoming invalid situation, operating system is worked as machine, has just measured corresponding Time Created of tolerance limit and retention time tolerance limit.

Followingly according to the test philosophy synoptic diagram method of testing provided by the invention is introduced, analyzes: at first see also Fig. 3, Fig. 3 is the test philosophy synoptic diagram of tolerance limit Time Created.In the process of test tolerance limit Time Created, the fixed clock signal, the test signal that allows FPGA produce realizes postponing through the door of CPLD, when the gate delay in CPLD reaches certain number, test signal is invalid by effectively becoming at rising edge clock, it is effective at clock signal clk rising edge as test signal testsignal is shown respectively among Fig. 3 through 1 gate delay, 2 gate delays are still effective at clock signal clk rising edge, up to the appearance of n gate delay of process in the rising edge invalid situation of clock signal clk, the test signal of this moment is exactly an invalid signals.So, the rising edge of invalid signals is exactly the minimum Time Created of signal up to the scope of the rising edge of clock signal clk, and test signal never through the original signal of gate delay to the time that invalid signals occurs be exactly the time delay of door among the CPLD, just Time Created tolerance limit.That is to say that Time Created, tolerance limit equaled the time that the number of the gate delay of the test signal institute warp of test signal when invalid multiply by each gate delay.Like this, if know invalid test signal the number of gate delay of process, just measured tolerance limit Time Created of signal, also just correspondingly measured minimum Time Created.

See also Fig. 4, Fig. 4 is the test philosophy synoptic diagram of retention time tolerance limit.When measurement retention time tolerance limit, the fixing test signal, the enable clock signal is realized postponing through the door of CPLD, and is when the gate delay in CPLD reaches certain number, invalid by effectively becoming in the test signal of certain rising edge clock.Clock signal is shown through 1 gate delay among Fig. 4 respectively, rising edge test signal at clock signal clk is effective, clock signal is still effective in the rising edge test signal of clock signal clk through 2 gate delays, it is invalid to record test signal through n gate delay at the rising edge of clock signal clk up to clock signal, the time that the number of the gate delay of the clock signal institute warp when at this moment, utilizing test signal invalid multiply by each gate delay can calculate the retention time tolerance limit of signal.Calculate test signal point ineffective time apart from the time period between the negative edge of this test signal, income value is the minimum hold time of signal.

The above introduction only is preferred embodiment of the present invention, can not limit scope of the invention process with this.The variation that is equal to that those skilled in the art in the present technique field are done according to the present invention, for example each step among the above embodiment is made up, or add components and parts beyond the components and parts that the present invention mentions, testing process is done equivalent variations or apparent and easy to know derivation, and the improvement known of those skilled in that art, all should still belong to the scope that patent of the present invention contains.

Claims

1, a kind of PCI test card, it is characterized in that it comprises: signal generator, time-delay gate array, control circuit and display unit, wherein signal generator produces the required signal of test, the time-delay gate array comprises a plurality of gate delays, wherein single gate delay is to one time delay of signal lag, display unit shows the number of the gate delay of current signal institute warp, the generation of control circuit control signal and through the number of gate delay.

2, PCI test card as claimed in claim 1 is characterized in that the required signal of test that described signal generator produces comprises clock signal and test signal.

3, PCI test card as claimed in claim 1 is characterized in that control circuit can be controlled by the computer system that installs application program additional by the user.

4, PCI test card as claimed in claim 1 is characterized in that described display unit can multiply by the number of gate delay time delay of each gate delay and direct display delay time.

5, PCI test card as claimed in claim 1 or 2 is characterized in that described signal generator and control circuit are made of programmable logic device (PLD).

6, PCI test card as claimed in claim 5 is characterized in that described programmable logic device (PLD) is FPGA.

7, PCI test card as claimed in claim 1 is characterized in that described time-delay gate array is made of CPLD.

8, as claim 1 or 4 described PCI test cards, it is characterized in that described display unit is LED.

9, a kind of method of testing of pci system: it is characterized in that may further comprise the steps:

A. provide test signal and clock signal;

B. add gate delay to test signal, increase a gate delay, at every turn till test signal is invalid;

C. write down the number of the gate delay of the test signal institute warp of test signal when invalid.

10, the time that the method for testing of pci system as claimed in claim 9, the number of the gate delay of the test signal institute warp when it is characterized in that utilizing test signal invalid multiply by each gate delay can calculate tolerance limit Time Created of signal.

11, the method for testing of pci system as claimed in claim 9 is characterized in that calculating test signal point ineffective time apart from the time period between the next rising edge of clock signal, and income value is the minimum Time Created of signal.

12, a kind of method of testing of pci system is characterized in that may further comprise the steps:

A. provide test signal and clock signal;

Add gate delay b. for the pci clock signal, increase a gate delay, at every turn till test signal is invalid;

C. write down the number of the gate delay of the clock signal institute warp of test signal when invalid.

13, the time that the method for testing of pci system as claimed in claim 12, the number of the gate delay of the clock signal institute warp when it is characterized in that utilizing test signal invalid multiply by each gate delay can calculate the retention time tolerance limit of signal.

14, the method for testing of pci system as claimed in claim 12 is characterized in that calculating test signal point ineffective time apart from the negative edge of current test signal or the time period between the rising edge, and income value is the minimum hold time of signal.