JP2006329735A - Method and device for measuring time interval - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for measuring time intervals capable of extremely reducing repeated processing and performing quick measurement. <P>SOLUTION: The measurement method or the like solving the problems includes a step of generating a clock signal edge bit stream indicating the timing of a signal edge of a clock signal by sampling the clock signal with a sampling frequency at an integer multiple of the frequency of the clock signal, a step of acquiring a quotient of the clock signal edge bit stream by a half period of the clock signal and a data signal edge bit stream corresponding to the clock signal edge bit stream by the half period when generating the data signal edge bit stream indicating the timing of the signal edge of the data signal by sampling the data signal at the timing the same as the sampling, and a step of acquiring the time interval by the product of a logarithm of quotient to the base of two and the sampling frequency. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a time interval measuring method and apparatus, and more particularly to a time interval measuring method and apparatus for measuring a time difference between a clock signal and a data signal of a device that outputs a data signal in synchronization with a clock signal.

  In digital circuits composed of digital devices such as MPUs, memories, and analog / digital converters, it is common to input and output data based on a common clock signal in order to facilitate data exchange between devices. It is. In data input / output, the output device first sets a data value on the data signal line, and then the input device reads the data value at the signal edge of the clock signal. At this time, if the signal edge of the clock signal rises (or falls) before the data value of the data signal line is stabilized, erroneous data may be delivered. For this reason, as shown in FIG. 2, it is common to design such that a signal edge rises (or falls) after a predetermined time has elapsed from the start of data value setting. This time is called setup time.

  For the setup time, a standard value and an error range are provided in the specifications for each device, and the circuit designer performs circuit design based on the specifications. For this reason, if the device deviates from the specification value, data cannot be exchanged stably, and the device will not operate as intended by the designer. In order to eliminate such defective devices in advance, a setup time test may be performed in the manufacturing process.

  The setup time can be measured as a time difference between signal edges of the clock signal and the data signal. The above-mentioned non-defective product determination can be performed by determining whether or not the measured value is within the specification range. For example, in a DDR (Double Data Rate) -SDRAM, a non-defective product is determined by measuring a setup time for each memory cell and testing whether the average value and variation are within a predetermined range.

  By the way, as one of the signal edge time interval measurement methods, there is a time interval measurement using oversampling as disclosed in Patent Document 1 and Patent Document 2. In this method, first, bit values (0 or 1) of a plurality of digital signals under measurement whose time differences are measured are sampled at a sampling frequency higher than that of the signals under measurement to create a bit stream. Next, the timing of changing the bit value is searched to determine the position of the signal edge. Finally, there is a method in which a time difference is measured from the deviation of the signal edge positions of a plurality of signals under measurement and the sampling frequency.

JP 2002-196053 A JP 2004-127455 A

  By the way, in the time interval measurement using the oversampling described above, search processing is required in two stages, that is, a stage where a signal edge is detected from a bit stream and a stage where a signal edge position shift between signals under measurement is obtained. That is, in the stage of detecting a signal edge, the value of the bit stream is sequentially compared from the first bit of the bit stream, and search processing for obtaining the position of the signal edge where the bit value changes is performed. Further, at the stage of obtaining the shift of the signal edge position, a search process is required for specifying the position of the signal edge of the second signal under measurement corresponding to the signal edge of the first signal under measurement serving as a reference. Since these search processes repeatedly execute the same process many times, a very long processing time is required. This increase in processing time leads to an increase in measurement time. Therefore, a time interval measurement method that does not involve such a search process has been demanded.

  The problem described above is a measurement method for measuring a time interval between a signal edge of the clock signal and a signal edge of the data signal of a device that outputs a data signal in synchronization with the clock signal, and the clock signal is A first step of sampling at a sampling frequency that is an integer multiple of the frequency of the clock signal to generate a clock signal edge bit stream that indicates the timing of the signal edge of the clock signal, and the same sampling as in the first step A second step of sampling the data signal at a timing to generate a data signal edge bit stream indicating the timing of the signal edge of the data signal; and the clock signal edge bit stream corresponding to a half cycle of the clock signal And the clock signal error for the half cycle. A third step of obtaining a quotient of the data signal edge bit stream corresponding to a dibit stream, and a fourth step of obtaining the time interval from a product of a logarithm with the quotient of 2 and the sampling frequency, It is solved by a measurement method characterized by including the above, an apparatus using the same, and the like.

  Repetitive processing in time interval measurement is greatly reduced, and quick measurement is possible.

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic configuration diagram of a time interval measuring apparatus 10 according to the present invention. The time interval measuring apparatus 10 includes a sampling signal oscillator 11 that oscillates a sampling signal 14C that determines the sampling timing of the signals under measurement 14A and 14B, and a sampler 12 that samples the signals under measurement 14A and 14B based on the sampling signal 14C. , The information processing device 13 that processes the sampling data to obtain the time interval and the control device 15 that controls the operation of the time interval measurement device 10. The sampler 12 is connected to the sampling signal oscillator 11 and the information processing device 13 through a data bus. The control device 15 is connected to the sampling signal oscillator 11, the sampler 12, and the information processing device 13 and controls each operation. The information processing apparatus 13 includes a microprocessor (MPU) 13A and a memory 13B. Further, the control device 15 has a computer function and incorporates a hard disk as a recording medium. The hard disk stores a program for causing the time interval measurement method to function on a computer.

  The sampler 12 receives a data signal 14B from the device under measurement 21 and a clock signal 14A for determining the data input / output timing of the device under measurement 21 from the clock signal oscillator 20 from the outside of the apparatus. When the clock signal 14A is oscillated inside the device 21, the device 21 is configured to supply the clock signal 14A and the data signal 14B to the sampler 12.

  Moreover, in the time interval measuring device 10 of the present embodiment, the control device 15 is provided separately from the information processing device 13, but the two do not necessarily have different configurations. For example, the control program for the time interval measurement method may be stored in the memory 13B of the information processing apparatus 13, and the sampling signal oscillator 11 and the sampler 12 may be controlled by executing the program by the MPU 13A. .

  Next, the operation of the time interval measuring apparatus 10 will be described in detail with reference to the schematic configuration diagram of FIG. 1 and the operation flowchart of FIG. In the following description, an example of measurement of the setup time (measurement of the signal time interval between the clock signal 14A and the data signal 14B) of a DDR-SRAM whose operating frequency (the oscillation frequency of the clock signal 14A) is 250 MHz will be described.

  First, the control device 15 sets the oscillation frequency of the sampling signal oscillator 11 to a frequency that is an integral multiple of the clock signal 14A (step 30). In the present embodiment, the sampling signal 14C is set to 4 GHz (period 250 ps), which is 16 times the frequency 250 Mz of the clock signal 14A. Next, the sampler 12 repeatedly samples the clock signal 14A and the data signal 14B at a rate of one sampling for each period of the sampling signal 14C, and stores the sampling value in the memory 13B. At this time, the sampling number is an integral multiple of the frequency ratio between the clock signal 14A and the sampling signal 14C. In this embodiment, since the frequency ratio is 16, it is sufficient to perform at least 16 samplings. However, in order to ensure measurement accuracy, an average value is obtained by taking a sampling number several to several tens of times the frequency ratio. Is desirable. In this embodiment, the number of samplings was set to 80, which is 5 times the frequency ratio. At this time, the data sequence of the sampling values stored in the memory 13B is called a bit stream. In this specification, the bit stream of the clock signal 14A is called a clock signal bit stream, and the bit stream of the data signal 14B is called a data signal bit stream.

  Next, the information processing device 13 calculates the time interval between the clock signal 14A and the data signal 14B, that is, the setup time, from the sampling data (clock signal bit stream and data signal bit stream) stored in the memory 13B. The control device 15 performs control. This calculation is performed in the following steps.

  First, the data of half the frequency ratio is acquired from the beginning of the sampling data. In this embodiment, since the frequency ratio is 16, the first 8 bits are obtained from the clock signal bit stream and the data signal bit stream stored in the memory 13B (step 32). The acquired 8-bit clock signal bit stream includes one signal edge (rising or falling). Such a signal edge can be detected by capturing the timing at which the bit value changes from 0 to 1 or from 1 to 0. However, if the value of each bit is sequentially searched from the beginning of the bit stream, processing time is required.

  Therefore, by taking exclusive OR (EXOR) of the acquired bit stream and the delayed bit stream obtained by shifting the bit stream by 1 bit, the signal edge bit is set to 1 and the other bits are set to 0. An edge bit stream is generated (step 33). For example, as shown in FIG. 5, when the clock signal bit stream is 00111111, the delayed clock signal bit stream is 00011111, the exclusive OR (EXOR) of the two is 00100000, and the bit value is 3 from the beginning from 0 to 1. A clock signal edge bit stream in which only the value of the bit of the bit becomes 1 and the value of the other bits becomes 0 is generated.

  Similarly, the data signal edge bit stream is generated by taking the exclusive OR (EXOR) with the delayed data signal bit stream shifted by 1 bit in the data signal bit stream acquired in step 32 as well. The data signal is not a signal that periodically changes like a clock signal. Therefore, when the data value is the same as the previous data value, there is no signal edge because the signal does not change, and the values of all the bits of the data signal edge bit stream are zero. In this case, the time interval between the signal edge of the clock signal and the signal edge of the data signal cannot be calculated. Therefore, before the calculation process, the obtained 8-bit data signal edge bit stream is regarded as an 8-digit binary number, and it is determined whether or not the value is 0, thereby determining the presence or absence of a signal edge. (Step 34). If it is 0, it is determined that there is no signal edge, and the next process (step 37) is performed without measuring the time difference.

  When a signal edge exists in the acquired 8-bit data signal bit stream, the clock signal edge bit stream and the data signal edge bit stream are each regarded as an 8-digit binary number, and the data signal edge bit stream is converted into a clock signal. A quotient is obtained by dividing by the edge bitstream, and a logarithm with the obtained quotient as the base is taken (step 35). As a result, it is possible to determine how many bits the signal edge of the clock signal edge bitstream is shifted from the signal edge of the data signal edge bitstream without performing a search process. For example, when the clock signal edge bit stream is 00100000 and the data signal edge bit stream is 10000000, the calculation is as follows.

  Since the sampling data is data sampled with a sampling signal having a period of 250 ps, the time interval between the clock signal and the signal edge of the data signal (setup time) is obtained by obtaining the product of the deviation amount of the signal edge and the sampling period (250 ps). ) Can be obtained (step 36). For example, when the deviation amount is 2, the time interval is 2 × 250 ps = 500 ps.

  Although the time interval can be obtained by the above processing, in the device test, the data value output from the device is generally confirmed together with the measurement of the setup time. In addition to the time interval measurement of the signal edge, the data value is also acquired (step 37). As shown in FIG. 6, the data value is acquired by calculating the logical product of the clock signal edge bit stream and the data signal bit stream, and determining whether the logical product is 0 by taking the logical product as an 8-digit binary number. Do. When the data value output from the device 21 is 1, since the value of the bit of the data signal sampled simultaneously with the signal edge of the clock signal is 1, the logical product does not become 0. On the other hand, when the data value output from the device 21 is 0, all bits of the logical product are 0. By such a zero determination of the logical product, the data value output from the device 21 can be obtained at a higher speed than the bit value of the data signal bit stream corresponding to the signal edge is obtained by the search process. The acquired data value is stored in the memory 13B.

  With the operations from step 32 to step 37, the signal edge measurement for 8 bits (clock signal half cycle) is completed. Similar processing is repeated until there is no unprocessed bit stream in the memory 13B (step 38). In this embodiment, since 80 samplings are performed, the signal edge time interval measurement and data value acquisition processing from step 32 to step 37 is repeated 10 times. Finally, the average value and variance (variation) of the measured signal edge time interval are calculated, and the setup time measurement for one memory cell is completed (step 39).

  FIG. 4 shows an example of processing results up to the third repetition. In the first repetition (first 8 bits, the first half cycle of the clock signal), the signal edge of the clock signal is the third bit and the signal edge of the data signal is the first bit, so the logarithm of the quotient of the signal edge bit stream is 2 and the signal edge time interval is 500 ps. In the second iteration, since the data signal does not change, all the bits of the data signal edge bit stream become 0. For this reason, it is determined that there is no signal edge, and time interval measurement is not performed. In the third iteration, since the signal edge of the clock signal is the third bit and the signal edge of the data signal is the second bit, the logarithm of the quotient of the signal edge bit stream is 1, and the signal edge time interval is 250 ps.

  Since the DDR-SRAM has a plurality of memory cells (may be a memory cell for pass / fail inspection), the time interval measurement described above is repeated for each memory cell, and the setup time of the DDR-SRAM is determined from the result. Is determined to be within the specification. Further, by comparing the data value acquired in step 37 with the data value written in the SRAM before performing the measurement described in the present embodiment, it is possible to determine whether the data is correctly written / read out. .

  Although the technical idea according to the present invention has been described in detail with reference to specific embodiments, various changes and modifications can be made by those skilled in the art to which the present invention belongs without departing from the spirit and scope of the claims. It is clear that can be added. For example, the time interval measurement method according to the present invention is not limited to the DDR-SRAM setup time measurement, and is a digital device that outputs a data signal in synchronization with a clock signal, such as an analog / digital converter, an MPU, or a communication interface device. It can be widely used as a method for measuring the time interval between signal edges of a clock signal and a data signal.

It is a schematic block diagram of the time interval measuring apparatus which concerns on one Example of this invention. It is explanatory drawing of the setup time of DDR-SRAM. It is an operation | movement flowchart of the time interval measuring apparatus which concerns on one Example of this invention. It is explanatory drawing of the time interval measurement which concerns on one Example of this invention. It is explanatory drawing of the calculation method of a clock signal edge bit stream. It is explanatory drawing of the calculation method of a data value.

Explanation of symbols

10 Time Interval Measurement Device 11 Sampling Signal Oscillator 12 Sampler 13 Information Processing Device 14A Clock Signal 14B Data Signal 21 Device

Claims (6)

A device for outputting a data signal in synchronization with a clock signal, a measurement method for measuring a time interval between a signal edge of the clock signal and a signal edge of the data signal,
Sampling the clock signal at a sampling frequency that is an integer multiple of the frequency of the clock signal to generate a clock signal edge bitstream that indicates the timing of the signal edge of the clock signal;
A second step of sampling the data signal at the same timing as the sampling of the first step to generate a data signal edge bitstream indicating the timing of the signal edge of the data signal;
A third step of obtaining a quotient of the clock signal edge bit stream for a half cycle of the clock signal and the data signal edge bit stream corresponding to the clock signal edge bit stream for the half cycle;
And a fourth step of obtaining the time interval from the product of the logarithm of the quotient of 2 and the sampling frequency. The first step comprises:
Sampling the clock signal at the sampling frequency to generate a clock signal bitstream;
A sixth step of generating the clock signal edge bitstream by obtaining an exclusive OR of the clock signal bitstream and a delayed clock signal bitstream obtained by shifting the clock signal bitstream by 1 bit; And the second step comprises:
A seventh step of sampling the data signal at the sampling frequency to generate a data signal bitstream;
And an eighth step of generating the data signal edge bitstream by obtaining an exclusive OR of the data signal bitstream and a delayed data signal bitstream obtained by shifting the data signal bitstream by 1 bit. The measurement method according to claim 1. The measurement method according to claim 1 or 2, further comprising:
The method according to claim 1, further comprising: determining a data value output from the device from a value of a bit of the data signal edge bitstream corresponding to an edge position of the clock signal edge bitstream. 2. The measuring method according to 2.   The program for functioning the measuring method in any one of Claim 1 to 3 with a computer.   A computer-readable recording medium on which the program according to claim 4 is recorded. A measuring device for measuring a time interval between a signal edge of the clock signal and a signal edge of the data signal of a device that outputs a data signal in synchronization with a clock signal,
A signal oscillator for oscillating a sampling signal having a frequency that is an integral multiple of the clock signal;
Sampling means for sampling the clock signal and the data signal based on the timing of the sampling signal to generate respective clock signal bit streams and data signal bit streams;
Generating a clock signal edge bit stream and a data signal edge bit stream indicating the signal edge position of each signal from the clock signal bit stream and the data signal bit stream for a predetermined half period of the clock signal; and And an information processing means for determining the time interval from the product of the logarithm of the quotient of the clock signal edge bit stream and the data signal edge bit stream, and the sampling frequency.

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