CN103676622A - High-precision method and device for measuring interval between positive time and negative time - Google Patents
High-precision method and device for measuring interval between positive time and negative time Download PDFInfo
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- CN103676622A CN103676622A CN201310512907.1A CN201310512907A CN103676622A CN 103676622 A CN103676622 A CN 103676622A CN 201310512907 A CN201310512907 A CN 201310512907A CN 103676622 A CN103676622 A CN 103676622A
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Abstract
The invention provides a high-precision method and device for measuring an interval between positive time and negative time. The device comprises a signal shaping and measuring gate extracting unit, a synchronization and interpolation unit, a clock counting unit, a storage unit and a data processing unit, wherein the signal shaping and measuring gate extracting unit, the synchronization and interpolation unit, the clock counting unit, the storage unit and the data processing unit are in connection with one another and in communication with one another. The signal shaping and measuring gate extracting unit conducts comparing and shaping on input signals according to a trigger level, converts measured signals into ECL level signals, and extracts gate signals corresponding to the measured signals through an ECL trigger. The synchronization and interpolation unit samples the two routes of gate signals through a counting clock. By means of the scheme, various types of signal input can be achieved, and the wide input dynamic range can be supported; a channel circuit is obtained through a high-speed ECL device, the channel bandwidth is large, narrow-pulse measurement can be achieved, the minimum measurable pulse width can reach 2.5ns, and the measurement resolution ratio can reach 40ps.
Description
Technical field
The invention belongs to positive and negative time interval measurement technical field, in particular a kind of high-precision positive and negative time interval measurement method and device.
Background technology
High-precision time interval measurement technology is widely used in the fields such as satellite navigation, radar fix, laser ranging, nuclear physics detecting and time and frequency measurement.One of NAS, using one of its important symbol as the national defense force of assessment, all can hold chronometer time and time interval measurement technical conferences every year, and the science and technology that must greatly develop it as country.The time interval measurement method of current widespread use have pulse counting method, analog interpolation, lag line interpolation method, vernier method and time m-amplitude transformation approach.The measuring accuracy of pulse counting method determines by step-by-step counting clock, and measuring error is ± 1 clock period, in order to improve measuring accuracy, need to correspondingly improve counting clock frequency.With current mature technology level, the highest 2～3GHz that can only work of counting clock frequency, time resolution can only reach 500ps left and right like this, far can not meet the requirement to time interval measurement precision in most situation.Analog interpolation is to improve measuring accuracy based on burst pulse expansion technique, can cause the increase of Measuring Time after pulse strenching, and the single measurement time needs hundreds of more than nanosecond at least, so the method occasion of being not suitable for measuring speed to have relatively high expectations.The most general method of high precision time interval measurement field application is at present latter three kinds, and its time interval measurement precision can reach tens psecs.
Lag line can be divided into two kinds of tapped delay line and differential delay line, and differential delay line can realize higher measuring accuracy compared with tapped delay line, but consumption of natural resource is also more.There is large quantity research this kind of method successfully to be realized in FPGA, utilize look-up table, carry chain and the cascade chain of FPGA inside as delay cell, can realize the measuring accuracy of 100ps left and right.Because the delay unit of FPGA inside is subject to the impact of temperature and supply voltage larger, its environmental suitability is very poor, need to compensate in a large number and calibrate to ensure its measuring accuracy, thereby its commercial value is not too remarkable at present in practical process.Vernier method and time the m-amplitude transformation approach existing precedent that is successfully applied to commercial testing tool, for example the universal frequency meter 53230A of Agilent company development utilizes vernier method to realize the time measurement resolution of 20ps, the time interval of Stanford University's development when tester SR620 utilizes m-amplitude transformation approach also reached the time measurement resolution of 20ps.In order to realize high time measurement resolution, these two kinds of methods are had relatively high expectations to processing technology, and cost of manufacture is also more expensive, just to the higher occasion of time interval measurement index request, are using more.The present invention utilizes general integrated device to design a high-precision time interval measurement device, has not only obtained the time measurement resolution of 40ps, and cost of manufacture is lower, to realize threshold not high yet, has higher actual promotional value.
The time interval is for describing an event with respect to the leading degree of another Time To Event, measuring by time value.When reference event occurs formerly, gained time interval measurement value is for just; Otherwise time interval measurement value is for negative.The sequencing that reference event and observation event occur is unknown sometimes, when this situation is carried out to time interval measurement, just need to use positive and negative time interval measurement.The instrument at present with positive and negative time interval measurement function has a lot, and the most representative on implementation is the frequency time compartment analysis instrument HP5370 of Hewlett-Packard, its positive and negative time interval measurement realize theory diagram as shown in Figure 1.Suppose that event 1 is for reference event, between event 1 and event 2, as shown in Figure 2, its principle of work is as follows for relation: due to before reference event occurs in, the detection polarity that extraction unit 101 is exported, for just, represents with high level; Rising edge by event 1 and event 2 synchronously produces measurement gate, measures the high impulse of gate to the time interval value in requisition for measuring; Signal strobe carries out bigness scale by clock count unit 102, and interpolation unit 103 carries out after accurate measurement, just can obtain measuring the precise time value of gate high impulse; Combine and just can obtain needing the positive and negative time interval of measurement with detection polarity number.Utilize such scheme HP5370 to realize the time interval measurement resolution of 200ps, reached-4s of time interval measurement scope～+ 4s.Its extraction unit 101 adopts the customization integrated chip with intellecture property to realize, and interpolation unit 103 adopts lag line to realize, and the core place that these two unit are also whole schemes, has higher technology and realize difficulty.
Shortcoming of the prior art is:
While 1, adopting single channel to complete positive and negative time interval measurement, when two events generation moment close proximity, for example, when the time interval is less than 50ps, with the response speed of current device, be difficult to judge that event is leading, that event lags, during positive and negative time interval measurement, polarity detects and can have one section of dead band, can reduce like this accuracy of positive and negative time interval measurement.
2,, with the above-mentioned condition of shortcoming 1, measure gate extraction circuit and burst pulse metering circuit and all cannot realize so high time interval measurement precision.Owing to being subject to the restriction of device pulse recognition ability, measuring gate can not be infinitely small; Burst pulse means that it has higher frequency component in addition, and this also will bring no small challenge to the layout of printed board and cabling, and these factors can limit the further raising of positive and negative time interval measurement resolution and measuring accuracy.
3, the implementation that has adopted bigness scale and accurate measurement to combine in time measurement, synchronous processing must be done in bigness scale unit and accurate measurement unit, not so can introduce ± 1 error of measuring the clock period of some measurement result.When event rising edge and rising edge clock vicinity, because the response speed of pulse computing unit and interpolation unit is inconsistent, interpolation unit 103 may recognize nearest clock edge, pulse computing unit does not meet to be set up the retention time and has missed corresponding clock edge, will cause like this time measurement result to occur-1 clocking error; There will be+1 clocking error of negative edge in like manner.
4, adopt look-up table, carry chain and the cascade chain of FPGA inside as lag line, it is subject to the impact of supply voltage and temperature comparatively remarkable.Can increase time delay along with the rising of temperature, and while supposing 25 degrees Celsius, be 1 time delay, and during 85 degrees Celsius of temperature, will become 1.1 time delay, and during temperature-40 degree Celsius, will become 0.9 time delay; Time delay, the fluctuation along with supply voltage also can change, and while supposing that supply voltage is 3.3V, be 1 time delay, and when supply voltage is 3.5V, will become 0.95 time delay, and when supply voltage is 3.1V, be 1.05 time delay.Visible supply voltage and temperature have obvious impact to the measuring accuracy of the method, and this has also limited the application of the method in Practical Project.
Therefore, there is defect in prior art, needs to improve.
Summary of the invention
Technical matters to be solved by this invention is for the deficiencies in the prior art, and a kind of high-precision positive and negative time interval measurement method and device are provided.
Technical scheme of the present invention is as follows:
Adopt such scheme:
1, adopt binary channels to complete positive and negative time interval measurement, can realize very high measuring accuracy, not have dead-time problem simultaneously.
2, adopt high-speed comparator to complete input signal shaping, can realize polytype signal input and wide input dynamic range.Channel circuit adopts High Speed ECL device to realize, and channel bandwidth is large, can realize burst pulse and measure.
3, the extraction circuit design adopting is simple, and the measurement gate that not only can realize without dead band extracts, and can carry out broadening to measuring gate, avoids the burst pulse of being inconvenient to process.
4, adopt microstrip line as delay cell, can realize very high time interval measurement resolution, and time interval measurement resolution is affected by environment little, calibration process is also very simple.
5, adopt counter collocation form flexibly, resource consumption is few, can realize very wide positive and negative time interval measurement scope.
6, adopt general integrated device to realize, technical threshold is less demanding, realizes cost low.
Accompanying drawing explanation
Fig. 1 be in prior art positive and negative time interval measurement realize schematic diagram.
Fig. 2 is event 1 and event 2 work schedule schematic diagram in Fig. 1.
Fig. 3 is the high-precision positive and negative time interval measurement device of the present invention.
Fig. 4 is event 1 and event 2 work schedule schematic diagram in Fig. 3.
Fig. 5 is that shaping and extraction unit are realized theory diagram
Fig. 6 is that front interpolation unit is realized theory diagram
Fig. 7 is front interpolation unit work schedule schematic diagram
Fig. 8 is that theory diagram is realized in clock count unit
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
As shown in Fig. 3-8, the positive and negative time interval measurement device of the present invention comprises following components:
Signal shaping and measurement gate extraction unit, the triggering level according to arranging, compares shaping to input signal, measured signal unification is converted to the ECL signal of being convenient to subsequent treatment, utilizes trigger to extract the two-way signal strobe that need to measure.
Synchronous and interpolation unit, utilize counting clock to sample to measuring signal strobe, obtain the signal strobe of synchronizeing with counting clock, one tunnel send clock count unit to carry out bigness scale to measuring gate, another road send interpolation unit to carry out front interpolation measurement, completes measuring the accurate measurement of the inadequate clock period part in gate forward position.
Clock count unit, utilizes synchronous signal strobe control counter, completes and measures measuring the number of cycles of gate.
Storage and Processing unit, complete the storage to clock count unit and interpolation unit measurement data, interpolation measurement data is first gone out to burr and process, then according to coding rule, convert interpolative data to interpolation time value, finally calculate positive and negative time interval measurement value.
Basic functional principle of the present invention is as follows: as shown in work schedule Fig. 4, when needing measurement event 2 with respect to positive and negative time interval of event 1, no matter be after the effective rising edge of reference event 1 or observation event 2 arrives, all will make corresponding trigger be output as high level, complete the mark to event due in, specific works principle is with reference to figure 5.After the effective edge edge of two events is all labeled, through FPGA, detects and after delay a period of time, two triggers resetted simultaneously.As shown in Figure 4, the difference in pulse width of two pulse signals is the positive and negative time interval that needs measurement, therefore needs first measure respectively the pulse width of two pulse signals.In realization, adopted bigness scale to add the mode that accurate measurement combines, utilized clock count unit that the bigness scale value of pulse width is provided, lag line interpolation unit provides the accurate measurement value of pulse width, and the positive and negative time interval value that finally can obtain measuring is:
±TI2→1＝TG1－TG2
＝IT1＋IT11－IT12－（IT2＋IT21－IT22）
＝IT1＋IT11－IT2－IT21
＝Tclk×（N1－N2）＋TD×（M1－M2）
Adopt binary channels to complete positive and negative time interval measurement, by subtraction, embody relativeness between two events, when reference event changes, without changing hardware circuit setting, only need to change their positions in computing.Adopt twin-channel structure can overcome the dead-time problem existing in positive and negative time interval measurement in the past.Extract circuit and realize simply, by additional delay, improved the width of measuring signal strobe, can reduce the design pressure of subsequent conditioning circuit.Adopt synchronous treatment technology, avoided measured value appearance ± 1 clocking error.Adopt microstrip line as lag line, time delay is affected by environment little; Lag line adopts differential configuration to improve time interval measurement resolution, and time interval measurement resolution will no longer be subject to the restriction of device physical size.Implementation is simple, and key components used is general integrated device, and the technology of the present invention threshold is less demanding, realize cost low, there is promotional value widely.
The present invention can obtain following performance index: positive and negative can reach-4s of time interval measurement scope～+ 4s, and positive and negative time interval measurement resolution can reach 40ps, and the positive and negative time interval measurement precision of single is better than 100ps.
In order to expand the dynamic range of input signal, support polytype signal input, the present invention has designed a high-speed comparator at input end, completes the shaping of input signal and level conversion.The high-speed comparator of selecting is ADCMP582, and it can identify minimum pulse width is 100ps, and output level form is PECL, and after high-speed comparator shaping, input signal unification converts the PECL signal with high speed rising and falling edges to.The magnetic hysteresis interval of comparer is adjustable, and minimum judgement magnetic hysteresis interval can reach 10mV left and right, and these can provide solid foundation for realizing high precision time interval measurement.
PECL signal after shaping send the extraction unit being comprised of trigger and FPGA, extracts and measures signal strobe.The data termination ECL high level of trigger, the reversed-phase output signal of trigger send FPGA after ECL to TTL conversion, FPGA detects two paths of signals while being all low, after utilizing the inner 100MHz clock signal delay of FPGA 40ns, simultaneously by two extraction trigger resets.Trigger models used all in design are MC100EP51, and maximum operation frequency surpasses 3GHz, and the foundation needing and retention time are 100 psec left and right, and it is MC100EP21 that ECL to TTL converter is selected model.
To measure gate and send the data terminal of synchronizer trigger, the clock signal of clock termination 1GHz, after the sampling of 1GHz clock signal, can obtain the signal strobe with clock signal synchronization, is called for short sync gate.Clock count unit is sent on synchronous gate signal one tunnel, and interpolation unit is sent on a road.In clock count unit, synchronous gate signal enables as binary counter MC100EP016's, and the counting clock frequency of counter is 1GHz.Counter works during sync gate is height is data storage and the zero clearing completing between lowstand counter at sync gate.MC100EP016 is 8 binary counters, and during actual use, it far can not meet the design requirement to counting bit wide.In the present invention in FPGA indoor design 24 digit counters, cascade forms 32 digit counters with it, maximum measuring time can reach 4 seconds, this can meet the demand to time interval measurement scope in most cases.Certainly, for improving time interval measurement scope, can realize flexibly by the bit wide of the inner counting of configuration FPGA.
In order to improve the Measurement sensibility degree of interpolation unit, the present invention selects microstrip line as delay cell, and it has higher environmental stability.The microwave sheet material that specific inductive capacity is little is selected in printed board, to improve the transmission speed of microstrip line power on signal.In the present invention, microstrip line length corresponding to 1ps transmission delay is 0.2217mm, and the length of lag line 1 correspondence is 20mm, and the length of lag line 2 correspondences is 28.868mm.Interpolation unit maximum measuring time is 1ns, and this progression that needs delay chain is 25, and the total length that can extrapolate lag line 1 is 500mm, and the total length of lag line 2 is 721.7mm.Temperature coefficient according to 1cm microstrip line under certain document statistics room temperature condition is 0.014ps/ ℃, both during 1 ℃ of the every rising of temperature, the total delay time of lag line 1 increases 0.7ps, the total delay time of lag line 2 increases 1ps, differential delay line total delay time increases 0.3ps/ ℃, and interpolation unit of the present invention has higher stability as can be seen here.
FPGA utilizes the rising edge of latch signal to latch interpolate value, utilizes negative edge to latch count value.In FPGA, utilize latch signal and 100MHz clock to generate a reseting pulse signal, latch signal negative edge postpones 10ns and produces reseting pulse signal, and the pulse width of reset signal is 10ns.
In FPGA interpolative data to go out burr rule as follows: the output valve of N position equals the logical “and” of N-1 position and N position input value; Primary output valve is identical with input value.
Through after above-mentioned processing, by the known clock period, be, after 1000ps, interpolation unit are 40ps substitution formula (1) every grade of time delay, just can count out the positive and negative time interval value (unit is ps) that needs measurement:
±TI＝1000×(N1－N2)＋40×(M1－M2)。
Embodiment bis-
On the basis of above-described embodiment, the method that the present embodiment provides is:
Step 1: peak value and valley according to input signal arrange comparative level, convert input signal to ECL signal by high-speed comparator, makes it have the less rising and falling edges time, to reduce trigger error.
Step 2: the ECL signal after high-speed comparator shaping is sent to the clock port of D flip-flop, the data termination high level of D flip-flop, after carrying out a rising edge, trigger is just output as height immediately.
Step 3: send FPGA by the reversed-phase output signal of two-way D flip-flop, FPGA detect two paths of signals be all low after, through postponing after a while, two triggers are carried out to reset operation simultaneously, the output signal of two triggers is forced to draw as low, and such two trigger outputs can form a pulse signal.Trigger positive output signal is for measuring gate, the rising edge of two-way measurement gate carries respectively the temporal information of event 1 and event 2, and the negative edge that two-way is measured gate overlaps completely, thereby the Measuring Time of two-way gate is done to subtraction just can obtain the relatively positive and negative time interval between two events, wherein with reference to the Measuring Time of gate as minuend.
Step 4: by measuring signal strobe and send the data terminal of synchronizer trigger, utilize counting clock to sample to measuring gate, obtain the signal strobe of synchronizeing with counting clock, referred to as sync gate.Synchronous gate signal is divided into two-way, and clock calculation unit is sent on a road; Interpolation unit is together sent with measurement signal strobe in another road.
Step 5: be sent to the synchronous gate signal of clock calculation unit, control as the use of binary computations device.During sync gate is height, clock signal is counted, obtain measuring gate thick time measured value; At sync gate, be between lowstand, utilize the latch signal that interpolation unit provides to latch count value, at FPGA inner utilization latch signal negative edge, after time delay, produce a reset signal, the state of binary counter is resetted.
Step 6: interpolation unit has adopted the mode of differential delay line to realize, measuring signal strobe is differential signal Zhong mono-tunnel, send the data terminal of corresponding trigger after classified delay, is fixed as TD1 every grade of time delay; Synchronous gate signal is another road of differential signal, send the clock end of corresponding trigger after classified delay, is fixed as TD2 every grade of time delay, and time delay, TD1 was than the large 40ps of TD2, and specific implementation principle as shown in Figure 6.
Step 7: the rising edge of measuring gate in interpolation unit is led over sync gate, lead time is zero to a clock period.Through after every grade of delay chain, the rising edge of measuring gate postpones 40ps with respect to sync gate.Suppose between M level and M+1 level, the rising edge of measuring gate overlaps with sync gate rising edge, after the rising edge of sync gate arrives the clock end of front M level trigger so, front M level trigger output is all high level, from M+1 level, starting to the output of afterbody trigger is all low level, and specific works sequential as shown in Figure 7.
Step 8: trigger output signal is sent to FPGA after level conversion, FPGA utilizes latch signal as clock, above-mentioned interpolative data to be latched.
Step 9: synchronous gate signal, through after whole delay chain, is sent to FPGA as latch signal through ECL to Transistor-Transistor Logic level conversion, controls latching of count value and interpolate value.Utilize the negative edge of latch signal to latch count value, utilize the rising edge of latch signal to latch interpolate value, specific implementation principle as shown in Figure 8.
Step 10: produce reset signal at FPGA inner utilization latch signal rising edge after time delay, the state of each trigger in interpolation unit is resetted.Adopt FPGA to produce reset signal, so conveniently the sequential of reset signal is controlled.
The interpolative data that step 11:FPGA latchs, after deburring and code conversion, converts scale-of-two interpolate value to, and minimum value is 0, maximal value is N(delay chain progression).Code conversion rule is as follows: from interpolation unit first order delay chain, start to calculate the number of output high level, if there is a continuous N high level, conversion value is M.
Step 12: utilize the substitution time delay formula (1) of known clock period and every grade of delay chain, just can count out the positive and negative time interval value that needs measurement.
The present invention has following feature: adopt binary channels to complete positive and negative time interval measurement, by subtraction, embody relativeness between two events, when reference event changes, without changing hardware circuit setting, only need to change their positions in computing.Adopt twin-channel structure can overcome the dead-time problem existing in positive and negative time interval measurement in the past.Extract circuit and realize simply, by additional delay, improved the width of measuring signal strobe, can reduce the design pressure of subsequent conditioning circuit.Adopt synchronous treatment technology, avoided measured value appearance ± 1 clocking error.Adopt microstrip line as lag line, time delay is affected by environment little; Lag line adopts differential configuration to improve time interval measurement resolution, and time interval measurement resolution will no longer be subject to the restriction of device physical size.Implementation is simple, and key components used is general integrated device, realizes cost low.
Should be understood that, for those of ordinary skills, can be improved according to the above description or convert, and all these improvement and conversion all should belong to the protection domain of claims of the present invention.
Claims (9)
1. a high-precision positive and negative time interval measurement method, is characterized in that, comprises the following steps:
Step 1: peak value and valley according to input continuous wave or pulse signal arrange comparative level, convert input signal to ECL signal by high-speed comparator, makes ECL signal have the rising and falling edges time of 40ps left and right;
Step 2: ECL signal is sent respectively to the clock port of two-way D flip-flop, the high level of the data termination ECL signal of two-way D flip-flop, when having after the rising edge of an ECL signal arrives, D flip-flop just immediately output signal be height;
Step 3: the reversed-phase output signal of two-way D flip-flop is sent to FPGA, when reversed-phase output signal that FPGA detects two-way D flip-flop be all low after, through 40ns, postpone, two-way D flip-flop is resetted simultaneously, the output signal of two-way D flip-flop is forced to draw as low, and now two-way D flip-flop will be exported respectively a pulse signal; Two-way D flip-flop positive output signal is for measuring gate, two-way is measured the rising edge corresponding event 1 of difference of gate and the due in of event 2, and the negative edge that two-way is measured gate overlaps completely, therefore the relatively positive and negative time interval between event 1 and event 2 can obtain by the Measuring Time during two-way gate height is done to subtraction, and wherein gate time corresponding to reference event is minuend;
Step 4: by measuring gate and be sent to the data terminal of synchronizer trigger, utilize counting clock to sample to measuring gate, obtain the signal strobe of synchronizeing with counting clock, synchronous gate signal is divided into two-way, and riches all the way delivers to clock calculation unit; Interpolation unit is together delivered to measurement gate in another road;
Step 5: be sent to the synchronous gate signal of clock calculation unit, as the work that enables control counter chip; At synchronous gate signal, while being high, clock signal is counted to get to the bigness scale time value of measuring gate; At synchronous signal strobe, while being low, utilize the latch signal that interpolation unit provides to latch the measured value of clock calculation unit; In FPGA, utilize the negative edge of latch signal after time delay, to produce a reset signal simultaneously, the state of counter is resetted;
Step 6: interpolation unit adopts the mode of differential delay line to realize, and measuring signal strobe is differential signal Zhong mono-tunnel is delivered to the data terminal of corresponding trigger after postponing step by step, is fixed as TD1 every grade of time delay; Synchronous gate signal is another road of differential signal, send the clock end of corresponding trigger after postponing step by step, and be fixed as TD2 every grade of time delay, time delay TD1 is set than the large 40ps of TD2;
Step 7: the rising edge of measuring gate in interpolation unit is led over sync gate, lead time is zero to a clock period, every through after one-level delay chain, the rising edge of measuring gate postpones 40ps with respect to sync gate; While being arranged between M level and M+1 level, the rising edge of measuring gate overlaps with sync gate rising edge, after the rising edge of sync gate arrives the clock end of front M level trigger, front M level trigger output is all high level, and from M+1 level, starting to the output of afterbody trigger is all low level;
Step 8: two-way D flip-flop output signal is sent to FPGA after level conversion, FPGA utilizes latch signal as clock, described interpolative data to be latched;
Step 9: synchronous gate signal is through after differential delay chain, through ECL signal, to the conversion of TTL signal level, send FPGA as latch signal, control latching of count value and interpolate value, utilize the negative edge of latch signal to latch count value, utilize the rising edge of latch signal to latch interpolate value;
Step 10: utilize latch signal rising edge to produce reset signal in FPGA after time delay, the state of each trigger in interpolation unit is resetted;
The interpolative data that step 11:FPGA latchs is after deburring and code conversion, convert interpolate value to, minimum value is 0, maximal value is N, code conversion rule is as follows: the number that starts to calculate output high level from interpolation unit first order delay chain, if there is a continuous N high level, conversion value is M;
Step 12: utilize substitution time delay of known clock period and every grade of delay chain public
Formula:, ± TI1 → 2=TG1-TG2=IT1+IT11-IT12-(IT2+IT21-IT22)=IT1+IT11-IT2-IT21=Tclk * (N1-N2)+TD * (M1-M2)
(formula 1)
Wherein ± TI1 → 2 represent that measurement event 1 is with respect to the positive and negative time interval of event 2, and IT1 represents to measure the bigness scale time value of gate 1, IT
11represent to measure forward position value excess time of gate 1 correspondence, IT12 represents to measure the rear along value excess time of gate 1 correspondence, Tclk represents the counting clock cycle, M1 represents to measure the front interpolate value of gate 1 correspondence, TD represents the temporal resolution (for 40ps) of differential delay, the symbol definition of measuring gate 2 is similar, just can calculate the positive and negative time interval value that needs measurement by above-mentioned formula.
2. the device of method as claimed in claim 1, is characterized in that, comprises signal shaping and measures gate extraction unit, synchronous and interpolation unit, clock count unit, storage unit, data processing unit and interconnect and communication mutually; Described signal shaping and measurement gate extraction unit, the triggering level that arranges according to measured signal, continuous wave or pulse signal to input compare shaping, measured signal is converted into ECL signal, utilizes signal shaping and measure the two-way signal strobe that the trigger extraction in gate extraction unit need to be measured; Described synchronous and interpolation unit, utilize the counting clock in synchronous and interpolation unit to sample to two-way signal strobe, obtain the signal strobe of synchronizeing with counting clock, riches all the way delivers to clock count unit and carries out bigness scale to measuring gate, another road is sent to interpolation unit and carries out front interpolation measurement, completes measuring the accurate measurement of the inadequate clock period part in gate forward position; Described clock count unit, utilizes synchronous signal strobe to control the counter in clock count unit, completes measuring the measurement in gate whole counting clock cycle; Described storage unit, for storing clock count unit and interpolation unit measurement data; Described data processing unit is processed for interpolation measurement data first being gone out to burr, then according to coding rule, converts interpolative data to interpolation time value, finally calculates positive and negative time interval measurement value.
3. device as claimed in claim 2, is characterized in that, the method that described burr is processed is: the output valve of N position equals the logical “and” of N-1 position and N position input value; Primary output valve is identical with input value.
4. device as claimed in claim 2, is characterized in that, described coding rule is: from interpolation unit first order delay chain, start to calculate the number of output high level, if there is a continuous N high level, conversion value is M.
5. device as claimed in claim 2, is characterized in that, described in calculate positive and negative time interval measurement value formula be:
±TI1→2＝TG1－TG2?＝IT1＋IT11－IT12－（IT2＋IT21－IT22）＝IT1＋IT11－IT2－IT21＝Tclk×（N1－N2）＋TD×（M1－M2）。
6. device as claimed in claim 2, it is characterized in that, described shaping and measurement gate extraction unit comprise DA, High Speed ECL comparer, trigger and FPGA, by DA, comparative level is set, utilize High Speed ECL comparer to compare shaping to input signal, trigger extracts and measures signal strobe under FPGA controls.
7. device as claimed in claim 2, it is characterized in that, described synchronous and interpolation unit comprises ECL trigger, micro-band lag line and FPGA, utilize trigger to extract the measurement gate of original gate and clock synchronous, utilize trigger and microstrip line to form difference interpolation unit, complete the accurate measurement to original gate residual time, utilize FPGA to carry out debounce and coding processing to the output of interpolation unit simultaneously.
8. device as claimed in claim 2, it is characterized in that, described clock count unit consists of High Speed ECL counter and the cascade of FPGA internal extended counter, High Speed ECL counter uses as the low level of cascade counter, and it completes the carry counting system signal that send a low speed of FPGA after high-speed counting part; The counting clock frequency that it can work very high, can realize and count flexibly bit wide.
9. device as claimed in claim 2, it is characterized in that, described storage unit and data processing unit are mainly realized by FPGA, FGPA utilizes the synchronous gate signal of input to produce various control signals, complete the storage to each functional unit measurement data, based on algorithm shown in formula 1, calculate the positive and negative time interval value that needs measurement.
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Cited By (31)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104111601B (en) * | 2014-07-30 | 2016-08-24 | 中国科学院测量与地球物理研究所 | A kind of time-to-digit converter based on time delay ring "flop-out" method and time interval measurement method thereof |
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| WO2018032644A1 (en) * | 2016-08-17 | 2018-02-22 | 中国电子科技集团公司第四十一研究所 | Bandwidth modulation domain measurement system and method therefor |
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