CN109995359A - Edge triggered flip flop metastable state observation system and its observation method - Google Patents
Edge triggered flip flop metastable state observation system and its observation method Download PDFInfo
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- CN109995359A CN109995359A CN201910282713.4A CN201910282713A CN109995359A CN 109995359 A CN109995359 A CN 109995359A CN 201910282713 A CN201910282713 A CN 201910282713A CN 109995359 A CN109995359 A CN 109995359A
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- trigger
- error code
- delayer
- edge
- metastable state
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
Abstract
The present invention provides a kind of edge triggered flip flop metastable state observation system and its observation methods, it include: a kind of edge triggered flip flop metastable state observation system, comprising: pulse signal source, delayer A, delayer B, trigger, NRZ/RZ converter, error code testing unit and oscillograph；It is respectively connected to delayer A and delayer B at the end D of trigger and the end CP, with the input delay interval τ of oscillograph readout delay device A and delayer B01.NRZ/RZ converter is set between the end trigger Q and error code testing unit；Jump edge and the end CP rising edge of a pulse in trigger Q end pulse are counted respectively with error code testing unit.The invention has the advantages that: the observation system is simple and easy, high reliablity, has important reference value to the engineers and technicians and faculty for being engaged in edge triggered flip flop meta-stable behavior research.
Description
Technical field
The present invention relates to metastable state observation technology field, in particular to a kind of edge triggered flip flop metastable state observation system.
Background technique
A kind of storage memory cell of the trigger as high speed widely applies in contemporary IT hardware circuit and system.
To realize the reliable storage to input data, it is desirable that settling time and retention time area of the input data before and after rising edge clock
Domain is kept constant, and metastable state otherwise will occur, and causes the error code for storing data in trigger.It is studied to trigger internal circuit
In the application of trigger cross clock domain, people often need to observe metastable state generating process.But since metastable state process belongs to random mistake
Journey is difficult observation in actual operation and obtains.
Summary of the invention
The present invention in view of the drawbacks of the prior art, provides a kind of edge triggered flip flop metastable state observation system, can be effective
Solve the above-mentioned problems of the prior art.
In order to realize the above goal of the invention, the technical solution adopted by the present invention is as follows:
A kind of edge triggered flip flop metastable state observation system, comprising: pulse signal source, delayer A, delayer B, trigger,
NRZ/RZ converter, error code testing unit and oscillograph；
It has been respectively connected to delayer A and delayer B at the end D of trigger and the end CP, with oscillograph readout delay device A and has been prolonged
The input delay interval τ of slow device B01。
NRZ/RZ converter is set between the end trigger Q and error code testing unit；
Jump edge and the end CP rising edge of a pulse in trigger Q end pulse are counted respectively with error code testing unit, then
It pressesFormula obtains the bit error rate δ in the case of the input stimulus01。
Error code testing unit by NI capture card and Labview software sharing,
When LABVIEW is programmed, only the data that NI capture card port processing is come in need to be subjected to rising edge differentiation, be posted with displacement
Storage continuous counter, and write clear terminal.
The data of NI capture card port processing carry out in rising edge discriminating program, and first index of reference array VI is by two ports
Data field separates, then respectively using Boolean conversion (point-by-point) VI progress rising edge differentiation, in the VI, direction selection false-
true.Clear terminal takes the method that data 0 are written to in construction of condition for fictitious time shift register, reaches the mesh of zeros data
's.
Further, pulse signal source exports 0~5V square wave, duty ratio 50%, frequency 100Hz.Phase shifter R=100 Ω.
A kind of observation method of edge triggered flip flop metastable state observation system, comprising the following steps:
Step 1, observed by oscillograph, make to jump edge and the end trigger CP rising edge spacing on the end D of trigger | τ01|>|
τ01L|。
Step 2, realization pair | τ01| the scanning of successively decreasing within settling time.
Step 3, as | τ01|<|τ01L| when, at the end trigger Q, error code waveform can be observed in oscillograph, at this time can be by oscillography
Device reads τ01Value reads δ by error code testing unit01Value.
Step 4, with | τ01| reduction, δ01Value gradually dull will increase.When | τ01|<|τ01H| when, δ01Value is up to
100%.Continue to reduce | τ01| until when being 0, δ01Value will remain 100% value.
Compared with prior art the present invention has the advantages that the observation system is simple and easy, high reliablity, to being engaged in edge
The engineers and technicians and faculty of trigger meta-stable behavior research have important reference value.
Detailed description of the invention
Fig. 1 is the error code curve graph in settling time of the invention；
Fig. 2 is the end D of the present invention in [τ01L, τ01H] schematic diagram is jumped on section；
Fig. 3 is the random error waveform diagram at the end Q of the present invention；
Fig. 4 is metastable state observation system block diagram of the present invention；
Fig. 5 is metastable state observation system circuit diagram of the present invention；
Fig. 6 is error code testing cellular construction figure of the present invention；
Fig. 7 is metastable state of embodiment of the present invention experimental observation flow chart；
Fig. 8 is δ~τ error code curve graph in 74HC74 of embodiment of the present invention settling time
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention more comprehensible, it is developed simultaneously embodiment with following combination attached drawing,
The present invention is described in further details.
Working principle
In edge D flip-flop settling time TsuRegion, there are an error code curves as shown in Figure 1.
When " 0 " jump to " 1 " of later moment in time of the D end data by jump previous moment, between the hopping edge D and CP rising edge
It is divided into τ01, and meet | τ01L|>|τ01|>|τ01H| when, as shown in Figure 2.
Stable metastable state error code waveform can be observed at the end trigger Q, as shown in Figure 3.
In Fig. 3, the end Q random error waveform at a time and is not known, but has statistics rule, with τ01From greatly to
It is small, the bit error rate will from 0% gradually monotone increasing to 100%.
CP, Q (RZ) rising edge are counted, there are mathematical relationships between count value:
For convenience of counting, the end Q need to be exported non-return-to-zero waveform Q (NRZ) and be converted to zero waveform Q (RZ).
The composition of metastable state observation system
It is as shown in Figure 4 that metastable state observation system constitutes block diagram.For the delay for realizing the end D and the end CP, distinguish at the end D and the end CP
Delayer 1 and delayer 2 have been accessed, has read input delay interval τ with oscillograph01.With error code testing unit to being jumped in the pulse of the end Q
Edge and the end CP rising edge of a pulse are counted respectively, then obtain the bit error rate δ in the case of the input stimulus by (3) formula01。
If the end D and the end CP use same pulse signal source, delayer selects RC retardation ratio circuit, NRZ/RZ circuit by the end Q with
The end CP phase with obtain, so that it may realize timing shown in Fig. 3.It is as shown in Figure 5 to test physical circuit.
In Fig. 5 circuit, operating voltage 5V, pulse signal source model RIGOL DS1102E, oscillograph model Tektronix
MSO58.Pulse signal source exports 0~5V square wave, duty ratio 50%, frequency 100Hz.Phase shifter R=100 Ω, C2Select 5/
20pF trimmer.Integrated 42 input terminals and door CD4081 are selected with door.In order to shaping be isolated, NOT gate is selected integrated six defeated
Enter NOT gate CD4069.
Error code testing unit
Error code testing unit is by NI capture card and Labview software sharing, as shown in Figure 6.
The model NI USB-6001 of capture card has 13 digital ports.This experiment uses two number ports I/O,
That is port P0.0, port P0.1.
When LABVIEW is programmed, only the data that P0.0, P0.1 port processing are come in need to be subjected to rising edge differentiation, with displacement
Register continuous counter, and write clear terminal.
The data of data port acquisition carry out in rising edge discriminating program, and first index of reference array VI is by the data of two ports
It distinguishes, then respectively using Boolean conversion (point-by-point) VI progress rising edge differentiation, in the VI, direction selection false-true.
Clear terminal takes the method that data 0 are written to in construction of condition for fictitious time shift register, achievees the purpose that zeros data.
Embodiment 1
The process for carrying out experimental observation to edge D flip-flop using metastable state observation system is as shown in Figure 7.
A kind of observation method of edge triggered flip flop metastable state observation system, comprising the following steps:
Step 1, make C1、C2Minimum increases C3, observed by oscillograph, make to jump edge and trigger CP on the end D of trigger
Hold rising edge spacing | τ01|>|τ01L|。
Step 2, fixed C3, it is gradually increased C1, realization pair | τ01| the scanning of successively decreasing within settling time.
Step 3, as | τ01|<|τ01L| when, at the end trigger Q, error code waveform can be observed in oscillograph, at this time can be by oscillography
Device reads τ01Value reads δ by error code testing unit01Value.
Step 4, fixed C1And C3, increase fine tuning capacitor C2Value.With | τ01| reduction, δ01Value gradually dull will increase.
When | τ01|<|τ01H| when, δ01Value is up to 100%.Continue to reduce | τ01| until when being 0, δ01Value will remain 100% value.
In Fig. 5, the d type flip flop in figure is substituted by integrated trigger 74HC74, observes example as metastable state.Actual measurement
Data are as shown in table 1.
1 74HC74 integrated trigger error rate data of table record
| τ01(ns) | δ (%) |
| -20.000 | 0 |
| -10.00 | 0 |
| -5.000 | 0 |
| -3.000 | 0 |
| -1.300 | 0 |
| -1.289 | 3.32 |
| -1.220 | 13.06 |
| -1.197 | 32.03 |
| -1.096 | 54.91 |
| -1.082 | 62.28 |
| -1.059 | 74.84 |
| -1.036 | 82.59 |
| -1.013 | 95.55 |
| -0.850 | 100 |
| -0.500 | 100 |
| 0 | 100 |
τ in table 101It is read by oscillograph from the end D and half height of the end CP waveform.
The end Q is monitored with oscillograph, works as τ01Into [τ01L, τ01H] in section, there is metastable state error code.
The error code curve drawn by 1 data of table is as shown in figure 8, τ01L=1.675ns, τ01H=1.013ns, error code intermediate zone
Within the scope of 1.675ns~1.013ns.
This embodiment describes the design philosophy of edge triggered flip flop metastable state observation system, specific test circuit is given
With detailed test process.When the delay value between the end trigger D and the end CP is in a certain section in settling time, pass through oscillography
Device can be intuitive to see the end Q error code output waveform when metastable state occurs.Made in embodiment with integrated edge triggered flip flop 74HC74
For example, 0%~100% dull stable error code waveform is showed within the scope of settling time 1.675ns~1.013ns,
Measuring accuracy reaches 0.001ns.
Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this hair
Bright implementation method, it should be understood that protection scope of the present invention is not limited to such specific embodiments and embodiments.Ability
The those of ordinary skill in domain disclosed the technical disclosures can make its various for not departing from essence of the invention according to the present invention
Its various specific variations and combinations, these variations and combinations are still within the scope of the present invention.
Claims (3)
1. a kind of edge triggered flip flop metastable state observation system characterized by comprising pulse signal source, delayer A, delayer
B, trigger, NRZ/RZ converter, error code testing unit and oscillograph；
It is respectively connected to delayer A and delayer B at the end D of trigger and the end CP, with oscillograph readout delay device A and delayer
The input delay interval τ of B01；
NRZ/RZ converter is set between the end trigger Q and error code testing unit；
Jump edge and the end CP rising edge of a pulse in trigger Q end pulse are counted respectively with error code testing unit, then pressedFormula obtains the bit error rate δ in the case of the input stimulus01；
Error code testing unit by NI capture card and Labview software sharing,
When LABVIEW is programmed, only the data that NI capture card port processing is come in need to be subjected to rising edge differentiation, use shift register
Continuous counter, and write clear terminal；
The data of NI capture card port processing carry out in rising edge discriminating program, and first index of reference array VI is by the data of two ports
It distinguishes, then respectively using Boolean conversion (point-by-point) VI progress rising edge differentiation, in the VI, direction selection false-true；
Clear terminal takes the method that data 0 are written to in construction of condition for fictitious time shift register, achievees the purpose that zeros data.
2. a kind of edge triggered flip flop metastable state observation system according to claim 1, it is characterised in that: pulse signal source is defeated
0~5V square wave out, duty ratio 50%, frequency 100Hz；Phase shifter R=100 Ω.
3. a kind of observation method of edge triggered flip flop metastable state observation system according to claim 1, which is characterized in that packet
Include following steps:
Step 1, observed by oscillograph, make to jump edge and the end trigger CP rising edge spacing on the end D of trigger | τ01|>|τ01L|；
Step 2, realization pair | τ01| the scanning of successively decreasing within settling time；
Step 3, as | τ01|<|τ01L| when, at the end trigger Q, error code waveform can be observed in oscillograph, can be read at this time by oscillograph
τ out01Value reads δ by error code testing unit01Value；
Step 4, with | τ01| reduction, δ01Value gradually dull will increase；When | τ01|<|τ01H| when, δ01Value is up to 100%；
Continue to reduce | τ01| until when being 0, δ01Value will remain 100% value.
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| CN111262583A (en) * | 2019-12-26 | 2020-06-09 | 普源精电科技股份有限公司 | Metastable state detection device and method and ADC circuit |
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| CN1380998A (en) * | 2000-03-06 | 2002-11-20 | 皇家菲利浦电子有限公司 | Method and apparatus for generating random numbers using flip-flop meta-stability |
| CN102346236A (en) * | 2011-06-21 | 2012-02-08 | 电子科技大学 | Time parameter measurement system |
| CN104182203A (en) * | 2014-08-27 | 2014-12-03 | 曙光信息产业(北京)有限公司 | True random number generating method and device |
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| CN1380998A (en) * | 2000-03-06 | 2002-11-20 | 皇家菲利浦电子有限公司 | Method and apparatus for generating random numbers using flip-flop meta-stability |
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Cited By (3)
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| CN111262583A (en) * | 2019-12-26 | 2020-06-09 | 普源精电科技股份有限公司 | Metastable state detection device and method and ADC circuit |
| CN111262583B (en) * | 2019-12-26 | 2021-01-29 | 普源精电科技股份有限公司 | Metastable state detection device and method and ADC circuit |
| US11451236B2 (en) | 2019-12-26 | 2022-09-20 | Rigol Technologies Co., Ltd. | Metastabile state detection device and method, and ADC circuit |
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