CN103227639B

CN103227639B - A kind of phase detecting circuit for time-to-digit converter

Info

Publication number: CN103227639B
Application number: CN201310142744.2A
Authority: CN
Inventors: 张长春; 张陆; 李卫; 郭宇锋; 方玉明
Original assignee: Nanjing Post and Telecommunication University
Current assignee: Nanjing Post and Telecommunication University
Priority date: 2013-04-23
Filing date: 2013-04-23
Publication date: 2016-01-20
Anticipated expiration: 2033-04-23
Also published as: CN103227639A

Abstract

The invention provides a kind of phase detecting circuit for time-to-digit converter.Described phase detecting circuit adds rising edge testing circuit in traditional phase detecting circuit, rising edge testing circuit by continue high level through double sampling, obtain the pulse of a unit clock width, 32 of follow-up decoding circuit input ports are made all to only have one of them port to be high level at any time, thus reduce the design difficulty of decoding circuit, reduce the area of circuit, improve the performance of circuit and the precision of time to digital converter.Phase detecting circuit of the present invention is very simple and be easy to realize, and has good application prospect.

Description

A kind of phase detecting circuit for time-to-digit converter

Technical field

The invention belongs to integrated circuit (IC) design field, particularly a kind of phase detecting circuit for time-to-digit converter.

Background technology

Time-to-digit converter (TimeDigitalConverter, TDC), be a kind of common circuit of time measurement, main computing reference signal is to the time that event occurs and two interpulse time intervals, the interval of time is converted into high-precision digital value, and realizes numeral output.Be widely used in electronic applications at present, as in all-digital phase-locked loop ADPLL, improve the time response of its test component and signal.In recent years, TDC of greatest concern was the structure using high speed CMOS digital circuit, and main cause is that signal-under-test can realize higher time precision.TDC accuracy is studied, will application and the quality assurance of TDC be conducive to.

Fig. 1 is a kind of traditional structure for the time-to-digit converter in ADPLL, mainly comprises following components composition: 32 d type flip flops, 32 phase detecting module, two 5 bit decoders, 5 adders, 6 digit counters and some or door.The following operation principle briefly introducing TDC:

(1) measuring principle of pulsewidth

32 d type flip flops are sampled to phase difference pulse signal PUL, and the clock controlling the sampling of 32 d type flip flops is by external circuit ring oscillator (Free-RunningRingOscillator, FRO) provide, FRO provides 32 sampled clock signals with identical phase difference, the time interval of continuous print two sampling clocks is △, if phase difference PUL signal is high level at the rising edge place of sampling clock, then the value that corresponding d type flip flop is adopted is " 1 ".Just have a d type flip flop every the time interval of △ to sample to PUL, just can represent the pulsewidth of PUL signal by the number of " 1 " of adopting.If the input Q of phase detecting module _n-1q _nq _n+1=011, the rising edge just representing PUL arrives, and corresponding phase detecting module will with signal record sampling clock number " n " now.Work as Q _m-1q _mq _m+1=100, the trailing edge representing PUL arrives, and so corresponding phase detecting module just also uses a signal record " m " now.The logic module of the inside will record the number of " 1 " between two edges in two sub-sections, and Part I record PUL rising edge place sampled clock signal adopts the number of times r of " 1 "; Part II records PUL leading edge position to the difference of trailing edge position sampling clock, is (m-n).Total number of " 1 " is two parts sum, and namely the width of PUL high level is (r+m-n) △.

(2) time is to the transforming principle of numeral:

The original position tracer signal s first produced phase detecting module module and end position tracer signal e encodes, then calculates its difference with an adder, completes Part II above-mentioned calculating.And current record signal c is used for triggering counter, obtains Part I and calculate.But notice that one " 1 " of the counter that c now triggers represents 32, so high 5 as last binary number.The combination of last two parts just obtains required by the binary number of time to digital translation.

Fig. 2 is traditional inner phase detecting circuit structure of TDC, when TDC works, when the rising edge of phase pulse signal PUL arrives, the then input signal ABC=011 of phase detecting module, T trigger 2 can produce a lasting high level signal s under corresponding clock control signal, records the rising edge of corresponding phase pulse signal; Equally, when the trailing edge of phase pulse signal PUL arrives, then the input signal ABC=100 of phase detecting module, T trigger 3 can produce a permanent High level signal e under corresponding clock control signal, records corresponding phase impulse trailing edge.Corresponding high level can continue always, until next phase pulse signal PUL arrives, again detected by this phase detecting module, high level just can become low level.This situation is concerning the input (s [31:0] or e [31:0]) of decoding circuit later, have when there is multiple high level simultaneously, bring more complicated input condition, the difficulty will brought to digital decoder on design programming like this, also can increase the area of circuit simultaneously, and the precision of influence time digital translation.

Summary of the invention

The present invention is directed to the deficiencies in the prior art, especially for the problem of the output signal permanent High level of existing time-to-digit converter phase detecting circuit, propose a kind of phase detecting circuit for time-to-digit converter.The output signal of described circuit is the pulse of a unit clock width, thus reduces the design difficulty of follow-up decoding circuit.

The present invention is for solving the problems of the technologies described above, adopt following technical scheme: a kind of phase detecting circuit for time-to-digit converter, described phase detecting circuit adds rising edge testing circuit at the output of existing time-to-digit converter phase detecting circuit, described rising edge testing circuit, rising edge sampling is carried out to a lasting high level, and then produce the pulse signal of a unit clock width, the design of follow-up decoding circuit is made to become simpler, and then reduce the area of circuit, realize the function that time figure transforms.

Described rising edge testing circuit comprises three d type flip flops, a not gate and one and door; Under control of the clock signal, first d type flip flop is to the rising edge signal sampling of input, second d type flip flop is to the first d type flip flop output signal sampling, 3d flip-flop is sampled to the second d type flip flop output signal, 3d flip-flop output signal inputs and door after not gate negate together with the second d type flip flop output signal, is the pulse of a unit clock width with the output signal of door.

The invention has the beneficial effects as follows: the invention provides a kind of phase detecting circuit for time-to-digit converter.Described phase detecting circuit adds rising edge testing circuit in traditional phase detecting circuit, rising edge testing circuit by continue high level through double sampling, obtain the pulse of a unit clock width, 32 of follow-up decoding circuit input ports are made all to only have one of them port to be high level at any time, thus reduce the design difficulty of decoding circuit, reduce the area of circuit, improve the performance of circuit and the precision of time to digital converter.Phase detecting circuit of the present invention is very simple and be easy to realize, and has good application prospect.

Accompanying drawing explanation

Fig. 1 is the structure of traditional TDC.

Fig. 2 is the phase detecting circuit in traditional TDC structure.

Fig. 3 is the circuit structure that conventional phase testing circuit adds rising edge detection module.

Fig. 4 is the structure of rising edge detection module.

Fig. 5 is the simulation waveform figure of rising edge detection module.

Fig. 6 is the simulation waveform adding the time-to-digit converter improving phase detecting circuit.

Fig. 7 is the result simulation waveform of whole time-to-digit converter.

Embodiment

Below in conjunction with accompanying drawing, illustrate a kind of phase detecting circuit for time-to-digit converter of the present invention further.

As shown in Figure 3, a kind of time-to-digit converter phase detecting circuit of the present invention, rising edge testing circuit is added: input signal A in conventional phase testing circuit, B, C is three continuous phase sampled signals, corresponding pulse current record signal c is generated through conventional phase testing circuit, pulse original position tracer signal S, end-of-pulsing position tracer signal E, but S tracer signal now and E tracer signal are lasting rising edge signal, the rising edge detection module they being sent into two same structures generates pulse original position tracer signal s and the end position tracer signal e of corresponding unit clock width.

Fig. 4 is rising edge testing circuit structure chart, its operation principle is: sampled to rising edge UP signal under the control of clock by d type flip flop 1, export as UP_1 signal, d type flip flop 2 pairs of UP_1 signals are sampled, export as UP_2, d type flip flop 3 pairs of UP_2 signals are sampled, and export as UP_3; After UP_3 negate again with UP_2 phase with, connect one and door, be Reg_UP signal with the output of door, be the pulse duration of a unit clock width.Wave simulation figure as shown in Figure 5.

The course of work of whole new phase detection module is: when phase impulse rising edge arrives, i.e. input signal ABC=011, high level " 1 " is exported with door 1, deliver to T trigger 1 and T trigger 2 when clock signal trailing edge arrives, make to become " 1 " in the output of these two T triggers of subsequent clock cycle falling edge.This situation means, from low transition to high level, S signal becomes high level logic " 1 ", and the high level S continued is after rising edge detection module, and by the pulse signal s of a generation unit clock width, representative detects phase impulse original position; When phase impulse trailing edge arrives, ABC=100, saltus step is high level when next rising edge clock signal arrives by the output of T trigger 3, E signal also will become high level, the high level E continued is after rising edge detection module, also by the pulse signal e of a generation unit clock width, representative detects phase place end position.

Fig. 6 is the wave simulation figure of the new utilization of phase detecting module in time-to-digit converter, as shown in the figure: after phase pulse signal PUL arrives, its rising edge is detected by the 26th d type flip flop (d type flip flop 25 in Fig. 1), then S can produce a permanent High level from low to high, send in rising edge detection module, thus sampled by continuous print 3 d type flip flops, and then obtaining the pulse signal s of unit clock width, the original position representing PUL is recorded.

Fig. 7 is the simulation result figure of whole time-to-digit converter, PUL is phase difference pulse signal, and the output size that Out [10:0] is whole TDC is the binary number representation method of phase pulse signal width.In simulation waveform figure, the developed width PULs=3750ns of continuous sampling clock interval △=62.5ns, first PUL, and test the width PULc=60 × 62.5ns=3750ns obtained, i.e. PULc=PULs.

In sum, a kind of time-to-digit converter phase detecting circuit provided by the invention, by adding rising edge testing circuit after conventional phase testing circuit, lasting high level is converted into the pulse signal of a unit clock width, record original position and the end position of phase pulse signal more easily, thus reduce the design of follow-up decoding circuit, reduce the area of circuit, and then the accuracy that when improve, number transforms.

For those skilled in the art, according to above implementation of class can be easy to association other advantage and distortion.Therefore, the present invention is not limited to above-mentioned instantiation, and it carries out detailed, exemplary explanation as just example to a kind of form of the present invention.Not deviating from the scope of present inventive concept, the technical scheme that those of ordinary skill in the art are obtained by various equivalent replacement according to above-mentioned instantiation, all should be included within right of the present invention and equivalency range thereof.

Claims

1. the phase detecting circuit for time-to-digit converter, it is characterized in that, described phase detecting circuit adds rising edge testing circuit at the output of existing time-to-digit converter phase detecting circuit, described rising edge testing circuit, rising edge sampling is carried out to a lasting high level, and then produces the pulse signal of a unit clock width;