CN105187053B - A kind of metastable state and eliminate circuit for TDC - Google Patents

Abstract

The invention belongs to electronic circuit technology field, more particularly to a kind of metastable state and eliminate circuit for TDC.The circuit primary structure of the present invention is made up of the first rising edge d type flip flop, the second rising edge d type flip flop, the 3rd rising edge d type flip flop, the first trailing edge d type flip flop and the second trailing edge d type flip flop；The D input termination external input signals of the D inputs of first rising edge d type flip flop, the first trailing edge trigger；The Q output of second rising edge d type flip flop connects the clock signal input terminal of the 3rd rising edge d type flip flop；The Q output of second trailing edge d type flip flop connects the D inputs of the 3rd rising edge d type flip flop.Beneficial effects of the present invention are that while the result after ensureing that time figure quantifies has identical range and resolution ratio with traditional TDC, can effectively eliminate timing error caused by metastable state, greatly improve the reliability of TDC precision.

Description

A Metastable Elimination Circuit for TDC

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to a metastable state elimination circuit for TDC.

Background technique

Time interval measurement technology has a large number of applications in many fields. It is not only widely used in atomic physics, laser ranging, positioning and timing, but also in the field of time interval measurement technology and automatic detection equipment; in addition, in the defense industry, time interval measurement is an important means of identification and detection , the requirements for accuracy are very strict, even reaching the level of picoseconds. Therefore, a high-precision TDC circuit plays an important role.

A typical all-digital time converter uses a DLL and a counter two-stage structure to quantify time. The basic idea is to measure the time between the rising edge of the start signal and the rising edge of the stop signal by counting a clock. The range of the TDC is mainly determined by the counting range of the counter, and the resolution depends on the DLL. A typical TDC circuit diagram based on this idea is shown in Figure 1, and its timing diagram is shown in Figure 2. The coarse value counter realizes the timing of nT _clk ; the latch encoding module realizes the timing of △T _start and △T _stop ; the data processing module Encode the 8-bit output sampled by the DLL and calculate the difference between the two timing parts ε=△T _stop -△T _start , and then give a carry signal c to the rough value counting module according to the difference. The timing output of the data processing module and the rough value counter module is combined into a conversion time △T, which is the time interval between the rising edges of the start and stop signals to be measured. From Figure 2, △T=nT _clk - △T _start + △T _stop , where T _clk is the clock cycle, △T _start and △T _stop are the start and end time measurement errors, and n is the count of the counter in △T value. Note that the conversion error from time to number is ε=△T _stop -△T _start , and △T=nT _clk +ε can be obtained.

Figure 3 is a circuit diagram of the DLL. Ideally, the DLL divides the clock into 8 phases, and samples each output phase when the start signal arrives. The timing diagram is shown in Figure 4. In fact, there will be deviations due to duty cycle distortion, signal jitter, delay deviation, etc., and start may appear metastable at a special sampling position. As shown in Figure 1, the calculation of △T _start is only related to the rising edge of d[7:0], so consider the position of the rising edge of d[7:0] signal when the start signal arrives. ①② is a pair of sampling positions, ③④ is another pair of sampling positions.

Due to the setup and hold time of the D flip-flop during sampling, start samples d[7:0] at position ①②. Since d[7] is in an inverted state, a metastable state may occur, resulting in an error in the sampling result. Therefore, △T _start may jump from T _clk to 0ns; or on the contrary, it may jump from 0ns to T _clk , resulting in a large deviation in the TDC count.

When start samples d[7:0] at position ③④, since d[2] is in an inverted state, although a metastable state may also occur, the correct value will be sampled at d[1] and d[3] , so △T _start has only one phase error, which can be ignored.

Contents of the invention

What the present invention aims to solve is to propose a metastability elimination circuit for TDC in view of the above problems.

To achieve the above object, the present invention adopts the following technical solutions:

A metastability elimination circuit for TDC, the circuit consists of a first rising edge D flip-flop, a second rising edge D flip-flop, a third rising edge D flip-flop, a first falling edge D flip-flop and a second falling edge D flip-flop Formed along the D flip-flop;

The D input terminal of the first rising edge D flip-flop is connected to an external input signal, its clock signal input terminal is connected to an external clock signal, and its Q output terminal is connected to the D input terminal of the second rising edge D flip-flop; the second rising edge D The clock signal input terminal of the flip-flop is connected to the external clock signal, and its Q output terminal is connected to the clock signal input terminal of the third rising edge D flip-flop; the D input terminal of the first falling edge flip-flop is connected to the external input signal, and its clock signal input terminal Connect the external clock signal, its Q output terminal is connected to the D input terminal of the second falling edge D flip-flop; the clock signal input terminal of the second falling edge D flip-flop is connected to the external clock signal, and its Q output terminal is connected to the third rising edge D trigger The D input terminal of the device; the first rising edge D flip-flop, the second rising edge D flip-flop, the first falling edge D flip-flop and the second falling edge D flip-flop are connected to the same external clock signal; the third rising edge The Q output terminal of the flip-flop is the output terminal of the metastability elimination circuit.

The beneficial effect of the invention is that, while ensuring that the result of time digital quantization has the same range and resolution as the traditional TDC, it can effectively eliminate the timing error caused by the metastable state, and greatly improve the reliability of the TDC accuracy.

Description of drawings

Figure 1 Typical TDC circuit structure;

Fig. 2 is a timing diagram of a typical time-to-digital conversion principle;

Fig. 3 is a DLL module structural diagram;

Figure 4 is a schematic diagram of the position where the metastable state may occur in the special sampling of start;

Fig. 5 is a schematic diagram of the logical structure of the metastable state elimination circuit of the present invention;

Fig. 6 is the application diagram of the metastable state elimination circuit of the present invention;

Fig. 7 is the time sequence diagram at the sampling position of the circuit of the present invention at position ① in Fig. 4;

Fig. 8 is a timing diagram at the sampling position of the circuit of the present invention at position ② in Fig. 4;

Fig. 9 contains the partial sequence diagram of the counter of the TDC of structure of the present invention;

Figure 10 is a schematic diagram of traditional TDC linearity;

Fig. 11 is a schematic diagram of TDC linearity using the circuit structure of the present invention.

detailed description

Below in conjunction with accompanying drawing and embodiment, describe technical solution of the present invention in detail:

In order to eliminate the timing error caused by metastable state when the traditional TDC adopts DLL and counter to quantify the time interval, the invention adds a metastable state elimination logic circuit. The TDC after eliminating the metastable state has the same accuracy as the typical TDC. The only difference is that when the start is sampled at the position ①② in Figure 4, the typical TDC may not be sampled correctly, so that the quantized result has a clock cycle deviation from the correct result, which is very Serious deviation. However, the circuit after adding the metastable state elimination logic will have a deviation of one clock period in the quantization result of the DLL after sampling incorrectly. At the same time, it will also give the counter a signal start_clk, so that the count n will also have a deviation of 1, as shown in Figure 9. Among them, start_clk is the signal generated by start after edge synchronization; stop_clk is the signal generated by stop after edge synchronization; start_stop is the signal generated by start_clk and stop_clk after passing through the enable module, as the enable signal of the counter; clk_dealy is the delayed clk Signal; gated_clk_delay is the signal after start_stop and clk_dealy pass through the two-input AND gate, which is used as the counting signal of the counter. Because the quantization errors of n and △T _start produced by the start metastable state sampling are offset, the elimination of the start sampling metastable state is realized.

The structure of the present invention is shown in Figure 5, wherein start_clk is the signal generated by start after rising edge synchronization, start_nclk is the signal generated by start after falling edge synchronization, Q_nclk is the sampling output signal of start on the falling edge of the clock, and the output s_out is the circuit critical result.

The structure of the present invention is shown in Figure 5. The circuit consists of a first rising edge D flip-flop, a second rising edge D flip-flop, a third rising edge D flip-flop, a first falling edge D flip-flop and a second falling edge D flip-flop. A flip-flop is formed; the D input terminal of the first rising edge D flip-flop is connected to an external input signal, its clock signal input terminal is connected to an external clock signal, and its Q output terminal is connected to the D output terminal of the second rising edge D flip-flop; The clock signal input terminal of the second rising edge D flip-flop is connected to the external clock signal, and its Q output terminal is connected to the clock signal input terminal of the third rising edge D flip-flop; the D input terminal of the first falling edge flip-flop is connected to the external input signal t, Its clock signal input terminal is connected to an external clock signal, and its Q output terminal is connected to the D input terminal of the second falling edge D flip-flop; the clock signal input terminal of the second falling edge D flip-flop is connected to an external clock signal, and its Q output terminal is connected to the second falling edge D flip-flop. D input terminals of three rising edge D flip-flops; the first rising edge D flip-flop, the second rising edge D flip-flop, the first falling edge D flip-flop and the second falling edge D flip-flop are connected to the same external clock signal ; The Q output terminal of the third rising edge trigger is the output terminal of the metastability elimination circuit.

This example works as follows:

As shown in Figure 4, at the sampling position ① or ②, the situation of d[x:x-1]=01 (x=6~1) does not appear. The sampling position judging module in FIG. 6 thus distinguishes whether the external input signal start (or stop) appears at the sampling position ① or ② in FIG. 4 . When it is judged that the sampling position is in ① or ②, the encoder uses the result encoding of the output signal s_out of the metastable state elimination circuit, that is, when s_out=0, △T _start is assigned as T _clk ; s_out=1, △T _start is assigned as 0ns. Otherwise, the encoder encodes normally and is not affected by s_out.

When start samples d[7:0] at position ① in Figure 4, the timing diagram of the metastable state elimination logic is shown in Figure 7. If the time interval between the external input signal start and the external clock signal clk signal does not meet the D flip-flop setup time, that is Sampling is not possible, and the start_clk signal is synchronously wrong. Let it be start_clk_wrong. It can be seen from Figure 9 that the counting result of the counter will decrease by one T _clk at this time. start_clk_wrong samples start_nclk to get the signal s_out_wrong=1, at this time, △T _start is 0ns, compared with the correct sampling s_out=0, △T _start reduces T _clk . Combined with △T=nT _clk - △T _start + △T _stop , it can be found that the error generated by △T _start is eliminated after being adjusted at nT _clk .

When start samples d[7:0] at position ② in Figure 4, the timing diagram of the metastable state elimination logic is shown in Figure 8. If the time interval between start and clk signals does not meet the D flip-flop setup time, it cannot be sampled, and the start_clk signal is synchronized Wrong, set it as start_clk_wrong, it can be seen from Figure 9 that the counting result of the counter will increase by one T _clk at this time. start_clk_wrong samples start_nclk to get the signal s_out_wrong=1, at this time, △T _start is T _clk , compared with the correct sampling s_out=0, △T _start increases T _clk . Combined with △T=nT _clk - △T _start + △T _stop , it can be found that the error generated by △T _start is eliminated after being adjusted at nT _clk .

In the same way: the error generated by △T _stop can also be eliminated, thereby eliminating the timing error caused by the occurrence of metastable state.

As shown in FIG. 10 and FIG. 11 , compared with a typical TDC, the TDC with a circuit that can eliminate the metastable state proposed by the present invention has better linearity, which greatly improves the reliability of the time quantization result.

Claims (1)

1. A metastability elimination circuit for TDC, the circuit consists of the first rising edge D flip-flop, the second rising edge D flip-flop, the third rising edge D flip-flop, the first falling edge D flip-flop and the first falling edge D flip-flop Two falling edge D flip-flops are formed; The D input terminal of the first rising edge D flip-flop is connected to an external input signal, its clock signal input terminal is connected to an external clock signal, and its Q output terminal is connected to the D input terminal of the second rising edge D flip-flop; the second rising edge D The clock signal input terminal of the flip-flop is connected to the external clock signal, and its Q output terminal is connected to the clock signal input terminal of the third rising edge D flip-flop; the D input terminal of the first falling edge flip-flop is connected to the external input signal, and its clock signal input terminal Connect the external clock signal, its Q output terminal is connected to the D input terminal of the second falling edge D flip-flop; the clock signal input terminal of the second falling edge D flip-flop is connected to the external clock signal, and its Q output terminal is connected to the third rising edge D trigger The D input terminal of the device; the first rising edge D flip-flop, the second rising edge D flip-flop, the first falling edge D flip-flop and the second falling edge D flip-flop are connected to the same external clock signal; the third rising edge The Q output end of the flip-flop is the output end of the metastable state elimination circuit; the metastable state elimination circuit is used to make the quantization result of the DLL have a clock cycle deviation after the TDC cannot sample correctly, and also give the counter A signal start_clk causes the count n to have a deviation of 1, and the generated count deviation and the clock cycle deviation are offset by two parts of the quantization error, which realizes the elimination of the sampling metastable state.