CN105187053B

CN105187053B - A kind of metastable state and eliminate circuit for TDC

Info

Publication number: CN105187053B
Application number: CN201510562858.1A
Authority: CN
Inventors: 甄少伟; 刘俐宏; 尤帅; 艾国润; 罗萍; 贺雅娟; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2015-09-07
Filing date: 2015-09-07
Publication date: 2017-12-22
Anticipated expiration: 2035-09-07
Also published as: CN105187053A

Abstract

The invention belongs to electronic circuit technology field, more particularly to a kind of metastable state and eliminate circuit for TDC.The circuit primary structure of the present invention is made up of the first rising edge d type flip flop, the second rising edge d type flip flop, the 3rd rising edge d type flip flop, the first trailing edge d type flip flop and the second trailing edge d type flip flop；The D input termination external input signals of the D inputs of first rising edge d type flip flop, the first trailing edge trigger；The Q output of second rising edge d type flip flop connects the clock signal input terminal of the 3rd rising edge d type flip flop；The Q output of second trailing edge d type flip flop connects the D inputs of the 3rd rising edge d type flip flop.Beneficial effects of the present invention are that while the result after ensureing that time figure quantifies has identical range and resolution ratio with traditional TDC, can effectively eliminate timing error caused by metastable state, greatly improve the reliability of TDC precision.

Description

A kind of metastable state and eliminate circuit for TDC

Technical field

The invention belongs to electronic circuit technology field, more particularly to a kind of metastable state and eliminate circuit for TDC.

Background technology

Time interval measurement technology suffers from largely applying in many fields.It not only Atomic Physics, laser ranging, Positioning timing etc., also had a wide range of applications in time interval measurement technology, automatic checkout equipment field；In addition, in state In anti-industry, as a kind of important discriminating and detection means, the requirement to precision is very strict, or even reaches for time interval measurement Picosecond magnitude is arrived.Therefore, high-precision TDC circuits play the role of important.

Typical digital time converter is quantified using DLL and counter two-layer configuration to the time.It thinks substantially Think it is that this period, TDC range between start signals rising edge and stop signal rising edges are measured by a clock count Mainly determined by rolling counters forward scope, and resolution ratio depends on DLL.A kind of typically TDC circuit diagrams based on this thought are such as Fig. 1, its timing diagram such as Fig. 2, thick value counter realize nT_clkTiming；Latch coding module and realize △ T_startWith △ T_stopTwo The timing divided；8 outputs that DLL is sampled to obtain by data processing module are encoded and the difference of two clocking portions are calculated Value ε=△ T_stop-△T_start, then give thick value counting module one carry signal c according to difference.Data processing module and thick value The timing of counter module two parts exports and into conversion time △ T, between start the and stop signal rising edges as to be measured Time interval.△ T=nT can be obtained by Fig. 2_clk-△T_start+△T_stop, wherein T_clkFor clock cycle, △ T_startWith △ T_stopFor The time measurement error of beginning and end, n are the count value of △ T inside counting devices.The transformed error that numeral is arrived between clocking is ε=△ T_stop-△T_start, △ T=nT can be obtained_clk+ε。

Fig. 3 is DLL circuit diagram, and ideally, clock is divided into 8 phases by DLL, when start signals arrive pair Each output phase sampling, its timing diagram such as Fig. 4.Actually due to reason meetings such as dutycycle distortion, signal jitter, delay distortions There is deviation, start is likely to occur metastable state in particular sample position.As shown in Figure 1, △ T_startCalculating only and d [7:0] upper Rise along relevant, it is contemplated that d [7 when start signals arrive:0] position of signal rising edge.2. 1. it is a pair of sampling locations, 3. 4. it is another pair sampling location.

There is foundation and retention time in d type flip flop during due to sampling, at 1. 2. position, start is to d [7:0] sample, Because d [7] is in the state of upset, it is possible to metastable state occur, cause sampled result mistake.So as to △ T_startBe possible to from T_clkTo 0ns saltus step；Or it is instead possible to from 0ns to T_clkSaltus step, cause TDC counting very big deviation occur.

Start 3. 4. position to d [7:When 0] sampling, because d [2] is in the state of upset, although Asia may also be produced Stable state, but correct value can be sampled in d [1] and d [3] place, so △ T_startThe error of only one phase, it can ignore Disregard.

The content of the invention

It is to be solved by this invention, aiming above mentioned problem, propose a kind of metastable state and eliminate circuit for TDC.

To achieve the above object, the present invention adopts the following technical scheme that：

A kind of metastable state and eliminate circuit for TDC, the circuit are triggered by the first rising edge d type flip flop, the second rising edge D Device, the 3rd rising edge d type flip flop, the first trailing edge d type flip flop and the second trailing edge d type flip flop are formed；

The D input termination external input signals of the first rising edge d type flip flop, when its clock signal input terminal connects outside Clock signal, its Q output connect the D inputs of the second rising edge d type flip flop；The clock signal input of second rising edge d type flip flop External timing signal is terminated, its Q output connects the clock signal input terminal of the 3rd rising edge d type flip flop；First trailing edge triggers The D input termination external input signals of device, its clock signal input terminal connect external timing signal, and its Q output connects the second decline Along the D inputs of d type flip flop；The clock signal input terminal of second trailing edge d type flip flop connects external timing signal, its Q output Connect the D inputs of the 3rd rising edge d type flip flop；The first rising edge d type flip flop, the second rising edge d type flip flop, first decline Along d type flip flop and the second trailing edge d type flip flop connection identical external timing signal；The Q output of 3rd rising edge flip-flops For the output end of metastable state and eliminate circuit.

Beneficial effects of the present invention are, the result after ensureing that time figure quantifies and traditional TDC have identical range and While resolution ratio, timing error caused by metastable state can be effectively eliminated, greatly improves the reliability of TDC precision.

Brief description of the drawings

Fig. 1 typical case's TDC circuit structures；

Fig. 2 is typical time period numeral transfer principle timing diagram；

Fig. 3 is DLL function structure charts；

Fig. 4 is that start particular samples are likely to occur metastable position view；

Fig. 5 is the logical construction schematic diagram of metastable state and eliminate circuit of the present invention；

Fig. 6 is the application drawing of metastable state and eliminate circuit of the present invention；

Fig. 7 is the 1. timing diagram of opening position during circuit of the present invention is Fig. 4 in sampling location；

Fig. 8 is the 2. timing diagram of opening position during circuit of the present invention is Fig. 4 in sampling location；

TDCs of the Fig. 9 containing structure of the present invention counter portion timing diagram；

Figure 10 is traditional TDC linearity degree schematic diagram；

Figure 11 is the TDC linearity degree schematic diagram using circuit structure of the present invention.

Embodiment

With reference to the accompanying drawings and examples, technical scheme is described in detail：

Timing caused by metastable state situation when the present invention uses DLL and counter quantization time interval for the traditional TDC of elimination Error, it with the addition of metastable state eliminates logic circuit.The TDC after metastable state is eliminated as typical TDC precision, unique difference exists In when start is when 1. 2. position samples Fig. 4, typical TDC is likely to correctly to sample, and makes quantized result more correct As a result there is the deviation of a clock cycle, be very serious deviation.And increase the circuit after metastable state eliminates logic can not DLL quantized result has the deviation of a clock cycle after correct sampling, while can also give one signal start_ of counter Clk, counting n is set also to produce deviation 1, as shown in figure 9, wherein start_clk is start caused letters after edge synchronization Number；Stop_clk is stop caused signals after edge synchronization；Start_stop is that start_clk and stop_clk passes through Caused signal after enabled module, the enable signal as counter；Clk_dealy is signals of the clk by delay；gated_ Clk_delay is that start_stop and clk_dealy is inputted with signal behind the door by two, the count signal as counter. Due to n and △ T caused by the sampling of start metastable states_startTwo parts quantization error counteracts, it is achieved thereby that start samplings are sub- The elimination of stable state.

The structure of the present invention as shown in figure 5, wherein start_clk is start caused signals after rising edge synch, Start_nclk is start caused signals after trailing edge synchronization, and Q_nclk is that clock falling edge samples output to start Signal, output s_out is circuit judges result.

The structure of the present invention as shown in figure 5, the circuit by the first rising edge d type flip flop, the second rising edge d type flip flop, the Three rising edge d type flip flops, the first trailing edge d type flip flop and the second trailing edge d type flip flop are formed；The first rising edge D triggerings The D input termination external input signals of device, its clock signal input terminal connect external timing signal, and its Q output connects the second rising Along the D output ends of d type flip flop；The clock signal input terminal of second rising edge d type flip flop connects external timing signal, its Q output Connect the clock signal input terminal of the 3rd rising edge d type flip flop；The D input termination external input signal t of first trailing edge trigger, Its clock signal input terminal connects external timing signal, and its Q output connects the D inputs of the second trailing edge d type flip flop；Second declines External timing signal is connect along the clock signal input terminal of d type flip flop, its Q output connects the D inputs of the 3rd rising edge d type flip flop End；The first rising edge d type flip flop, the second rising edge d type flip flop, the first trailing edge d type flip flop and the second trailing edge D triggerings Device connects identical external timing signal；The Q output of 3rd rising edge flip-flops is the output end of metastable state and eliminate circuit.

The operation principle of this example is：

As shown in figure 4, sampling location 1. or 2. when, be not in d [x:X-1]=01 (x=6~1) situation.Then scheme In 6 thus sampling location judge module distinguishes whether external input signal start (or stop) sampling location in Fig. 4 occurs 1. or 2..1. or 2. when judging sampling location when, encoder using the output signal s_out of metastable state and eliminate circuit knot Fruit encodes, that is, works as s_out=0, △ T_startIt is entered as T_clk；S_out=1, △ T_startIt is entered as 0ns.Otherwise, encoder is normal Coding, is not influenceed by s_out.

When 1. start samples d [7 in Fig. 4 positions:When 0], metastable state eliminates logic its timing diagram such as Fig. 7, if outside input Signal start is unsatisfactory for d type flip flop settling time with external timing signal clk signal time interval, i.e., can not sample, start_ Clk signal timing error, if it is start_clk_wrong, now rolling counters forward result can reduce one as shown in Figure 9 T_clk.Start_clk_wrong samplings start_nclk obtains signal s_out_wrong=1, this seasonal △ T_startFor 0ns, compared with During correct sampling s_out=0, △ T_startReduce T_clk.With reference to △ T=nT_clk-△T_start+△T_stopIt can be found that △ T_start Caused error is by nT_clkIt is eliminated after place's adjustment.

When 2. start samples d [7 in Fig. 4 positions:When 0], metastable state eliminates logic its timing diagram such as Fig. 8, if start with Clk signal time interval is unsatisfactory for d type flip flop settling time, i.e., can not sample, start_clk signal timing errors, if it is Start_clk_wrong, now rolling counters forward result can increase a T as shown in Figure 9_clk.Start_clk_wrong is sampled Start_nclk obtains signal s_out_wrong=1, this seasonal △ T_startFor T_clk, when relatively correctly sampling s_out=0, △ T_startAdd T_clk.With reference to △ T=nT_clk-△T_start+△T_stopIt can be found that △ T_startCaused error is by nT_clkAdjust at place It is eliminated after whole.

Similarly：△T_stopCaused error can be also eliminated, so as to eliminate due to timing caused by metastable appearance Error.

As shown in Figure 10 and Figure 11, the TDC linearity of metastable state circuit can be eliminated compared to typical TDC, band proposed by the present invention Degree is more preferable, greatly improves the reliability of time quantization result.

Claims

1. a kind of metastable state and eliminate circuit for TDC, the circuit is triggered by the first rising edge d type flip flop, the second rising edge D Device, the 3rd rising edge d type flip flop, the first trailing edge d type flip flop and the second trailing edge d type flip flop are formed；

The D input termination external input signals of the first rising edge d type flip flop, its clock signal input terminal connect external clock letter Number, its Q output connects the D inputs of the second rising edge d type flip flop；The clock signal input terminal of second rising edge d type flip flop connects External timing signal, its Q output connect the clock signal input terminal of the 3rd rising edge d type flip flop；The D of first trailing edge trigger Input termination external input signal, its clock signal input terminal connect external timing signal, and its Q output meets the second trailing edge D and touched Send out the D inputs of device；The clock signal input terminal of second trailing edge d type flip flop connects external timing signal, and its Q output connects the 3rd The D inputs of rising edge d type flip flop；The first rising edge d type flip flop, the second rising edge d type flip flop, the first trailing edge D are touched Send out device and the second trailing edge d type flip flop connection identical external timing signal；The Q output of 3rd rising edge flip-flops is metastable State eliminates the output end of circuit；The metastable state and eliminate circuit is used for after TDC can not be sampled correctly, makes DLL quantized result The deviation of a clock cycle is had, while can also give one signal start_clk of counter, counting n is also produced deviation 1, And caused counting deviation is offset with clock cycle deviation two parts quantization error, the metastable elimination of sampling is realized.