CN105675981A - FPGA-based frequency meter and frequency measuring method - Google Patents
FPGA-based frequency meter and frequency measuring method Download PDFInfo
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Abstract
The application provided a FPGA (Field-Programmable Gate Array)-based frequency meter and a frequency measuring method. The frequency meter comprises a clock source, a host computer, a frequency division shaping unit and a processing unit. The frequency meter utilizes the processing unit to perform once rough time measurement on the rising edge of a signal to be measured corresponding to the rising edge of a frequency division signal in each period of the frequency division signal to obtain a first time value, and utilizes the processing unit to perform multiple fine time measurement on the rising edge of the signal to be measured corresponding to the rising edge of a frequency division signal in each period of the frequency division signal, processes the measuring results of the first time value and the multiple fine time measurement, and obtains the frequency of an external original signal based on a first frequency division multiple and a second frequency division multiple. According to the multiple fine time measurement in the frequency measurement process of a whole external original signal, fine time measurement errors are reduced, and the frequency meter measurement precision on the external original signal frequency is improved.
Description
Technical field
The application relates to signal measurement technique field, more particularly, it relates to a kind of frequency based on FPGA takes into account frequency measurement method.
Background technology
Frequency measurement, in the fields such as daily life, work and scientific research, is one of most basic parameter. Along with development and the social demand of science and technology, particularly in wireless communication field and electronic technology field, people are more and more higher for the requirement of frequency measurement accuracy. The high-acruracy survey to frequency of main flow generally adopts measure of time method now, to lower frequency, measured signal frequency dividing is obtained fractional frequency signal, several fractional frequency signal cycles carry out thick time and the time interval measurement of thin time; Calculate then in conjunction with total frequency dividing multiple and obtain the measured signal cycle, obtain the frequency of measured signal finally by the method asking the measured signal cycle reciprocal. Wherein, for the lifting of the precision of fine measurement, it it is the key obtaining improving the frequency measurement accuracy of measured signal.
Generally by the special IC (ApplicationSpecificIntegratedCircuit customized in prior art, or field programmable gate array (Field-ProgrammableGateArray ASIC), FPGA) cymometer with frequency measurement function is realized as acp chip, by adopting analog interpolation or delay line interpolation or vernier method etc. to realize the accurate measurement of thin time interval; Wherein adopt analog interpolation and vernier method etc. that the certainty of measurement of thin interval is higher than the delay line interpolation adopted based on the FPGA cymometer realized based on the ASIC cymometer realized. But the cymometer that customization ASIC realizes frequency measurement is long compared to the cymometer construction cycle realizing frequency measurement based on FPGA design, complex circuit designs, and cost is high. Therefore, one of frequency measurement accuracy direction becoming research staff's effort how improving the cymometer based on FPGA.
Summary of the invention
For solving above-mentioned technical problem, the invention provides a kind of frequency based on FPGA and take into account frequency measurement method, to realize improving the purpose of the frequency measurement accuracy of the cymometer based on FPGA.
For realizing above-mentioned technical purpose, embodiments provide following technical scheme:
A kind of cymometer based on FPGA, described cymometer includes: clock source, host computer, frequency dividing shaping unit and processing unit;
Described clock source is connected with the clock signal input terminal of described processing unit, for providing clock signal for described processing unit;
Described frequency dividing shaping unit is used for receiving extraneous primary signal, and it is divided after multiple carries out scaling down processing with first obtains measured signal;
The operating clock signals that described processing unit generates for utilizing described clock signal is as clock reference, carry out scaling down processing with the second frequency dividing multiple to measured signal and obtain fractional frequency signal, and the described fractional frequency signal cycle is utilized measure of time method, with the measured signal rising edge corresponding with described fractional frequency signal rising edge for object, carry out repeatedly fine measurement obtain measurement result and once thick measure of time obtain very first time value, in conjunction with the described first frequency dividing multiple and the second described extraneous primary signal of frequency dividing multiple calculating, and by the frequency of described extraneous primary signal to described host computer transmission,
Described processing unit is arranged in on-site programmable gate array FPGA.
Preferably, described processing unit includes clock module, frequency division module, management module, thick counting module, fine measurement module, calculation process module and communication module; Wherein,
Described clock module is used for receiving described clock signal, obtaining operating clock signals after described clock signal is processed, described operating clock signals is as the clock reference of described management module, thick counting module, fine measurement module and calculation process module;
Described management module controls function for providing for described fine measurement module, thick counting module, calculation process module and communication module and selects control signal and pendulous frequency control signal for providing for described fine measurement module;
Described frequency division module obtains fractional frequency signal for described measured signal carries out scaling down processing, and the described fractional frequency signal cycle is the interval that described measure of time method is measured, and described fractional frequency signal is the beginning control signal of this measurement;
Described fine measurement module is used for utilizing described measured signal, fractional frequency signal, selection control signal and pendulous frequency control signal to generate enable signal and to described thick counting module and manages module transmission, and the measured signal rising edge corresponding with fractional frequency signal rising edge is carried out repeatedly fine measurement within each fractional frequency signal cycle, and measurement result is sent to described calculation process module;
Described thick counting module, for the control in conjunction with described enable signal, operating clock signals and management module, carries out once thick measure of time to measured signal within each fractional frequency signal cycle and obtains very first time value, and be transferred to described calculation process module;
Described calculation process module is for receiving the measurement result of described very first time value and repeatedly fine measurement, and calculate, in conjunction with the first frequency dividing multiple of described frequency dividing shaping unit and the second frequency dividing multiple of described frequency division module, the frequency obtaining described extraneous primary signal, and by described communication module to described host computer transmission;
Described second frequency dividing multiple is equal to the rising edge number of described measured signal in gate time.
Preferably, described calculation process module is for receiving the measurement result of described very first time value and repeatedly fine measurement, and calculates, in conjunction with the first frequency dividing multiple of described frequency dividing shaping unit and the second frequency dividing multiple of described frequency division module, the frequency obtaining described external world primary signal and include:
After described calculation process module receives the measurement result of described very first time value and repeatedly fine measurement, the measurement result of described repeatedly fine measurement is carried out computing and obtains the second time value, utilize described very first time value and the second time value to calculate and obtain the measured signal forward position moment corresponding with fractional frequency signal forward position in the fractional frequency signal cycle, and combine in fractional frequency signal cycle adjacent with this fractional frequency signal cycle and measured signal forward position moment that fractional frequency signal forward position is corresponding is calculated, it is thus achieved that the described fractional frequency signal cycle;By the described fractional frequency signal cycle divided by the described first cycle dividing multiple and the second frequency dividing multiple described measured signal of acquisition, and the cycle of described measured signal is carried out inverted computing, it is thus achieved that the frequency of described extraneous primary signal.
Preferably, described fine measurement module includes: concussion ring, d type flip flop group, the second d type flip flop and decoder; Described concussion ring includes MUX, time delay chain and phase inverter; Wherein,
Described MUX is the selector of a two-way, its first signal input part is used for receiving described measured signal, control signal input is used for receiving described selection control signal, the signal output part of described MUX is connected with the signal input part of described time delay chain, the signal output part of described time delay chain is connected with the signal input part of described phase inverter, the signal output part of described phase inverter is connected with the secondary signal input of described MUX, described MUX for controlling to enter the signal of described time delay chain under the control of described selection control signal,
Described time delay chain, for the measured signal received is carried out delay transport, is made up of the carry chain of FPGA internal additions device, and the non-linear time delay between carry chain unit is demarcated by code density method, and each delay cell rear end has tap;
Described phase inverter is for overturning the measured signal edge state that time delay chain exports, signal rising edge is made to return to original state after phase inverter at twice, when secondary signal input is received outfan by described MUX under the control of described selection control signal, it forms the concussion ring of time delay chain-phase inverter-MUX-time delay chain, measured signal rising edge earthquake ring transmits, adjacent two rising edges arrive the time difference of time delay chain, are the cycle of oscillation of signal;
Described d type flip flop group includes multiple d type flip flop, and its signal input part is connected with the tap of each delay unit rear end of time delay chain successively, and clock termination receives described operating clock signals, thus operationally clock rising edge latches time delay chain state when arriving; Signal output part is connected with decoder, carries out decoding process for the state of latch is sent to decoder; The first d type flip flop of described d type flip flop group is the first d type flip flop, and the signal output part of described first d type flip flop is simultaneously coupled to described second d type flip flop input; Described first d type flip flop exports the first signal to described second d type flip flop; Obtaining secondary signal after the output signal of described second d type flip flop is carried out negated computing, described first signal, secondary signal and described fractional frequency signal and pendulous frequency control signal carry out obtaining described enable signal and to described decoder and thick counting module transmission with logical operations;
Described decoder is for, under the triggering of described enable signal, carrying out decoding process to described latch result, it is thus achieved that described measurement result;
Described d type flip flop group and decoder, namely for, after measured signal forward position enters time delay chain, under the control enabling signal, its positional information in time delay chain being converted to fine measurement result.
Preferably, described repeatedly fine measurement, by forming described concussion ring, adopts multi-times measurement method to realize, wherein:
Described concussion ring is after described measured signal enters described time delay chain by described MUX the first signal input part, by changing the selection control signal of described MUX control signal input, the secondary signal input of described MUX is accessed described time delay chain, the measured signal exported from described time delay chain is made to be again introduced into time delay chain after described phase inverter rollover states and described MUX, described measured signal rising edge again becomes rising edge after twice rollover states and is input in time delay chain, described decoder is under the control of described enable signal, carry out decoding and obtain fine measurement result, can realize within a fractional frequency signal cycle, repeatedly fine measurement is carried out for same measured signal rising edge, it is then passed through calculating and obtains more accurate fine measurement result, this is the multi-times measurement method of further improving measurement accuracy.
Preferably, described thick counting module is for the control in conjunction with described enable signal, operating clock signals and management module, within each fractional frequency signal cycle, carry out once thick measure of time to measured signal obtain very first time value, and be transferred to described calculation process module and include:
Described thick counting module is started working under the control of described management module, within each fractional frequency signal cycle, the rising edge of described operating clock signals is carried out counting and obtains count results, the cycle of described count results Yu described operating clock signals is carried out product calculation and obtains described very first time value, and when described enable signal is high level, described very first time value is sent to described calculation process module detecting.
Preferably, described thick counting module is the enumerator being operated under described system working clock reference.
Preferably, described clock source is atomic clock or crystal oscillator.
A kind of frequency measurement method, is applied to the cymometer described in any of the above-described embodiment, and described frequency measurement method includes:
Send instruction by host computer to the processing unit of described cymometer, start primary signal to external world and carry out frequency measurement;
Described cymometer is carried out Initialize installation;
Utilize described cymometer that described extraneous primary signal is carried out once slightly measure of time and repeatedly fine measurement, the measurement result the first frequency dividing multiple in conjunction with described cymometer and the second frequency dividing multiple are calculated obtaining the frequency of described extraneous primary signal, and send host computer to.
From technique scheme it can be seen that embodiments provide a kind of frequency based on FPGA to take into account frequency measurement method, wherein, described cymometer includes: clock source, host computer, frequency dividing shaping unit and processing unit; Described cymometer obtains very first time value by utilizing processing unit that the measured signal rising edge corresponding with fractional frequency signal rising edge carries out once thick measure of time within each cycle of described fractional frequency signal; And the measured signal rising edge utilizing processing unit pair corresponding with fractional frequency signal rising edge carries out repeatedly fine measurement within each cycle of described fractional frequency signal, the measurement result of described very first time value and repeatedly fine measurement is processed and divides multiple in conjunction with described first and described second frequency dividing multiple calculates the frequency obtaining described extraneous primary signal. Owing to having carried out repeatedly fine measurement in the frequency measuring process of whole extraneous primary signal, reduce the error of fine measurement, improve the certainty of measurement of described cymometer original signal frequency to external world.
And described cymometer adopts external clock source to provide clock signal for the processing unit being arranged in FPGA, have the advantages that precision and stability is high compared to FPGA self clock that can provide, thus improving the reliability and stability that described cymometer is measured for extraneous original signal frequency.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to the accompanying drawing provided.
The structural representation of a kind of cymometer based on FPGA that the embodiment that Fig. 1 is the application provides;
The structural representation of a kind of cymometer based on FPGA that the preferred embodiment that Fig. 2 is the application provides;
The sequential chart utilizing measure of time method to carry out thick time and fine measurement to measured signal that the embodiment that Fig. 3 is the application provides;
The structural representation of a kind of cymometer based on FPGA that another preferred embodiment that Fig. 4 is the application provides;
What the embodiment that Fig. 5 is the application provided enables the sequential chart of signal, operating clock signals, measured signal, selection control signal, the output signal of MUX signal output part, the first d type flip flop signal output part signal, the second d type flip flop signal output part signal, fractional frequency signal, pendulous frequency control signal;
The schematic flow sheet of a kind of frequency measurement method that the embodiment that Fig. 6 is the application provides.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments. Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
This application provides a kind of cymometer based on FPGA, as it is shown in figure 1, described cymometer includes: clock source 100, host computer 400, frequency dividing shaping unit 300 and processing unit 200;
Described clock source 100 is connected with the clock signal input terminal of described processing unit 200, for providing clock signal for described processing unit 200;
Described frequency dividing shaping unit 300 is used for receiving extraneous primary signal, and it is divided after multiple carries out scaling down processing with first obtains measured signal;
The operating clock signals that described processing unit 200 is used for utilizing described clock signal to generate is as clock reference, carry out scaling down processing with the second frequency dividing multiple to measured signal and obtain fractional frequency signal, and the described fractional frequency signal cycle is utilized measure of time method, with the measured signal rising edge corresponding with described fractional frequency signal rising edge for object, carry out repeatedly fine measurement obtain measurement result and once thick measure of time obtain very first time value, in conjunction with the described first frequency dividing multiple and the second described extraneous primary signal of frequency dividing multiple calculating, and the frequency of described extraneous primary signal is transmitted to described host computer 400,
Described processing unit 200 is arranged in on-site programmable gate array FPGA.
It should be noted that, field programmable gate array (Field-ProgrammableGateArray, FPGA) it is the chip of the repeatable programming of a kind of hardware, the repeatable programming of FPGA is not only embodied in the function of internal logic unit can field reconfigurable, its I/O pin and work clock distribution can redefine, and therefore control device based on the nuclear magnetic resonance spectrometer of FPGA and have the advantages such as cost is low, integrated level is high, flexible configuration. And in the present embodiment, it is only necessary to just go for different demands to FPGA code is slightly modified, without the amendment made on any hardware, meanwhile, its development process and difficulty, customization ASIC circuit also comparatively simplifies relatively. In an embodiment of the application, the model of described FPGA is Virtex-7, having only to take its internal little stock number with described Virtex-7FPGA for the cymometer that acp chip realizes and just can realize complete cymometer function, its cost is far below other high-precision cymometers on the market. Meanwhile, its construction cycle is short, and development cost to be substantially reduced compared to customization ASIC circuit.
Also, it should be noted owing to having carried out repeatedly fine measurement in the frequency measuring process of whole extraneous primary signal, reduce the error of fine measurement, improve the certainty of measurement of described cymometer original signal frequency to external world. And described cymometer adopts external clock source 100 to provide clock signal for the processing unit 200 being arranged in FPGA, have the advantages that precision and stability is high compared to FPGA self clock that can provide, thus improving the reliability and stability that described cymometer is measured for extraneous original signal frequency.
On the basis of above-described embodiment, in an embodiment of the application, as in figure 2 it is shown, described processing unit 200 includes clock module 220, frequency division module 230, management module 240, thick counting module 250, fine measurement module 210, calculation process module 260 and communication module 270;Wherein,
Described clock module 220 is used for receiving described clock signal, obtaining operating clock signals after described clock signal is processed, described operating clock signals is as the clock reference of described management module 240, thick counting module 250, fine measurement module 210 and calculation process module 260;
Described management module 240 controls function for providing for described fine measurement module 210, thick counting module 250, calculation process module 260 and communication module 270 and selects control signal and pendulous frequency control signal for providing for described fine measurement module 210;
Described frequency division module 230 obtains fractional frequency signal for described measured signal carries out scaling down processing, and the described fractional frequency signal cycle is the interval that described measure of time method is measured, and described fractional frequency signal is the beginning control signal of this measurement;
Described fine measurement module 210 is used for utilizing described measured signal, fractional frequency signal, selection control signal and pendulous frequency control signal to generate enable signal and transmits to described thick counting module 250 and management module 240, and the measured signal rising edge corresponding with fractional frequency signal rising edge is carried out repeatedly fine measurement within each fractional frequency signal cycle, and measurement result is sent to described calculation process module 260;
Described thick counting module 250 is for the control in conjunction with described enable signal, operating clock signals and management module, within each fractional frequency signal cycle, carry out once thick measure of time to measured signal obtain very first time value, and be transferred to described calculation process module 260;
Described calculation process module 260 is for receiving the measurement result of described very first time value and repeatedly fine measurement, and calculated, in conjunction with the first frequency dividing multiple of described frequency dividing shaping unit 300 and the second frequency dividing multiple of described frequency division module 230, the frequency obtaining described extraneous primary signal, and passed through described communication module 270 and transmitted to described host computer 400;
Described second frequency dividing multiple is equal to the rising edge number of described measured signal in gate time.
It should be noted that, in the present embodiment, for the extraneous primary signal to any unknown frequency, stablizing of its gate time can both be ensured when described cymometer proceeds by frequency measurement, need described cymometer is carried out Initialize installation, divide, by described second, the rising edge number that multiple is set in gate time described measured signal.
Concrete method to set up includes: in record standard clock gate time, the counting n of described frequency division module 230, this is the frequency dividing multiple (namely described second frequency dividing multiple) of measured signal, during measurement, the frequency dividing multiple of frequency division module 230 is adjusted to n, then the fractional frequency signal cycle produced is just near gate time.
In addition repeatedly the concrete number of times adjustment of fine measurement can pass through the debugging to FPGA and written in code realization, it is also possible to sends instruction by host computer 400 and realizes. The concrete time number adjusting method of described fine measurement is not limited by the application, specifically depending on practical situation.
Also, it should be noted the application specific embodiment describes and utilizes the principle that measure of time method carries out thick time and fine measurement to be to measured signal illustrated, as it is shown on figure 3, convenient in order to represent, in accompanying drawing 3, the second frequency dividing multiple is set to 3. In the present embodiment, measure if, with operating clock signals, it is all generally then use an enumerator, record the operating clock signals periodicity N1 and operating clock signals periodicity N2 of position as shown in the figure, then N2 and N1 is poor, obtain their difference, described difference and operating clock cycle are carried out product calculation, the result T3 of thick measure of time can be obtained.But it can be seen that, also having very big error between the result T3 and time total linear spacing T of thick measure of time, so needing to carry out fine measurement, measuring the value of number in the figure T1 and T2, then result T3 and the T1 utilizing thick measure of time is added and deducts T2 again, can obtain total linear spacing T of described time. Described above is used merely to explain after utilizing measure of time method to carry out the thick time, in addition it is also necessary to carry out the necessity of fine measurement, is not that the cymometer based on FPGA that the embodiment of the present application provides carries out the concrete principle of frequency measurement.
On the basis of above-described embodiment, in another embodiment of the application, described calculation process module 260 is for receiving the measurement result of described very first time value and repeatedly fine measurement, and calculates, in conjunction with the first frequency dividing multiple of described frequency dividing shaping unit 300 and the second frequency dividing multiple of described frequency division module 230, the frequency obtaining described external world primary signal and include:
After described calculation process module 260 receives the measurement result of described very first time value and repeatedly fine measurement, the measurement result of described repeatedly fine measurement is carried out computing and obtains the second time value, utilize described very first time value and the second time value to calculate and obtain the measured signal forward position moment corresponding with fractional frequency signal forward position in the fractional frequency signal cycle, and combine in fractional frequency signal cycle adjacent with this fractional frequency signal cycle and measured signal forward position moment that fractional frequency signal forward position is corresponding is calculated, it is thus achieved that the described fractional frequency signal cycle; By the described fractional frequency signal cycle divided by the described first cycle dividing multiple and the second frequency dividing multiple described measured signal of acquisition, and the cycle of described measured signal is carried out inverted computing, it is thus achieved that the frequency of described extraneous primary signal.
On the basis of above-described embodiment, in another embodiment of the application, as shown in Figure 4, described fine measurement module 210 includes: concussion ring (not marking label in accompanying drawing 4), d type flip flop group the 214, second d type flip flop 2 and decoder 215; Described concussion ring includes MUX 211, time delay chain 213 and phase inverter 212; Wherein,
Described MUX 211 is the selector of a two-way, its first signal input part is used for receiving described measured signal, control signal input is used for receiving described selection control signal, the signal output part of described MUX 211 is connected with the signal input part of described time delay chain 213, the signal output part of described time delay chain 213 is connected with the signal input part of described phase inverter 212, the signal output part of described phase inverter 212 is connected with the secondary signal input of described MUX 211, described MUX 211 for controlling to enter the signal of described time delay chain 213 under the control of described selection control signal,
Described time delay chain 213, for the measured signal received is carried out delay transport, is made up of the carry chain of FPGA internal additions device, and the non-linear time delay between carry chain unit is demarcated by code density method, and each delay cell rear end has tap;
Described phase inverter 212 overturns for the measured signal edge state exported by time delay chain 213, signal rising edge is made to return to original state at twice after phase inverter 212, when secondary signal input is received outfan by described MUX 211 under the control of described selection control signal, it forms the concussion ring of time delay chain-phase inverter-MUX-time delay chain, measured signal rising edge earthquake ring transmits, adjacent two rising edges arrive the time difference of time delay chain, are the cycle of oscillation of signal;
Described d type flip flop group includes multiple d type flip flop, and its signal input part is connected with the tap of each delay unit rear end of time delay chain 213 successively, and clock termination receives described operating clock signals, thus operationally clock rising edge latches time delay chain 213 state when arriving; Signal output part is connected with decoder, carries out decoding process for the state of latch is sent to decoder; The first d type flip flop of described d type flip flop group is the first d type flip flop, and the signal output part of described first d type flip flop is simultaneously coupled to described second d type flip flop input; Described first d type flip flop exports the first signal to described second d type flip flop; Obtaining secondary signal after the output signal of described second d type flip flop is carried out negated computing, described first signal, secondary signal and described fractional frequency signal and pendulous frequency control signal carry out obtaining described enable signal and to described decoder and thick counting module transmission with logical operations;
Described decoder is for, under the triggering of described enable signal, carrying out decoding process to described latch result, it is thus achieved that described measurement result;
Described d type flip flop group and decoder, namely for, after measured signal forward position enters time delay chain 213, under the control enabling signal, its positional information in time delay chain 213 being converted to fine measurement result.
In the present embodiment, described enable signal, operating clock signals, measured signal, selection control signal, MUX 211 signal output part output signal, the first d type flip flop 1 signal output part signal, the second d type flip flop 2 signal output part signal, fractional frequency signal, pendulous frequency control signal sequential chart as shown in Figure 5.
It should be noted that assuming in accompanying drawing 5 for the fine measurement number of times of measured signal is 3 times. In the present embodiment, fine measurement module 210 receives measured signal, is within it input in time delay chain 213 by MUX 211, and the state of time delay chain 213 is latched by the rising edge of described d type flip flop group 214 operationally clock signal. When enabling signal and being high level, the state that d type flip flop group 214 is latched time delay chain 213 by decoder 215 decodes, and obtains described measurement result.
Also, it should be noted in the present embodiment, when arriving in measured signal forward position, described selection control signal is set to low level, selects measured signal to be input in time delay chain 213; When an operating clock signals rising edge thereafter arrives, described selection control signal is set to high level, the signal access delay chain 213 of described phase inverter 212 outfan that described secondary signal input is received by described MUX 211. When pendulous frequency reaches setting value, the measurement in this measured signal pulse signal forward position being terminated, select control signal to be again set to high level, described time delay chain 213 starts to receive measured signal.
On the basis of above-described embodiment, in a preferred embodiment of the application, described repeatedly fine measurement, by forming described concussion ring, adopts multi-times measurement method to realize, wherein:
Described concussion ring is after described measured signal enters described time delay chain 213 by described MUX 211 first signal input part, by changing the selection control signal of described MUX 211 control signal input, the secondary signal input of described MUX 211 is accessed described time delay chain 213, the measured signal from the output of described time delay chain 213 is made to be again introduced into time delay chain 213 after described phase inverter 212 rollover states and described MUX 211, described measured signal rising edge again becomes rising edge after twice rollover states and is input in time delay chain 213, described decoder 215 is under the control of described enable signal, carry out decoding and obtain fine measurement result, can realize within a fractional frequency signal cycle, repeatedly fine measurement is carried out for same measured signal rising edge, it is then passed through calculating and obtains more accurate fine measurement result, this is the multi-times measurement method of further improving measurement accuracy.
It should be noted that the multi-times measurement method of the present invention, the method in one measured signal forward position of single time delay chain 213 channel cycle repetitive measurement realizing, effectively reduce the occupancy of FPGA resource, global design is lower in cost.
In repetitive measurement process, as it is shown in figure 5, the operating clock signals cycle is Tclk, the cycle of oscillation of concussion ring is Tosc, the time delay of each delay unit of carry chain is Tcell。ToscValue it is known that assume that it is (k*Tclk+T0), T herein0It is the measured signal forward position being again introduced in time delay chain after concussion ring, the time that its advanced position is moved rearwards by. Therefore measure the value of signal leading edge in concussion ring with the m time (m is less than the fine measurement number of times set), deduct m T0Value, it is the position in measured signal forward position first time entrance time delay chain 213, by said method, this advanced position obtained after repetitive measurement computing being averaged, can obtain more accurate fine measurement result, this is namely for the multi-times measurement method of thin time. As T cycle of oscillationoscIt is not TcellIntegral multiple time, may certify that in theory, the minimum time unit of its measurement is Tcell1/n (n be set fine measurement number of times), say, that in an ideal case, the temporal resolution of the fine measurement of described cymometer is by n decile, and its temporal resolution improves n times.
On the basis of above-described embodiment, in the further embodiment of the application, described thick counting module 250 is for the control in conjunction with described enable signal, operating clock signals and management module 240, within each fractional frequency signal cycle, carry out once thick measure of time to measured signal obtain very first time value, and be transferred to described calculation process module 260 and include:
Described thick counting module 250 is started working under the control of described management module 240, within each fractional frequency signal cycle, the rising edge of described operating clock signals is carried out counting and obtains count results, the cycle of described count results Yu described operating clock signals is carried out product calculation and obtains described very first time value, and when described enable signal is high level, described very first time value is sent to described calculation process module 260 detecting.
On the basis of above-described embodiment, in a preferred embodiment of the application, described thick counting module 250 is the enumerator being operated under described system working clock reference.
On the basis of above-described embodiment, in another preferred embodiment of the application, described clock source 100 is atomic clock or crystal oscillator. In an embodiment of the application, described clock source 100 is SRSFS725 type atomic clock, but the concrete part category that described clock source 100 is adopted by the application does not limit, if the stable clock signal that can provide, specifically depending on practical situation.
On the basis of above-described embodiment, in an embodiment of the application, described frequency dividing shaping unit selects two frequency divider of RF-BAYFPS-10-12 (10 frequency dividing) and FPS-120-4 (120 frequency dividing) model as core simultaneously, achieve the frequency measurement of dynamic range 100Hz-12GHz, temporal resolution 10ps. When gate time is 1s, the certainty of measurement of described cymometer has reached 0.01ppb.
Accordingly, present invention also provides a kind of frequency measurement method, be applied to the cymometer described in any of the above-described embodiment, as shown in Figure 6, described frequency measurement method includes:
S101: send instruction to the processing unit 200 of described cymometer by host computer 400, starts primary signal to external world and carries out frequency measurement;
S102: described cymometer is carried out Initialize installation;
S103: utilize described cymometer that described extraneous primary signal is carried out once slightly measure of time and repeatedly fine measurement, the measurement result the first frequency dividing multiple in conjunction with described cymometer and the second frequency dividing multiple are calculated obtaining the frequency of described extraneous primary signal, and send host computer 400 to.
It should be noted that in the present embodiment, perform step 102, in order that extraneous primary signal to any unknown frequency, can both ensure stablizing of its gate time when described cymometer proceeds by frequency measurement. Described cymometer is carried out the rising edge number that Initialize installation is set in gate time measured signal by the second frequency dividing multiple of described cymometer.
In sum, the embodiment of the present application provides a kind of frequency based on FPGA and takes into account frequency measurement method, and wherein, described cymometer includes: clock source 100, host computer 400, frequency dividing shaping unit 300 and processing unit 200; Described cymometer obtains very first time value by utilizing processing unit 200 that the measured signal rising edge corresponding with fractional frequency signal rising edge carries out once thick measure of time within each cycle of described fractional frequency signal; And utilize processing unit 200 that the measured signal rising edge corresponding with fractional frequency signal rising edge is carried out repeatedly fine measurement within each cycle of described fractional frequency signal, the measurement result of described very first time value and repeatedly fine measurement is processed and divides multiple in conjunction with described first and described second frequency dividing multiple calculates the frequency obtaining described extraneous primary signal. Owing to having carried out repeatedly fine measurement in the frequency measuring process of whole extraneous primary signal, reduce the error due to fine measurement, improve the certainty of measurement of described cymometer original signal frequency to external world.
And described cymometer adopts external clock source 100 to provide clock signal for the processing unit 200 being arranged in FPGA, have the advantages that precision and stability is high compared to FPGA self clock that can provide, thus improving the reliability and stability that described cymometer is measured for extraneous original signal frequency.
In this specification, each embodiment adopts the mode gone forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually referring to.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention. The multiple amendment of these embodiments be will be apparent from for those skilled in the art, and generic principles defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments. Therefore, the present invention is not intended to be limited to the embodiments shown herein, and is to fit to the widest scope consistent with principles disclosed herein and features of novelty.
Claims (9)
1. the cymometer based on FPGA, it is characterised in that described cymometer includes: clock source, host computer, frequency dividing shaping unit and processing unit;
Described clock source is connected with the clock signal input terminal of described processing unit, for providing clock signal for described processing unit;
Described frequency dividing shaping unit is used for receiving extraneous primary signal, and it is divided after multiple carries out scaling down processing with first obtains measured signal;
The operating clock signals that described processing unit generates for utilizing described clock signal is as clock reference, carry out scaling down processing with the second frequency dividing multiple to measured signal and obtain fractional frequency signal, and the described fractional frequency signal cycle is utilized measure of time method, with the measured signal rising edge corresponding with described fractional frequency signal rising edge for object, carry out repeatedly fine measurement obtain measurement result and once thick measure of time obtain very first time value, in conjunction with the described first frequency dividing multiple and the second described extraneous primary signal of frequency dividing multiple calculating, and by the frequency of described extraneous primary signal to described host computer transmission,
Described processing unit is arranged in on-site programmable gate array FPGA.
2. cymometer according to claim 1, it is characterised in that described processing unit includes clock module, frequency division module, management module, thick counting module, fine measurement module, calculation process module and communication module; Wherein,
Described clock module is used for receiving described clock signal, obtaining operating clock signals after described clock signal is processed, described operating clock signals is as the clock reference of described management module, thick counting module, fine measurement module and calculation process module;
Described management module controls function for providing for described fine measurement module, thick counting module, calculation process module and communication module and selects control signal and pendulous frequency control signal for providing for described fine measurement module;
Described frequency division module obtains fractional frequency signal for described measured signal carries out scaling down processing, and the described fractional frequency signal cycle is the interval that described measure of time method is measured, and described fractional frequency signal is the beginning control signal of this measurement;
Described fine measurement module is used for utilizing described measured signal, fractional frequency signal, selection control signal and pendulous frequency control signal to generate enable signal and to described thick counting module and manages module transmission, and the measured signal rising edge corresponding with fractional frequency signal rising edge is carried out repeatedly fine measurement within each fractional frequency signal cycle, and measurement result is sent to described calculation process module;
Described thick counting module, for the control in conjunction with described enable signal, operating clock signals and management module, carries out once thick measure of time to measured signal within each fractional frequency signal cycle and obtains very first time value, and be transferred to described calculation process module;
Described calculation process module is for receiving the measurement result of described very first time value and repeatedly fine measurement, and calculate, in conjunction with the first frequency dividing multiple of described frequency dividing shaping unit and the second frequency dividing multiple of described frequency division module, the frequency obtaining described extraneous primary signal, and by described communication module to described host computer transmission;
Described second frequency dividing multiple is equal to the rising edge number of described measured signal in gate time.
3. cymometer according to claim 2, it is characterized in that, described calculation process module is for receiving the measurement result of described very first time value and repeatedly fine measurement, and calculates, in conjunction with the first frequency dividing multiple of described frequency dividing shaping unit and the second frequency dividing multiple of described frequency division module, the frequency obtaining described external world primary signal and include:
After described calculation process module receives the measurement result of described very first time value and repeatedly fine measurement, the measurement result of described repeatedly fine measurement is carried out computing and obtains the second time value, utilize described very first time value and the second time value to calculate and obtain the measured signal forward position moment corresponding with fractional frequency signal forward position in the fractional frequency signal cycle, and combine in fractional frequency signal cycle adjacent with this fractional frequency signal cycle and measured signal forward position moment that fractional frequency signal forward position is corresponding is calculated, it is thus achieved that the described fractional frequency signal cycle; By the described fractional frequency signal cycle divided by the described first cycle dividing multiple and the second frequency dividing multiple described measured signal of acquisition, and the cycle of described measured signal is carried out inverted computing, it is thus achieved that the frequency of described extraneous primary signal.
4. cymometer according to claim 2, it is characterised in that described fine measurement module includes: concussion ring, d type flip flop group, the second d type flip flop and decoder;Described concussion ring includes MUX, time delay chain and phase inverter; Wherein,
Described MUX is the selector of a two-way, its first signal input part is used for receiving described measured signal, control signal input is used for receiving described selection control signal, the signal output part of described MUX is connected with the signal input part of described time delay chain, the signal output part of described time delay chain is connected with the signal input part of described phase inverter, the signal output part of described phase inverter is connected with the secondary signal input of described MUX, described MUX for controlling to enter the signal of described time delay chain under the control of described selection control signal,
Described time delay chain, for the measured signal received is carried out delay transport, is made up of the carry chain of FPGA internal additions device, and the non-linear time delay between carry chain unit is demarcated by code density method, and each delay cell rear end has tap;
Described phase inverter is for overturning the measured signal edge state that time delay chain exports, signal rising edge is made to return to original state after phase inverter at twice, when secondary signal input is received outfan by described MUX under the control of described selection control signal, it forms the concussion ring of time delay chain-phase inverter-MUX-time delay chain, measured signal rising edge earthquake ring transmits, adjacent two rising edges arrive the time difference of time delay chain, are the cycle of oscillation of signal;
Described d type flip flop group includes multiple d type flip flop, and its signal input part is connected with the tap of each delay unit rear end of time delay chain successively, and clock termination receives described operating clock signals, thus operationally clock rising edge latches time delay chain state when arriving; Signal output part is connected with decoder, carries out decoding process for the state of latch is sent to decoder; The first d type flip flop of described d type flip flop group is the first d type flip flop, and the signal output part of described first d type flip flop is simultaneously coupled to described second d type flip flop input; Described first d type flip flop exports the first signal to described second d type flip flop; Obtaining secondary signal after the output signal of described second d type flip flop is carried out negated computing, described first signal, secondary signal and described fractional frequency signal and pendulous frequency control signal carry out obtaining described enable signal and to described decoder and thick counting module transmission with logical operations;
Described decoder is for, under the triggering of described enable signal, carrying out decoding process to described latch result, it is thus achieved that described measurement result;
Described d type flip flop group and decoder, namely for, after measured signal forward position enters time delay chain, under the control enabling signal, its positional information in time delay chain being converted to fine measurement result.
5. cymometer according to claim 4, it is characterised in that described repeatedly fine measurement, by forming described concussion ring, adopts multi-times measurement method to realize, wherein:
Described concussion ring is after described measured signal enters described time delay chain by described MUX the first signal input part, by changing the selection control signal of described MUX control signal input, the secondary signal input of described MUX is accessed described time delay chain, the measured signal exported from described time delay chain is made to be again introduced into time delay chain after described phase inverter rollover states and described MUX, described measured signal rising edge again becomes rising edge after twice rollover states and is input in time delay chain, described decoder is under the control of described enable signal, carry out decoding and obtain fine measurement result, can realize within a fractional frequency signal cycle, repeatedly fine measurement is carried out for same measured signal rising edge, it is then passed through calculating and obtains more accurate fine measurement result, this is the multi-times measurement method of further improving measurement accuracy.
6. cymometer according to claim 2, it is characterized in that, described thick counting module is for the control in conjunction with described enable signal, operating clock signals and management module, within each fractional frequency signal cycle, carry out once thick measure of time to measured signal obtain very first time value, and be transferred to described calculation process module and include:
Described thick counting module is started working under the control of described management module, within each fractional frequency signal cycle, the rising edge of described operating clock signals is carried out counting and obtains count results, the cycle of described count results Yu described operating clock signals is carried out product calculation and obtains described very first time value, and when described enable signal is high level, described very first time value is sent to described calculation process module detecting.
7. cymometer according to claim 6, it is characterised in that described thick counting module is the enumerator being operated under described system working clock reference.
8. the cymometer according to any one of claim 1-7, it is characterised in that described clock source is atomic clock or crystal oscillator.
9. a frequency measurement method, is applied to the cymometer described in any one of claim 1-8, it is characterised in that described frequency measurement method includes:
Send instruction by host computer to the processing unit of described cymometer, start primary signal to external world and carry out frequency measurement;
Described cymometer is carried out Initialize installation;
Utilize described cymometer that described extraneous primary signal is carried out once slightly measure of time and repeatedly fine measurement, the measurement result the first frequency dividing multiple in conjunction with described cymometer and the second frequency dividing multiple are calculated obtaining the frequency of described extraneous primary signal, and send host computer to.
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| CN111175573A (en) * | 2020-02-14 | 2020-05-19 | 深圳市科信通信技术股份有限公司 | Method, device, equipment and medium for detecting alternating voltage frequency |
| RU208335U1 (en) * | 2021-09-13 | 2021-12-14 | Федеральное государственное унитарное предприятие «Всероссийский научно-исследовательский институт автоматики им.Н.Л.Духова» (ФГУП «ВНИИА») | Pulse repetition rate measurement unit |
| CN116827335A (en) * | 2023-08-25 | 2023-09-29 | 牛芯半导体(深圳)有限公司 | Frequency divider and data processing circuit |
| CN116827335B (en) * | 2023-08-25 | 2023-10-27 | 牛芯半导体(深圳)有限公司 | Frequency divider and data processing circuit |
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