CN104614976B - A kind of time-digital converter based on FPGA - Google Patents
A kind of time-digital converter based on FPGA Download PDFInfo
- Publication number
- CN104614976B CN104614976B CN201510076606.8A CN201510076606A CN104614976B CN 104614976 B CN104614976 B CN 104614976B CN 201510076606 A CN201510076606 A CN 201510076606A CN 104614976 B CN104614976 B CN 104614976B
- Authority
- CN
- China
- Prior art keywords
- delay
- tap
- code
- signal
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000005259 measurement Methods 0.000 claims abstract description 55
- 230000008859 change Effects 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 30
- 238000000605 extraction Methods 0.000 claims description 27
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 230000008520 organization Effects 0.000 claims description 7
- 230000002123 temporal effect Effects 0.000 claims description 7
- 238000013519 translation Methods 0.000 claims description 3
- 230000005587 bubbling Effects 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 238000004364 calculation method Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000012937 correction Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 230000008707 rearrangement Effects 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- NFGXHKASABOEEW-UHFFFAOYSA-N 1-methylethyl 11-methoxy-3,7,11-trimethyl-2,4-dodecadienoate Chemical compound COC(C)(C)CCCC(C)CC=CC(C)=CC(=O)OC(C)C NFGXHKASABOEEW-UHFFFAOYSA-N 0.000 description 1
- 240000001439 Opuntia Species 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000009206 nuclear medicine Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a kind of TDC based on fpga chip, which includes a pulse signal generator, multitap signal delay chain, flip-flop array, connection network, signal intensity along searching and coding circuit, timestamp output circuit.Pulse signal generator produces a trailing edge under the triggering of measured signal and is fed into signal delay chain.Flip-flop array is latched to each tap state of delay chain under the control of system clock, and passes to connection network.Each tap after connecting distribution of the network according to each delay units delay width of delay chain for measuring in advance to latch is reordered and is extracted, and the state of tap is passed to signal intensity along searching and coding circuit.The present invention can eliminate the impact of 0 delay cell and nonlinearity erron on delay chain to greatest extent, reduce " bubbling " phenomenon in tap state temperature meter code, the performance indications of certainty of measurement, measurement dead time and resource occupation amount in terms of these three are made to reach reasonable balance such that it is able to realize high performance TDC measuring systems.
Description
Technical field
The invention belongs to the digitized measurement field of time quantum, and in particular to a kind of time digital transformation based on FPGA
Device.
Background technology
Time measurement refers to the time interval between the moment that one event of measurement occurs, or two events of measurement.
Time measurement technology all has important application, such as high-energy physics experiment research, nuclear medicine, military affairs and the people in many fields
With radar, and the field such as laser ranging is required for high-precision time measurement technology.Time-digital converter (TDC：Time-
Digital-Convertor it is exactly) a kind of time quantum to be converted into digital quantity to realize the record of an event generation time
Function element.For the measurement of the time interval between two events, typically two events can be measured respectively by two TDC
At the generation moment, the difference at two generation moment is exactly the time interval of two events.At present, TDC realizes that carrier can be divided into
Based on ASIC (Application Specific Integrated Circuit) special chips and based on FPGA (Field
Programmable Gate Array) two kinds of programming device.With the continuous development of FPGA technology, monolithic FPGA can be carried
For logical resource amount it is increasing, the flexibility of its programmable configuration is also increasingly stronger, and FPGA has become digital display circuit collection
Into the platform of design.On this platform, if it is possible to while the measurement of some physical quantitys is realized, the measurement of such as time quantum, nothing
Doubt the data acquisition and processing system special to the user based on FPGA significant.In recent years, the TDC based on FPGA is designed
Technology grows a lot, and a kind of approach of most important of which is to constitute multi-tap using the carry chain in FPGA basic logic resources
Signal transmission delay chain (TDL：Tapped Delay Line), the measurement essence of TDC is improved so as to realize the interpolation of time quantum
Degree.
Various possible specific implementations are had based on TDL types TDC of FPGA, the TDC measurements that different schemes can be realized
Precision is different with the measurement dead time, and the fpga logic stock number shared by single channel TDC is also different.The little measurement dead time can be with
The measurement handling capacity of TDC is improved, few logical resource occupancy can save FPGA resource for the data acquisition of user's design
With the other parts of processing system, or the multichannel TDC system on monolithic FPGA can be realized.However, current TDC is realized
Scheme can not improving certainty of measurement, reduce the measurement dead time and reduce the finger that resource occupation amount is obtained in terms of these three
Mark.
For ease of understanding, multi-tap transmission delay chain (TDL is constituted to the carry chain logical resource using fpga chip first：
Tapped Delay Line) temporal interpolation is realized, so as to the principle for improving TDC certainties of measurement is simply introduced.
The most simple realization method of the digitized measurement of event generation time can be with a high-frequency clock counter come
Realize.When measured signal arrives, the state of counter at that time is recorded, the state is exactly to survey the time of event generation time
Value.The TDC precision of the method is exactly the cycle of counter clock signal.In order to obtain high measurement accuracy, it is necessary to using very
High clock frequency.The maximum clock frequency for being currently based on FPGA is about 710MHz, i.e. highest measurement precision is about
1.408ns.In order to improve the certainty of measurement of TDC, a kind of common method for being currently based on FPGA technology is to try to construct one
The delay chain being unified into by multiple delay cells.The total delay time of the delay chain is greater than the cycle of a system clock, each
The state of delay cell is drawn by tap.To transmit in the measured signal feed-in delay chain, in the arrival of each system clock
Carve the state of the state and delay chain of recording clock counter simultaneously.The former is to mark the thick time of measured signal, Hou Zheshi
Both combinations are exactly the accurate results of measured signal by the thin time mark of measured signal.Using this temporal interpolation skill
Art, the certainty of measurement of TDC depend primarily on the size and precision of delay cell in delay chain.At present, it is to be calculated using FPGA mostly
Constituting delay chain, the length of each delay cell is exactly the transmission of correspondence carry chain to carry chain in art logical operation resource
Retardation.The state of retardation each tap can be drawn using the trigger with carry chain in same resource units, with
The coding of retardation state is exported for subsequent conditioning circuit.When requiring to measure the time interval of two events, can be with
Using two TDC passages, the generation moment of two events is recorded respectively, difference therebetween is exactly time interval.
The delay width of each delay cell has heterogeneity, and each measuring node has measure error.Differential can be used
Non-linear and integral nonlinearity is representing above-mentioned heterogeneity and measure error respectively.Differential nonlinearity can be defined as actually prolonging
The difference for postponing width and ideal delay width of unit, is typically represented for unit with ideal delay width (1 LSB) late.Integration
The non-linear sum that can be defined as from first delay cell to the differential nonlinearity of all delay cells of place measuring node.
It represents the error between the reading value of place measuring node and preferable measured value, typically also with ideal delay width (LSB) is
Unit is represented.In TDC measurements, if not borrowing and correcting by unit, integral nonlinearity is exactly the measurement of each measuring node
Error, therefore the needs by cell correcting circuit will be removed, it is necessary to improve integral nonlinearity as far as possible.
The content of the invention
It is contemplated that while effectively improving the certainty of measurement of TDC, reducing its measurement dead time and reducing single TDC
Passage fpga logic stock number to be taken.
To solve above-mentioned technical problem, the present invention proposes a kind of time-digital converter based on FPGA, including thick clock
Counter, pulse signal generator, signal delay chain, flip-flop array, connection network, signal intensity are along searching and encode electric
Road, and timestamp output circuit, wherein, thick clock counter is driven by clock signal of system, for producing measured signal
Thick timestamp；The pulse signal generator pulse that then generation one has change edge under the triggering of measured signal is simultaneously
It is transmitted in being fed into the signal delay chain；The signal delay chain for carrying out delay transport to measured signal, by many
Individual delay cell composition, and there is tap at the rear of each delay cell, also there is in front of first delay cell tap；Institute
Flip-flop array is stated for latching to each tap state of signal delay chain, and the tap state of latch is taken out according to described
The natural ordering of head passes to the connection network；The connection network for by the tap for receiving state according to presetting
Annexation enter line translation, then pass to the signal intensity along finding and coding circuit；The signal intensity along finding and
The change edge of the pulse transmitted in the signal delay chain that coding circuit is latched for searching, and according to the change edge
Position generate the binary code for representing thin timestamp；The timestamp output circuit is for according to signal intensity is along searching and compiles
The thin timestamp of binary code of code circuit output and the thick timestamp of thick clock counter output are converted into measured signal together
Arrival timestamp simultaneously outputs it.
Specific embodiment of the invention, the connection network is by the tap state for receiving according to set in advance
The conversion that annexation is carried out includes：Each tap of the signal delay chain is reordered, it is determined that one kind is by the triggering
Device array is connected to the signal intensity along the annexation found with coding circuit.
Specific embodiment of the invention, it is described reorder including：By the tap of 0 width delay cell and the next one
The tap position of delay cell is exchanged.
Specific embodiment of the invention, it is described reorder can be repeated several times carry out, once adjustment order after
The delay width of each delay cell is measured, and whether the delay cell number of 0 width is judged more than a threshold value, if it is, again
It is secondary to reorder, until the number of 0 width delay cell is less than the threshold value.
Specific embodiment of the invention, the delay width of each delay cell of the measurement are surveyed using code density method
Measure the delay width of each delay cell.
Specific embodiment of the invention, the connection network is by the tap state for receiving according to set in advance
The conversion that annexation is carried out includes：Each tap to the signal delay chain is extracted, it is determined that one kind is by the trigger
Array is connected to the signal intensity along the annexation found with coding circuit.
Specific embodiment of the invention, the rule of the extraction is：Make what is made based on the signal delay chain
The integral nonlinearity of temporal interpolation measurement is minimum.
Specific embodiment of the invention, the extraction is：Always taking out after being extracted in first setting signal delay chain
Head number is R, then according to system clock cycle TclockCalculate ideal delay length w of the groups of delay cells formed after extracting：w
=Tclock/R Tclock, and complete to extract according to ideal delay length w.
Specific embodiment of the invention, extraction is the tap S for meeting following formulal, 1≤l≤n：
Wherein, if the delay width of original each delay cell is B1、B2、B3、…、Bn, numbers of the n for delay cell, original
The output tap of each delay cell for beginning is designated as S respectively1、S2、S3、…、Sn, the B used in above formula0It is to set up in order to above formula
And the dummy delay amount added, B0=0, the tap after extraction is designated as T1、T2、T3、…、TR, above formula is given to each
I, can be calculated a minimum l, the corresponding tap S of the minimum l valueslIt is exactly the T after extractingi。
Specific embodiment of the invention, the signal intensity is along searching and coding circuit according to from the connection net
The tap state that network is received generates one and represents thermometer-code of the change along position, is generated according to the thermometer-code and is become for representing
Change " one-hot " code along position, then be the binary code for representing timestamp by " one-hot " code conversion.
Specific embodiment of the invention, the signal intensity are moved by one by turn along searching and coding circuit
Window the thermometer-code cutting is obtained into 2NIndividual window value, n=2N, numbers of the n for delay cell, the bit wide of the window
For m, m is natural number and 2≤m≤2N, and obtained and the thermometer by the true value corresponding to window value described in sequential
Corresponding " one-hot " code of code.
Specific embodiment of the invention, the truth table changed between all possible window value and corresponding true value
It is stored in the basic logic unit LUT in FPGA.
Specific embodiment of the invention, when the signal intensity is used to find thermometer along searching and coding circuit
During the trailing edge of code, in the truth table, only last be 0, remaining corresponding true value of window value for being 1 be 1,
The corresponding true value of remaining window value is 0；Or, only last be 0, remaining be 1 the corresponding true value of window value
For 0, the corresponding true value of remaining window value is 1.
Specific embodiment of the invention, the change is along searching and coding circuit for the " one- represented with " 1 "
Hot " codes, by calculating 2N-1The logical "or" computing of individual " one-hot " code word is obtaining the coding of each of binary code；
For " one-hot " code represented with " 0 ", by calculating 2N-1The logic "and" operation of individual " one-hot " code word enters obtaining two
The coding of each of code processed.
Specific embodiment of the invention, the change are made using pipeline organization combination along searching and coding circuit
The logical "or" computing or logic "and" operation are realized with the LUT of FPGA, every one-level of streamline is one or several
Parallel dependence LUT and the logical "or" computing realized or logic "and" operation.
Additionally, the present invention also proposes a kind of thermometer-code based on FPGA to the code conversion method of binary code, it is described
Thermometer-code has 2NPosition, the binary code have a N positions, and N is natural number, and methods described includes：Moved by one by turn
Window the thermometer-code cutting is obtained into 2NIndividual window value, the bit wide of the window is m, and m is natural number and 2≤m≤2N,
And " one-hot " code corresponding with the thermometer-code is obtained by the true value corresponding to window value described in sequential；By institute
State " one-hot " code and be converted to binary code.
Specific embodiment of the invention, the truth table changed between all possible window value and corresponding true value
It is stored in the basic logic unit LUT in FPGA.
Specific embodiment of the invention, when the signal intensity is used to find thermometer-code along circuit is found
Rise along when, in the truth table, only first be 0, remaining corresponding true value of window value for being 1 be 1, remaining window
It is worth corresponding true value and is 0；Or, it is 0 that only first is 0, remaining corresponding true value of window value for being 1, remaining window
The corresponding true value of mouth value is 1；When the signal intensity is used to find the trailing edge of thermometer-code along searching circuit, described
In truth table, only last be 0, remaining corresponding true value of window value for being 1 be 1, remaining window value is corresponding true
Value is 0；Or, only last be 0, remaining corresponding true value of window value for being 1 be 0, remaining window value correspondence
True value be 1.
Specific embodiment of the invention, in " one-hot " code in the transfer process of binary code, for
" one-hot " code represented with " 1 ", by calculating 2N-1The logical "or" computing of individual " one-hot " code word is obtaining binary code
The coding of each；For " one-hot " code represented with " 0 ", by calculating 2N-1The logic of individual " one-hot " code word
AND operation is obtaining the coding of each of binary code.
Specific embodiment of the invention, the LUT for being applied in combination FPGA using pipeline organization realize the logic
Inclusive-OR operation or logic "and" operation, every one-level of streamline are one or several parallel dependence LUT and patrolling for realizing
Collect inclusive-OR operation or logic "and" operation.
The present invention also proposes a kind of thermometer-code based on FPGA to the code conversion device of binary code, the thermometer
Code has 2NPosition, the binary code have N positions, and N is natural number, and the code conversion device includes that signal intensity is electric along finding
Road and " one-hot " code to binary code change-over circuit, wherein, the signal intensity is moved by one by turn along searching circuit
Window the thermometer-code cutting is obtained into 2NIndividual window value, the bit wide of the window is m, and m is natural number and 2≤m≤2N,
And " one-hot " code corresponding with the thermometer-code is obtained by the true value corresponding to window value described in sequential；It is described
" one-hot " code is used to for " one-hot " code to be converted to binary code to binary code change-over circuit.
Specific embodiment of the invention, the conversion truth table between all possible window value and corresponding true value
It is stored in the LUT of fpga logic resource.
Specific embodiment of the invention, when the signal intensity is used to find thermometer-code along circuit is found
Rise along when, in the truth table, only first be 0, remaining corresponding true value of window value for being 1 be 1, remaining window
It is worth corresponding true value and is 0；Or, it is 0 that only first is 0, remaining corresponding true value of window value for being 1, remaining window
The corresponding true value of mouth value is 1；When the signal intensity is used to find the trailing edge of thermometer-code along searching circuit, described
In truth table, only last be 0, remaining corresponding true value of window value for being 1 be 1, remaining window value is corresponding true
Value is 0；Or, only last be 0, remaining corresponding true value of window value for being 1 be 0, remaining window value correspondence
True value be 1.
Specific embodiment of the invention, " one-hot " code to binary code change-over circuit is for " 1 " table
" one-hot " code for showing, by calculating 2N-1The logical "or" computing of individual " one-hot " code word is obtaining each of binary code
The coding of position；For " one-hot " code represented with " 0 ", by calculating 2N-1The logic "and" operation of individual " one-hot " code word
To obtain the coding of each of binary code.
Specific embodiment of the invention, the LUT for being applied in combination FPGA using pipeline organization realize the logic
Inclusive-OR operation or logic "and" operation, every one-level of streamline are one or several parallel dependence LUT and patrolling for realizing
Collect inclusive-OR operation or logic "and" operation.
The TDC of the present invention can make the performance indications of certainty of measurement, measurement dead time and resource occupation amount in terms of these three
Reach reasonable balance such that it is able to realize high performance TDC measuring systems, have important application valency in the association area of time measurement
Value.
Description of the drawings
Fig. 1 is the TDC structural representations of the present invention；
The TDC system main assembly block diagram that Fig. 2 is provided for one embodiment of the present of invention；
Fig. 3 a are surveyed by the delay chain tap that embodiment of the present invention the is provided lower use code density method that puts in order naturally
The delay cell width distribution figure for measuring；
Fig. 3 b are the differential nonlinearity figure obtained according to the delay cell width calculation of Fig. 3 a；
Fig. 3 c are the integral nonlinearity figure obtained according to the delay cell width calculation of Fig. 3 a；
Obtain using code density method is measured after the delay chain tap status re-arrangement sequence that Fig. 4 is provided for embodiment of the present invention
The delay cell width distribution figure for arriving；
Fig. 5 a be after delay chain tap state provided in an embodiment of the present invention is extracted using code density method measurement obtain it is micro-
Divide non-linear figure；
Fig. 5 b are that the use code density method measurement after delay chain tap state provided in an embodiment of the present invention is extracted is obtained
Integral nonlinearity figure；
In the case of Fig. 6 a are delay chain tap state provided in an embodiment of the present invention original Nature Link output, double TDC passages
The measurement histogram of measurement 3.3ns time intervals；
Fig. 6 b delay chain tap states provided in an embodiment of the present invention are exported after present invention conversion annexation
In the case of, the measurement histogram of double TDC channel measurements 3.3ns time intervals；
Fig. 7 is basic look-up table configuration schematic diagrames of Kintex-7FPGA that embodiment of the present invention is provided；
Fig. 8 finds signal intensity along principle schematic for the use slip window construction that embodiment of the present invention is provided；
For the use pipeline organization that embodiment of the present invention is provided, Fig. 9 realizes that 128 logical "or" operating structures show
It is intended to；
Figure 10 is that the total standard with double TDC channel measurements 3.3ns time intervals is extracted in embodiment tap of the present invention
Error relationship figure.
Specific embodiment
Fig. 1 is the structural representation of the time-digital converter based on FPGA that the present invention is provided.As shown in figure 1, its bag
Include thick clock counter, pulse signal generator, signal delay chain, flip-flop array, connection network, signal intensity along find and
Coding circuit and timestamp output circuit.
Thick clock counter is driven by clock signal of system, and for producing the thick timestamp of measured signal.
Pulse signal generator is external trigger, and which is used and then produces one with change edge under the triggering of measured signal
Pulse and be transmitted in being fed into signal delay chain.The change edge is chosen as rising edge or trailing edge.
For carrying out delay transport to measured signal, which is made up of signal delay chain multiple delay cells, and is prolonged at each
The front end of unit has tap late, therefore signal delay chain is multitap signal delay chain.
Flip-flop array for, under the control of system clock, latching to each tap state of signal delay chain, and
The tap state of the latch is passed to into the connection network according to natural ordering.
Connection network, for the tap state of the latch for receiving is entered line translation according to annexation set in advance,
The signal intensity is passed to again along searching and coding circuit；
Signal intensity is along the change for finding the pulse transmitted in signal delay chain being latched for searching with coding circuit
Change edge, and the binary code for representing thin timestamp is generated according to the position on the change edge.Generally, the tap shape of signal delay chain
State is one and represents thermometer-code of the change along position, and signal intensity is generated according to the thermometer-code along searching and coding circuit and used
Change " one-hot " code along position in expression, then be the binary code for representing timestamp by " one-hot " code conversion, be somebody's turn to do
Timestamp is a thin timestamp.
Thermometer-code shows as continuous several " 1 " (being envisaged that the mercury for thermometer) and remaining several " 0 " groups
Into, or on the contrary." one-hot " code then referred to except the coding of one of position, other positions all same, for example ...
00001000 ..., or ... 111110111 ...." one-hot " code that the former is alternatively referred to as represented by " 1 ", the latter are alternatively referred to as
" one-hot " code represented by " 0 ".
According to the present invention, the default annexation of the connection network be tap state that flip-flop array is latched according to
Original natural ordering sends the signal intensity to along searching and coding circuit.It is under default connection, described to be based on
The time-digital converter of FPGA can obtain the distribution results of each delay units delay width, here using code density method measurement
On the basis of, to each tap of signal delay chain respectively through reordering (tap realignment) and/or extract (tap
Decimation), determine that a kind of tap state by flip-flop array latch is connected to the signal intensity along searching and encodes
Annexation between circuit.The connection network is according to the annexation, the tap state transformation that flip-flop array is exported
After be conveyed to the signal intensity along finding and coding circuit.
A kind of mode for reordering is：The tap position of the tap of 0 width delay cell and next unit is exchanged.Should
Sequencer procedure repeatedly can be carried out, i.e.,：The delay width of each delay cell is measured after once adjustment order, judgement is
The no delay cell that also there is 0 width, or whether the delay cell number of 0 width is less than a threshold value, if it is, again
Secondary adjustment order, till the number of 0 width delay cell meets condition.Wherein, each delay can be measured by code density method
The retardation of unit.
It is for the delay width for reducing each delay cell that (decimate) is extracted in tap (tap) to delay cell
Heterogeneity (i.e. differential nonlinearity) and each tap node measure error (i.e. integral nonlinearity).It is described in the present invention
" extracting (tap decimation) " refers to that the tap to each delay cell (output tap) is chosen, so that according to selected
Each delay cell is divided into the groups of delay cells for arranging in order for the tap for taking.The extraction and described reordering can be independent
Using, it is also possible to it is used in combination, but is more preferably extracted after reordering.
What signal intensity edge searching and coding circuit were received is taking out for the groups of delay cells after reordering and/or extracting
Head status." extraction " can so that the measure error (i.e. integral nonlinearity) of the temporal interpolation measurement made based on the delay chain most
It is little, while improving the uniformity (i.e. differential nonlinearity) postponed between groups of delay cells between width.Thus, the present invention can be
Not by the case of by cell correcting circuit, higher certainty of measurement is obtained.
It is that several continuous delay cells are coupled together formation as far as possible one to be close on the process nature of described " extraction "
The tap of ideal delay cell width, a kind of rule of extraction are to make the integral nonlinearity in the measurement of each tap node minimum.
For the signal delay chain of the number of given delay cell, although tap sum to be extracted typically can all be less than original tap
Sum, but also allow the situation of tap sum to be extracted more than or equal to original tap number occur.
The unit between each tap after extraction can be regarded as reconfiguring for the delay cell of original continuous, therefore
Can be described as groups of delay cells.Can be equal to due to the tap sum after extraction, less than or greater than original tap number, therefore postpone single
In tuple, the number of continuous delay cell can be 1, it is also possible to more than 1, or 0.When the number of continuous delay cell
For 0 when, generate equivalent to the extraction carried out for same tap more than 1 time one postpone width be 0 dummy delay
Unit group.
As it was previously stated, the error (i.e. integral nonlinearity) that one of decimation rule is such that in each measurement point is minimum, and not
Manage whether the tap is above pumped through.When a tap is repeatedly extracted, the delay cell of 0 width will necessarily be produced, this
The result of sample remains the minimum needs of integral nonlinearity.As the delay chain constituted based on FPGA internal carries chain is typically all had
There are excessively poor differential nonlinearity and integral nonlinearity, to the new delay chain state being made up of groups of delay cells formed after extraction
Reading, can all cause non-linear (integral nonlinearity and/or the differential nonlinearity) of final time measurement to be greatly improved.
A kind of specific embodiment for extracting is that the total tap number after being extracted in first setting signal delay chain is R, then
According to system clock cycle TclockCalculate ideal delay length w of the groups of delay cells formed after extracting：W=Tclock/ R, and
Complete to extract according to ideal delay length w.
If the delay width of each delay cell is B1、B2、B3、…、Bn, numbers of the n for delay cell, each delay cell
The output tap of front end is designated as S respectively1、S2、S3、…、Sn, the tap of the groups of delay cells after extraction is designated as T1、T2、T3、…、TR。
For the tap T of the groups of delay cells after extractioni, 1≤i≤R, then what which extracted is that to meet following formula minimum l values corresponding
Tap Sl, 1≤l≤n：
Wherein, B0It is in order that above formula is set up and a dummy delay amount of addition, B0=0.
Connection network in FIG is representing the above-mentioned way of realization reordered with extraction process.In fact, the connection network
There is also in the TDC structures that existing FPGA is realized, only use annexation in order (i.e. above-mentioned to lack there
Save annexation).The present invention have passed through reordering and extracting for delay cell, and what is utilized is the reconfigurable feature of FPGA, will
The annexation of connection network is changed accordingly.
To avoid the interference of " bubbling " phenomenon, the change of the present invention from being preferably along searching and coding circuit and adopt sliding window method
Thermometer-code is converted to into " one-hot " code.The process for obtaining " one-hot " code corresponding with thermometer-code is exactly to find in fact
The process on signal intensity edge.Here, we set the tap number of signal delay chain as n=2N, then thermometer-code have 2NPosition is turned
The binary code got in return is N positions, and N is natural number.
Specifically, sliding window method of the invention passes through a window for moving by turn first by the thermometer-code cutting
Obtain 2NIndividual window value, the bit wide of the window is m, and m is natural number and 2≤m≤2N, and pass through window value described in sequential
Corresponding true value obtains " one-hot " code corresponding with the thermometer-code.
Additionally, the impact in order to eliminate " bubbling ", here regulation, when the change is used to find along searching and coding circuit
During the trailing edge of thermometer-code, only last be 0, remaining corresponding true value of window value for being 1 be 1, remaining window
It is worth corresponding true value and is 0 (for " one-hot " code represented by " 1 ")；Or, only last position is that 0, remaining position is
The 1 corresponding true value of window value is 0, and the corresponding true value of remaining window value is 1 (for " one-hot " code represented by " 0 ").
Conversion truth table between all possible window value and corresponding true value is stored in the LUT of fpga logic resource.
The change edge is found and coding circuit is for " one-hot " code represented with " 1 ", by calculating 2N-1Individual " one-
The logical "or" computing of hot " code words is obtaining the coding of each of binary code；For " one-hot " that represented with " 0 "
Code, by calculating 2N-1The logic "and" operation of individual " one-hot " code word is obtaining the coding of each of binary code.Pass through
When FPGA is realized, the LUT for being applied in combination FPGA using pipeline organization realizes the logical "or" computing or logical "and"
Computing, every one-level of streamline are one or several parallel dependence LUT and the logical "or" computing realized or logical "and"
Computing.
Timestamp output circuit is for the binary code and thick clock according to the searching of signal intensity edge and coding circuit output
The count signal of counter output is converted into the arrival time of measured signal together.
The characteristics of below by the description of the technical scheme to one embodiment of the present of invention to make the present invention and beneficial effect
Fruit is clearer, complete.It is to be appreciated that embodiment described herein is only a part of embodiment of the present invention, rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creative work premise
Lower obtained every other embodiment, belongs to the scope of protection of the invention.
Fig. 2 is the TDC system main assembly block diagram that one embodiment of the present of invention is provided.It includes that a pulse signal is sent out
Raw device, the TDL being made up of carry chain (Tapped Delay Line), flip-flop array, a signal intensity edge are sought
Look for and coding circuit and a coarse counter driven by system clock and timestamp output circuit.What the present embodiment was used
Fpga chip is Kintex-7xc7k325t-2ffg900.
In the present embodiment, the system clock frequency of FPGA is 710MHz, and the cycle is 1.408ns.It is made up of carry chain
The total delay time length of TDL is greater than the cycle of a system clock, and its total tap number is less than 200, and whole TDL can be with complete
Logical resource of the site preparation in using a clock zone is realizing.Do so can be avoided due to TDL cross clock domains, at two
There is larger delay cell in the boundary in clock domain.Every time measured signal arrives, all can trigger generator output signal
Low level is changed to by high level, the signal is transmitted along TDL, flip-flop array is latched in the rising edge of next system clock
The state of TDL.The state will be given signal and be found along change and coding circuit.The result of coding is exactly signal intensity along in TDL
In position, that is, thin timestamp.The output of the coarse counter is the thick timestamp of measured signal.By thin timestamp and slightly
The time mark that the combination of timestamp is measured after exactly surveying, is exported by timestamp output circuit.
Due to the retardation of each delay cell in TDL it is usually unequal, along with the clock of control trigger array
There is Skew (i.e. due to clock network path-length not etc. reason in the Clock control end of each trigger in signal network
Cause the moment of the tap state of flip/flops latch not strict while), the delay width of each delay cell for being showed can be caused
Spend (time delay), or even effective delay width of some units is 0.Prolonging for each delay cell can be obtained by measurement
Slow width.
Code density method is a kind of method for being usually used in and measuring each delay units delay amount size, and it is to produce one outside
With the incoherent square-wave signal of system clock as external trigger signal, each rising edge of the signal can trigger generator
One signal trailing edge of generation (note, in this embodiment, after the set time that trailing edge is produced, the output of impulse generator
High level can be reverted to), carry out a time mark surveying record.Due to external trigger signal and clock signal of system it is uncorrelated,
The moment that arrives of external trigger signal should be evenly distributed in a cycle of system clock.Thus under flip-flop array is latched
The TDL states come, the position of its trailing edge equiprobably should be distributed in a cycle.Occur conversely speaking, to prolong at each
The example number (measuring number of times) of the trailing edge of unit should be directly proportional with its slow cell width is prolonged late, accordingly, it is possible to measure each
The retardation width of individual delay cell.
Fig. 3 a are primitive nature order (i.e. the order of connection of delay chain) of the embodiment of the present invention according to delay chain, sharp
The delay cell width distribution figure obtained with code density method measurement, its transverse axis are tap sequence numbers, and the longitudinal axis is to postpone width.
Can be seen that from Fig. 3 a, the effective delay width for having the suitable delay cell of most be 0, i.e. these units from
The change edge of signal can not independently be seen.The delay cell of 0 width is unfavorable to obtaining high temporal interpolation resolution ratio, because
It has been added to the retardation of oneself in other delay cells, causes unit retardation larger, and effectively postpones single
First number is reduced, and temporal interpolation resolution ratio is reduced.On the other hand, the delay cell of zero width can be in status switch thermometer-code
Produce " bubbling ".By taking trailing edge as an example, preferable status switch should be ... 11110000 ..., but due to the delay list of zero width
Unit is present, it is possible to the status switch for occurring ... 11010000 ..., wherein first 0 is exactly " bubbling ", this with " emitting
The conditional code of bubble " can cause the searching of trailing edge to be difficult to, and have found also inaccurate.In order to retrieve the damage that this part is caused
Becoming estranged reduces change along the design difficulty for finding circuit, and the present invention proposes to send into signal intensity in the tap status switch that will be latched
Along finding with before coding circuit, the tap of delay cell is reordered, weight is carried out equivalent to by the tap state of delay cell
Sort to reduce the delay cell number of 0 width to greatest extent.
In the embodiment, according to each unit retardation distribution map that code density method is measured, by the tap of 0 width unit with
The tap position of one unit is exchanged, after adjustment order again with code density method measurement delay cell width distribution figure (similar to
Fig. 3 a), such as the delay cell of also 0 width is present, and just presses above-mentioned rule adjustment again, measures again, adjust again, Zhi Daoji
Till not having or do not have completely the delay cell of 0 width to occur.So far, reorder and complete, then flip-flop array is latched
Tap state give ensuing signal intensity along finding and coding circuit according to new order.
Fig. 4 is that the delay cell width distribution figure for obtaining is measured after the embodiment of the present invention is reordered as stated above, it is seen that
All of width is not 0.
It is also seen that from Fig. 3 a except front four delay cell seems to look like exception, other each delay cells
The difference for postponing width is very big.Fig. 3 b are the differential nonlinearity figures of the delay width calculation according to Fig. 3 a, and Fig. 3 c are according to Fig. 3 a
Delay width calculation integral nonlinearity figure.The abscissa of Fig. 3 b and Fig. 3 c is the tap number of delay chain, the unit of ordinate
It is a preferable delay cell width (LSB：Least Significant Bit)).The enforcement is shown from Fig. 3 b and Fig. 3 c
The nonlinearity erron of the delay cell of example is very big.In prior art, for so big nonlinearity erron is necessarily required to surveying
Amount result carries out correcting by unit, in the general TDC structures based on signal delay chain, will have online by unit correction electricity
Road, demarcates measurement result each time using the integral nonlinearity for having measured.But, as it was previously stated, the present invention passes through
" extraction " technology eliminating above-mentioned nonlinearity erron, without by cell correcting circuit.
In this embodiment, when extracting, need to carry out the tap sum R of extraction process in needing first to set the TDL,
The present embodiment is set as R=80, then can calculate each delay cell according to the clock cycle and preferably postpone length, this
The clock cycle of embodiment is 1.408ns, and preferable delay cell length (LSB) is 17.6ns.Due to starting in Fig. 3 a
Four delay cells and impulse generator in the same logical blocks of the FPGA (SLICE), its postpone change width some
Exception, directly ignores them in the present embodiment, the 5th delay cell is demarcated as first B1.Next it is exactly 80 taps
Extraction process, the process is by a MATLAB program on PC according to following extraction formula calculating realization.Referring to Fig. 2,
The delay width of each delay cell is designated as B1、B2、…、Bn, the output tap of each delay cell is respectively labeled as S1、S2、...、
Sn, the tap after extraction is labeled as T1、T2、...、TR, R=80 in the present embodiment.Start to be set as B0=0, TiExtract as Sl,
L meets following condition：
Pass throughA minimum l is calculated, this is most
The corresponding tap S of little l valueslIt is exactly the T after extractingi。
The extraction process that above formula is represented is so that the error of integral nonlinearity is minimized.
Fig. 5 a and Fig. 5 b are the differential nonlinearity figures and integral nonlinearity that the delay chain code density method after extracting is measured
Figure.It can be seen that, to compare with Fig. 3 b with Fig. 3 c, the nonlinearity erron of Fig. 5 a and Fig. 5 b performances improves a lot.
Reordering and extracting to delay cell in the present invention, what is utilized are the reconfigurable features of FPGA, will connect net
The annexation of network is changed accordingly, i.e., the connection network is directly by tap SlIt is connected to Ti.This change can be utilized
The Include files that MATLAB programs are changed in FPGA synthesis tool softwares automatically are realizing, it is not necessary to the participation of hand layouts.
In this embodiment, due to measured signal trigger an impulse generator trailing edge, the trailing edge indicate by
Transmission of the signal on TDL is surveyed, 11110000 ... form that the conditional code being latched on TDL has ..., present such code word
Signal intensity is given respectively along searching and coding circuit, the position of trailing edge is found out by which, and generates a mark trailing edge position
" one-hot " code put, is then encoded to binary code output by " one-hot " code again.This process nature is first-class to serve as reasons together
Basic problem of the thermometer-code to the transform coding of binary code.
Signal intensity is all minimum logic money in fpga chip along the fpga logic resource found and coding circuit is used
Basic look-up table in the unit of source.Basic look-up table resource in current two big main flow FPGA (Xilinx and Altera) it is concrete
Version is incomplete same, and the main distinction is different with output signal number in the input maximum bit wide of basic look-up table, for example originally
The basic look-up table configuration of the Kintex-7FPGA used by embodiment is as shown in Figure 7.It has 6 inputs, 2 output ends.
The look-up table is used as one 6 input look-up table (6-LUT), it is also possible to be used as 25 inputs look-up table (5-LUT), this
When 15 to be assigned 1.The look-up table of the FPGA of other series or other companies is similar with this.The present embodiment is by the lookup of Fig. 7
Table be used as 2 5-LUT, one of them be used for trailing edge searching circuit, another for the time being without.The searching principle on change edge is such as
Shown in Fig. 8.Whether window in have interested change edge, the width of each sliding window is 5 if found using slip window construction parallel, it
It is the input bit wide of basic look-up table.If the input of last window is less than 5, with " 1 " polishing.If found in a window
Change edge interested is arrived, the window is output as 1, be otherwise 0.So fenestrate output just will pass through what is reordered
TDL conditional codes are transformed to " one-hot " code.D is used in Fig. 8i" one-hot " code of trailing edge is represented, i is 0 or positive integer.
The change of table 1. is along the truth table for finding circuit
Table 1 is the basic look-up table for changing edge searching with " bubbling " error correcting capability provided in an embodiment of the present invention
Truth table, wherein DiIt is just 1 only in the case of 11110, other situations are 0.
The arrangement of above-mentioned truth table so that change has certain " bubbling " fault-tolerant ability along searching, if for example gone out
Existing ... 1111010000 ... code word, then last 1 will be ignored.In other words by the truth table assignment of look-up table, become
Change along searching with " bubbling " error correcting capability.For the present embodiment, it is occur continuous 3 " to emit that maximum is capable of the situation of error correction
Bubble ".This has been enough for the state code word through TDL status re-arrangement sequences, because in we put into practice, no discovery has company
The occurrence of continuing two " bubbling ".
The only one of which 1 in " one-hot " code of the present embodiment, remaining is all 0, wherein change edge is indicated in 1 position
Position (it is of course also possible to be only one of which 0, remaining is all 1, wherein 0 position is exactly the position for changing edge).The present embodiment will
" one-hot " code is converted into the binary code (A of 87, A6, A5, A4, A3, A2, A1, A0).The thinking of adopted encryption algorithm
It is which code word is 1 some code word in binary code to be caused to be 1 in " one-hot " code.
With A6Encryption algorithm as a example by, table 2 be " one-hot " code provided in an embodiment of the present invention to binary code coding
Mathematical algorithm illustrates table.
Table 2. makes coding export all D of A6=1iSituation
| A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 | Di |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | D64 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | D65 |
| … | … | … | … | … | … | … | … | … |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | D127 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | D128+64 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | D128+65 |
| … | … | … | … | … | … | … | … | … |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | D128+127 |
It can be A that table 2 is listed6=1 all Di, have 128 DiA can be made when equal to 16=1.Therefore A6Volume
Code algorithm should be exactly the logical "or" of 128.The position of 128 can be expressed simply as x1xxxxxx, and wherein x divides
Other value is 0 and 1.Equally, in binary code other all positions are all 128 D of correspondenceiLogical "or", these 128
There is same expression formula position, for example, make A3=1 all positions are on xxxx1xxx positions.
Above-mentioned encryption algorithm realizes that circuit theory is as shown in Figure 9.Here still use basic look-up table, but here
It is used as 6-LUT.The coding inclusive-OR operation of the present embodiment is realized using three class pipeline structure.Wherein the first order is by 22 6-
LUT is constituted, and can receive 132 inputs altogether, and there are 4 6-LUT the second level, and third level only one of which 6-LUT is touched with D between per grade
Send out device array buffer data.The truth table of all 6-LUT is all inclusive-OR operation.The A for finally exportingiIn expression binary code one
Position.For 8 binary codes of the present embodiment trailing edge, 8 sets of above-mentioned pipeline operation circuit is needed altogether, their concurrent operations,
Pipeline organization allows the speed of encoding operation to reach system clock frequency.
The present invention is the TDC methods for designing minimized towards nonlinearity erron.Nonlinearity erron is minimized and necessarily brings survey
The raising of accuracy of measurement.In order to show the raising of the certainty of measurement brought of the invention, in the described embodiment, use as shown in Figure 3 a
Delay chain, realizes the TDC of two passages, does not use by unit bearing calibration, does not also adopt reordering and extracting for the present invention,
One fixed time interval of measurement.The measured histogram for obtaining such as Fig. 6 a.Equally, we with the present invention towards non-linear
What error was minimized reorders and abstracting method, realizes the TDC of two passages, measures same time interval, the histogram for obtaining
Such as Fig. 6 b.Fig. 5 a are compared with Fig. 5 b, it is seen that histogrammic alteration of form, the standard error of measurement is also improved by 30.9ps
For 12.7ps.Thus provable, the present invention can obtain high survey in the case of need not be by unit correction hardware or software
Amount resolution ratio.
It should be noted that the delay chain given for, there is the total tap number of optimal extraction.Figure 10 is given
The realized TDC of the present embodiment measures the standard error of a Fixed Time Interval with total extraction number variation relation, wherein horizontal
Axle is the total tap number for extracting, and the longitudinal axis is the standard error that binary channels TDC measures 3.3ns time intervals.
Particular embodiments described above, has been carried out to the purpose of the present invention, technical scheme and beneficial effect further in detail
Describe in detail bright, it should be understood that the foregoing is only the specific embodiment of the present invention, be not limited to the present invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc. should be included in the protection of the present invention
Within the scope of.
Claims (14)
1. a kind of time-digital converter based on FPGA, including thick clock counter, pulse signal generator, signal delay
Chain, flip-flop array, connection network, signal intensity edge are found and coding circuit, and timestamp output circuit, wherein
The thick clock counter is driven by clock signal of system, for producing the thick timestamp of measured signal；
The pulse signal generator then one pulse with change edge of generation feed-in under the triggering of measured signal
It is transmitted in the signal delay chain；
The signal delay chain is made up of multiple delay cells for carrying out delay transport to measured signal, and each postpones list
The front end of unit has tap；
The flip-flop array for latching to each tap state of signal delay chain, and by latch tap state according to
The natural ordering of the tap passes to the connection network；
The network that connects is for entering line translation according to annexation set in advance by the tap for receiving state, then passes to
The signal intensity is along searching and coding circuit；
The signal intensity is along the pulse transmitted in the signal delay chain found and coding circuit is latched for searching
Change edge, and the binary code for representing thin timestamp is generated according to the position on the change edge；
The timestamp output circuit is for the thin timestamp of binary code according to the searching of signal intensity edge and coding circuit output
The arrival timestamp of measured signal is converted into together and is output it with the thick timestamp of thick clock counter output；
The tap state for receiving is included by the connection network according to the conversion that annexation set in advance is carried out：Will be described
Each tap of signal delay chain is reordered, it is determined that the flip-flop array is connected to the signal intensity along searching by one kind
With the annexation of coding circuit.
2. the time-digital converter based on FPGA as claimed in claim 1, it is characterised in that it is described reorder including：By 0
The tap position of the tap of width delay cell and next delay cell is exchanged.
3. the time-digital converter based on FPGA as claimed in claim 2, it is characterised in that it is described reorder it is repeatable many
It is secondary to carry out, the delay width of each delay cell is measured after once adjustment order, whether judge the delay cell number of 0 width
More than a threshold value, if it is, reorder again, until the number of 0 width delay cell is less than the threshold value.
4. the time-digital converter based on FPGA as claimed in claim 3, it is characterised in that each delay cell of the measurement
Delay width be the delay width that each delay cell is measured using code density method.
5. the time-digital converter based on FPGA as any one of Claims 1-4, it is characterised in that the company
Connecing network includes the tap state for receiving according to the conversion that annexation set in advance is carried out：To the signal delay chain
Each tap extracted, determine and a kind of the flip-flop array be connected to into the signal intensity along finding and coding circuit
Annexation.
6. the time-digital converter based on FPGA as claimed in claim 5, it is characterised in that the rule of the extraction is：
Make the integral nonlinearity that the temporal interpolation made based on the signal delay chain is measured minimum.
7. the time-digital converter based on FPGA as claimed in claim 6, it is characterised in that the extraction is：First set
Total tap number after being extracted in signal delay chain is R, then according to system clock cycle TclockCalculate what is formed after extracting
Ideal delay length w of groups of delay cells：W=Tclock/RTclock, and complete to extract according to ideal delay length w.
8. the time-digital converter based on FPGA as claimed in claim 7, it is characterised in that extraction is to meet following public affairs
The tap S of formulal, 1≤l≤n：
Wherein, if the delay width of original each delay cell is B1、B2、B3、…、Bn, n is the number of delay cell, original
The output tap of each delay cell is designated as S respectively1、S2、S3、…、Sn, the tap after extraction is designated as T1、T2、T3、…、TR, in order to
Setting up above formula needs to increase an amount B0, and set：B0=0；To each given i, can all be calculated in a satisfaction
The l values of the minimum of formula, the corresponding tap S of the minimum l valueslIt is exactly the T after extractingi。
9. the time-digital converter based on FPGA as claimed in claim 1, it is characterised in that the signal intensity is along finding
One is generated according to the tap state received from the connection network with coding circuit and represent thermometer-code of the change along position, root
According to the thermometer-code generate for represent change along position " one-hot " code, then should " one-hot " code conversion be expression when
Between the binary code that stabs.
10. the time-digital converter based on FPGA as claimed in claim 9, it is characterised in that the signal intensity is along seeking
Look for and the thermometer-code cutting is obtained into 2 by a window for moving by turn with coding circuitNIndividual window value, n=2N, n is to prolong
The number of slow unit, the bit wide of the window is m, and m is natural number and 2≤m≤2N, N is natural number, and passes through sequential institute
State the true value corresponding to window value and obtain " one-hot " code corresponding with the thermometer-code.
11. time-digital converters based on FPGA as claimed in claim 10, it is characterised in that all possible window value
The truth table changed between corresponding true value is stored in the basic logic unit LUT in FPGA.
12. time-digital converters based on FPGA as claimed in claim 11, it is characterised in that when the signal intensity edge
Find and coding circuit be used for when finding the trailing edge of thermometer-code, in the truth table, only last position be 0, remaining
It is 1 that position is the 1 corresponding true value of window value, and the corresponding true value of remaining window value is 0；Or, only last position be 0,
Remaining corresponding true value of window value for being 1 is 0, and the corresponding true value of remaining window value is 1.
13. time-digital converters based on FPGA as claimed in claim 9, it is characterised in that the change along finding and
Coding circuit for " one-hot " code represented with " 1 ", by calculating 2N-1The logical "or" computing of individual " one-hot " code word comes
Obtain the coding of each of binary code；For " one-hot " code represented with " 0 ", by calculating 2N-1Individual " one-hot "
The logic "and" operation of code word is obtaining the coding of each of binary code.
14. time-digital converters based on FPGA as claimed in claim 13, it is characterised in that the change along finding and
Coding circuit realizes the logical "or" computing or logic "and" operation using the LUT that pipeline organization is applied in combination FPGA,
Every one-level of streamline is one or several parallel dependence LUT and the logical "or" computing realized or logic "and" operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510076606.8A CN104614976B (en) | 2015-02-12 | 2015-02-12 | A kind of time-digital converter based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510076606.8A CN104614976B (en) | 2015-02-12 | 2015-02-12 | A kind of time-digital converter based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104614976A CN104614976A (en) | 2015-05-13 |
| CN104614976B true CN104614976B (en) | 2017-03-29 |
Family
ID=53149478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510076606.8A Expired - Fee Related CN104614976B (en) | 2015-02-12 | 2015-02-12 | A kind of time-digital converter based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104614976B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111565044B (en) * | 2020-05-25 | 2024-05-03 | 明峰医疗系统股份有限公司 | ADC device based on split-phase clock TDC and analog-to-digital conversion method thereof |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016127357A1 (en) * | 2015-02-12 | 2016-08-18 | 中国科学技术大学 | Fpga-based time-to-digital converter |
| CN105068405B (en) * | 2015-08-28 | 2017-10-03 | 中国科学技术大学 | Single channel signal pulsewidth high-precision measuring method and device that FPGA is realized |
| CN106019923B (en) * | 2016-05-18 | 2018-11-13 | 中国科学技术大学 | A kind of time-digital converter based on FPGA |
| CN107643674B (en) * | 2016-07-20 | 2020-01-03 | 南京理工大学 | Vernier type TDC circuit based on FPGA carry chain |
| CN106227026B (en) * | 2016-09-05 | 2019-01-11 | 中国科学院国家授时中心 | A kind of time-interval counter of double delay interpolation methods |
| CN106773613B (en) * | 2016-12-19 | 2019-03-22 | 武汉中派科技有限责任公司 | Time-to-digit converter and Method Of Time Measurement |
| CN107908097B (en) * | 2017-11-13 | 2019-12-03 | 中国电子科技集团公司第四十一研究所 | Using the time interval measurement system and measurement method of mixing interpolation cascade structure |
| CN108333910B (en) * | 2018-05-02 | 2019-12-31 | 晶晨半导体(上海)股份有限公司 | Novel time-to-digital converter |
| CN110673463A (en) * | 2018-07-02 | 2020-01-10 | 陈昊昌 | High-linearity multi-channel tap delay line time-to-digital converter |
| CN109101075B (en) * | 2018-09-26 | 2020-04-21 | 上海星秒光电科技有限公司 | Time tag generation device and method |
| DE102019205731A1 (en) | 2019-04-18 | 2020-10-22 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Time-to-digital converter arrangement |
| CN110531404B (en) * | 2019-06-03 | 2021-07-09 | 中国科学技术大学 | Nuclear pulse charge time conversion method and system |
| CN110147037B (en) * | 2019-06-19 | 2021-03-30 | 东软医疗系统股份有限公司 | Time-to-digital converter adjusting method and device |
| JP2021052258A (en) * | 2019-09-24 | 2021-04-01 | セイコーエプソン株式会社 | Circuit arrangement, physical quantity measuring device, electronic apparatus, and movable body |
| CN110764396B (en) * | 2019-11-27 | 2020-10-30 | 华中科技大学 | Time-to-digital converter and time measuring method |
| CN112578661A (en) * | 2020-12-11 | 2021-03-30 | 天津大学 | Delay line calibration circuit for FPGA type time-to-digital converter |
| CN114047683B (en) * | 2021-11-15 | 2022-05-24 | 星汉时空科技(长沙)有限公司 | Time interval measuring method and device based on orthogonal sampling interpolation |
| CN114326358B (en) * | 2021-12-20 | 2024-05-17 | 中国科学院上海光学精密机械研究所 | Multi-chain parallel segmentation high-precision FPGA time-digital conversion method |
| CN117170210B (en) * | 2023-09-07 | 2024-04-26 | 中国科学院近代物理研究所 | FPGA-based tap delay chain type TDC |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5289135A (en) * | 1990-01-25 | 1994-02-22 | Nippon Soken, Inc. | Pulse phase difference encoding circuit |
| CN1719353A (en) * | 2005-06-21 | 2006-01-11 | 中国科学技术大学 | Time digital converter based on RPGA and its conversion method |
| CN102882527A (en) * | 2011-07-11 | 2013-01-16 | 山东欧龙电子科技有限公司 | Time-to-digital converter and time-to-digital conversion method |
| CN103208994A (en) * | 2013-03-11 | 2013-07-17 | 东南大学 | Two-stage time digital convert (TDC) circuit |
| CN103219994A (en) * | 2012-01-20 | 2013-07-24 | 联发科技股份有限公司 | Method and apparatus of calibrating mismatch of TDC |
| CN103472712A (en) * | 2013-09-26 | 2013-12-25 | 中国科学技术大学 | High-precision and high-integrality time-digital converter based on FPGA (Field Programmable Gate Array), and implementation method |
| CN103516367A (en) * | 2012-06-20 | 2014-01-15 | 中国科学院电子学研究所 | Time-to-digital converter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4725418B2 (en) * | 2006-05-31 | 2011-07-13 | 株式会社デンソー | Time measurement circuit |
-
2015
- 2015-02-12 CN CN201510076606.8A patent/CN104614976B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5289135A (en) * | 1990-01-25 | 1994-02-22 | Nippon Soken, Inc. | Pulse phase difference encoding circuit |
| CN1719353A (en) * | 2005-06-21 | 2006-01-11 | 中国科学技术大学 | Time digital converter based on RPGA and its conversion method |
| CN102882527A (en) * | 2011-07-11 | 2013-01-16 | 山东欧龙电子科技有限公司 | Time-to-digital converter and time-to-digital conversion method |
| CN103219994A (en) * | 2012-01-20 | 2013-07-24 | 联发科技股份有限公司 | Method and apparatus of calibrating mismatch of TDC |
| CN103516367A (en) * | 2012-06-20 | 2014-01-15 | 中国科学院电子学研究所 | Time-to-digital converter |
| CN103208994A (en) * | 2013-03-11 | 2013-07-17 | 东南大学 | Two-stage time digital convert (TDC) circuit |
| CN103472712A (en) * | 2013-09-26 | 2013-12-25 | 中国科学技术大学 | High-precision and high-integrality time-digital converter based on FPGA (Field Programmable Gate Array), and implementation method |
Non-Patent Citations (2)
| Title |
|---|
| 基于FPGA的数字IC时间参数测试技术研究;刘凤伟;《中国优秀硕士学位论文全文数据库工程科技辑》;20111215;全文 * |
| 基于门延时的数字TDC电路设计;李大鹏等;《中国集成电路》;20110731;第38-40页 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111565044B (en) * | 2020-05-25 | 2024-05-03 | 明峰医疗系统股份有限公司 | ADC device based on split-phase clock TDC and analog-to-digital conversion method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104614976A (en) | 2015-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104614976B (en) | A kind of time-digital converter based on FPGA | |
| CN104597748B (en) | FPGA (field programmable gate array)-based time-digital converter | |
| WO2016127357A1 (en) | Fpga-based time-to-digital converter | |
| CN106019923B (en) | A kind of time-digital converter based on FPGA | |
| CN100468234C (en) | Time digital converter based on RPGA and its conversion method | |
| Dezert et al. | A new probabilistic transformation of belief mass assignment | |
| Liu et al. | A spatial panel statistical analysis on cultivated land conversion and Chinese economic growth | |
| CN103714135A (en) | MapReduce recommendation method and system of second-degree interpersonal relationships of massive users | |
| Frougny et al. | Rational base number systems for $ p $-adic numbers | |
| CN111142357B (en) | Multi-edge position coding method for time-to-digital converter delay chain interpolation | |
| Komornik et al. | Bases in which some numbers have exactly two expansions | |
| Wang et al. | Low-complexity Winograd convolution architecture based on stochastic computing | |
| CN110837624A (en) | Approximate calculation device for sigmoid function | |
| Alvarez et al. | M. Levin’s construction of absolutely normal numbers with very low discrepancy | |
| Yu et al. | Approximate divider design based on counting-based stochastic computing division | |
| CN103336865B (en) | A kind of dynamic communication network construction method and device | |
| Matsenko et al. | Noise immunity of the fibonacci counter with the fractal decoder device for telecommunication systems | |
| Hao et al. | The principle and applications of asynchronous FIFO | |
| Wang | Forecasting modeling and analysis of power engineering in China based on Gauss-Chebyshev formula | |
| CN104808086B (en) | A kind of AD analog input cards and acquisition method with adaptation function | |
| Chandu et al. | Design and implementation of high efficiency square root circuit using Vedic mathematics | |
| CN107862132B (en) | Automatic node deletion method for circuit approximate calculation | |
| CN109104168B (en) | Circuit for measuring fine time | |
| Crutchfield et al. | Noise scaling of symbolic dynamics entropies | |
| Hubalek et al. | A multivariate view of random bucket digital search trees |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170329 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |