CN100468234C - Time digital converter based on RPGA and its conversion method - Google Patents

Abstract

The present invention relates to a time/digital converter based on FPGA and its conversion method, belonging to the field of time measurement technology. Said converter includes the following components: fine time measurement unit, coding unit, coarse time measurement unit and data buffer storage unit. The main application of said invention is to make high accuracy time measurement, it can be used in the fields of basis research and various application researches.

Description

Time-to-digital converter based on FPGA and conversion method thereof

Technical Field

The invention belongs to a time measuring device, and particularly relates to a time measuring device realized by using a field programmable logic device (FPGA).

Background

The precise time plays an important role in basic research fields such as the earth dynamics research, the relativistic research, the pulsar cycle research, the artificial satellite dynamics geodesic research and the like, is also commonly applied in application research such as aerospace, deep space communication, satellite launching and monitoring, geological mapping, navigation communication, power transmission, scientific metering and the like, national defense and national economic construction, and even has been deeply reached to the aspects of social life of people, and is almost beyond the reach. Of course, for daily life, the notion of time is generally accurate to minutes and is sufficient. However, in many applications such as high-precision instruments, physical experiments, national defense and the like, time measurement is an important and critical basic means, and the requirement on the measurement precision is very strict.

The time measurement methods are many, and can be mainly classified into a counting method, an interpolation method, a vernier caliper method, a time amplification method, and the like. The counting method is simple, but the measurement precision is not high. The time amplification method has the disadvantages of complex circuit, large dead time, large workload of calibration and maintenance, large power consumption and being not beneficial to improving the integration level. Therefore, time interpolation and vernier caliper methods are mostly used for high-precision time measurement, and the main implementation means is to develop a high-precision time-to-digital conversion (TDC) chip or plug-in. The traditional TDC plug-in is large in size, not beneficial to improving the integration level and large in power consumption. The newly developed TDC chip has high integration level and its precision is gradually improved with the development of semiconductor processes. However, the cost of development is relatively high, and on the other hand, under the condition of limited level of the electronic industry, a proper TDC chip meeting the requirement cannot be designed and manufactured.

Disclosure of Invention

The invention aims to provide a high-precision time-to-digital converter based on an FPGA (field programmable gate array), so that high-precision time measurement can be carried out on an input signal to be measured at lower cost.

The time-to-digital converter has a plurality of types, but the basic function of the time-to-digital converter is to realize the conversion from time information to digital information. The time-to-digital converter includes two time measurements, one of which is a coarse time measurement using a counting method, and the other of which is a fine time measurement using an interpolation method to achieve a high-precision time measurement. The key point of the invention is to use special carry line in FPGA to interpolate time for clock period to realize fine time measurement, and use two high-speed counters which work under positive phase and negative phase clocks and are synchronous with clock to realize coarse time measurement, thus realizing high-precision time-to-digital converter, and further carrying out high-precision time measurement for input signal to be measured.

The concrete solution of the invention is as follows:

the high-precision time-to-digital converter based on the FPGA is provided with a fine time measuring unit, a coding unit, a coarse time measuring unit and a data caching unit, wherein the units are all realized in the FPGA. The fine time measuring unit interpolates the time of the clock period by utilizing a special carry line which is universally existing in the FPGA and has very small fixed time delay, thereby realizing high-precision time-to-digital conversion. The coding unit is used for coding the data output by high-precision time-to-digital conversion, namely coding the data with wide output bit number and compressing the width of the data bit number, and the coding of the part adopts a pipeline technology to process. The coarse time measuring unit consists of two high-speed synchronous counters working under normal phase and reverse phase system clocks and is used for realizing coarse-precision time-to-digital conversion. The data cache unit is composed of a first-in first-out queue FIFO and used for temporarily caching data, the measurement result is cached in the FIFO so as to wait for an external device to read the data according to the reading sequence of the cache unit, and the corresponding storage space of the cache unit is released after the data is read; in the case of multiple channels, the measurement data for each channel is buffered in a FIFO together with its own channel number tag ID, so that the data of each channel is identified after the data is read out.

The FPGA is a field programmable logic device, logic is designed by using hardware programming languages such as VHDL or VerilogHDL (very high frequency description language) and the like, then files are generated by corresponding compiling comprehensive software according to logic design and setting, and the files are downloaded and configured to the corresponding FPGA so that the FPGA automatically realizes specific circuit connection of a bottom layer.

The time-to-digital conversion method applying the FPGA-based time-to-digital converter comprises the following steps:

step one, utilizing an interpolation method to measure fine time;

the special carry connecting lines in the FPGA are cascaded into a time delay line, namely a time interpolation chain, by utilizing a multi-bit adder or an addition carry primitive, so that the time interpolation of the clock period is realized. The input signal to be tested is transmitted on the time delay line, the output of the time delay line is gradually changed from low level to high level, the sampling circuit of the time delay line utilizes the clock signal to latch the output signal on the time delay line, and the time information transmitted on the time delay line by the input signal to be tested can be judged and analyzed from the data obtained by latching; the transmission time of the input signals to be measured arriving at different times on the time delay line is different, so that the arrival time information of the input signals to be measured, namely the fine time measurement, can be accurately measured.

Step two, encoding the locked data;

thermometer code data (thermometercode) output by the time delay line sampling circuit is encoded by using a binary search encoding scheme, and a pipeline technology is adopted when encoding is carried out.

Step three, carrying out coarse time measurement by two high-speed synchronous counters under the normal phase system clock and the reverse phase system clock;

in order to more reliably obtain the counting value when the input signal to be measured arrives, two counters working under a normal phase clock and a reverse phase clock are designed in the FPGA, and the stable and reliable counting value is judged and selected according to data obtained by fine time measurement and is used as a coarse time measurement value, so that coarse precision time-to-digital conversion of the signal to be measured is realized.

Step four, storing the digital information measured by the fine time measuring unit and the coarse time measuring unit into a data cache unit, and waiting for reading of an external device;

the data buffer unit is composed of a first-in first-out queue FIFO, and the external device reads the time measurement information according to the reading sequence of the FIFO.

In different system clock cycles, the number of stages (carry line number) used by the time delay line is different, and the number of stages used by the time delay line is in direct proportion to the system clock cycle, so that the method can estimate the minimum measurement unit (LSB or Bin) through the number of stages of delay lines used in two different clocks. Assuming that in the case of the clock period T1, the number of stages used by the time delay line is N1; in the case of the clock period T2, the number of stages used in the time delay line is N2, and the minimum measurement unit size is $\frac{T2-T1}{N2-\mathrm{<figure-callout\; id="1"\; label="N"\; filenames="C200510200340E00132.png"\; state="\{\{state\}\}">N</figure-callout>}1}.$

The invention is realized in FPGA, and has the following characteristics:

first, the use is flexible. The flexibility is the biggest characteristic of realizing the time-to-digital converter by using the FPGA. When the ASIC of the integrated circuit with special application is used, all functions and the like are designed well and fixed, and basically, no flexibility exists, and a user can only carry out corresponding design according to the ASIC. The FPGA is a programmable logic device, so that a user can design logic according to own needs and can work after solidifying and downloading the logic into the FPGA. The flexibility of the present invention includes the following aspects:

1. the function is flexible, and the logic function unit can be added, deleted and modified according to various requirements;

2. the number of channels is flexible, and an FPGA device with reasonable capacity can be selected according to actual requirements to realize a time-to-digital converter with proper number of channels;

3. the precision is flexible, the time measurement precision which can be realized by FPGA devices of different suppliers, different series, different capacities and different speed grades is different, and the FPGA devices can be selected according to the precision requirement, the cost and the like, so that the required measurement precision is realized;

4. the time measuring range is determined by the system clock and the digit of the counter, and the digit of the counter can be designed according to various requirements under the condition that the system clock is certain, so that the required time measuring range is realized;

5. the interface is flexible, and the FPGA has the characteristics that the logic can be changed, the level can be selected, and the like, so that the time-to-digital converter designed based on the FPGA is very flexible in the aspect of the interface and can meet the level requirement of a mainstream interface.

Secondly, the cost performance is high. The time-to-digital converter is realized by FPGA (field programmable gate array) with the best time precision of dozens of picoseconds (10)^-12Second), if the combination time amplification technology can reach several picoseconds, the requirements of most experiments and applications at present can be met. On the other hand, the FPGA is widely used and the price is lower and lower at present. The development cost of the opposite ASIC is higher, and although the precision can be made higher, the cost performance is lower from the point of view of cost performance. The time cost is low by utilizing the FPGA under the condition of obtaining the time-to-digital conversion with the same precision, so that the cost performance is high.

Drawings

FIG. 1 is a functional block diagram of the principles of the present invention;

FIG. 2 is a functional block diagram of the principle of the time delay line implementation of the present invention;

FIG. 3 is a functional block diagram of the principle of coarse time measurement in the present invention;

fig. 4 is a timing diagram of coarse time measurement in the present invention.

Detailed Description

The invention is described in further detail below with reference to the accompanying drawings:

as shown in fig. 1, the time-to-digital converter of the present invention includes a fine time measuring unit, an encoding unit, a coarse time measuring unit, and a data buffering unit, which are all implemented in an FPGA.

The fine time measurement unit utilizes a multi-bit adder or an addition carry primitive to cascade special carry connecting lines in the FPGA to form a time delay line, and a corresponding compiling synthesis option needs to be set in design software of an FPGA supplier, for example, in ISE integrated software of Xilinx company, an Optimization Goal option under a Synthesis-XST attribute is set to be Area, and the like. The field programmable logic device FPGA is more and more widely applied to modern electronic design, the performance is gradually improved, the price is gradually reduced, and the field programmable logic device FPGA is widely applied to various fields. In a common FPGA, a fixed dedicated connection line with a very small delay time, especially a dedicated carry connection line, is commonly used to implement fast digital signal processing, algorithms, and the like. The special carry lines are usually used for digital signal processing, but the invention skillfully utilizes the special carry lines, converts the original use of the special carry lines, provides a new using method, and utilizes methods such as a multi-bit adder or an addition carry primitive and the like to cascade the special carry lines in the FPGA to form a time delay line, after an input end of the time delay line receives an input signal to be tested, a blocking signal is generated by utilizing a sampling signal of a time delay line sampling circuit, namely a D trigger, and then the sampling circuit of the time delay line is closed. And latching the output signal of the time delay line by using a D trigger, namely a sampling circuit, in the same logic unit corresponding to the time delay line at the first rising edge of the clock signal after the input signal to be detected is input into the time delay line, latching the output signal by using a D trigger in the same logic unit corresponding to the first stage of the time delay line, and closing all D triggers corresponding to the time delay line at the next second rising edge of the clock signal.

When implemented using a multi-bit adder, as shown in fig. 2, the summands of the multi-bit adder are all set to 1, the addends are all set to 0 except for the least significant bit, and the least significant bit of the addend is used as the input of the external Hit signal to be measured. When there is no signal input, i.e., the lowest order bit is 0, all outputs of the multi-bit adder are 1; when there is a Hit signal to be measured input, i.e., the lowest order bit is 1, the output of the multi-bit adder is gradually changed from the low order bit to the high order bit to 0.

When the carry addition primitive is used for implementation, the special carry connecting lines are cascaded by using multi-stage carry addition primitives to form a time delay line, and the output of each stage of carry addition primitives is led out as the output of the time delay line. Firstly, the input Hit signal to be tested is subjected to AND operation with the fixed signal 1, so that the Hit signal to be tested is led to the input end of the time delay line. When a Hit signal to be measured is input, the signal is gradually transmitted from the input end along the time delay line, and the output of the time delay line is gradually changed from low to high to 1.

The specific working process of the time-to-digital converter comprises the following steps: and a positive phase system clock and a reverse phase system clock are provided from the outside, an external Hit signal to be detected is input into the fine time measuring unit and transmitted on the time delay line, and a sampling circuit of the time delay line acquires data on the rising edge of the clock signal. After the effective data is collected, the signal output by the sampling circuit is closed, and the sampling circuit of the time delay line, namely the D trigger and the D trigger for latching the counting value in the coarse time measurement, so that the output of the D trigger is always kept as the output before the closing. A sampling circuit of the time delay line outputs thermometer code data, namely Q output in the graph; the fine time measuring unit simultaneously outputs a Disable signal for turning off the D flip-flop latching the count value in the coarse time measuring unit. Thermometer Code data is input into the encoding unit, the encoding unit encodes the thermometer Code data and outputs the thermometer Code data, such as Code output in the figure, and simultaneously outputs corresponding selection and Control signals, such as Select and Control signals in the figure, so as to Control the counting value selection and data writing in the cache unit in the rough time measuring unit. The coarse time measuring unit works under a system clock and an inverted system clock, the D flip-flop of the sampling circuit of the fine time measuring unit is closed, meanwhile, a closing signal input by the fine time measuring unit is used for closing the latching sampling D flip-flop of the counter in the coarse time measuring unit, and then one of two counting values is selected as a coarse time measuring value according to a selection signal output by the encoding unit. The data output by the coding unit and the data output by the coarse time measurement are used as the input of a buffer unit, the writing clock signal of the buffer unit is obtained by frequency division from a system clock, the writing operation is carried out under the control of the control signal output by the coding unit, the writing clock is obtained by frequency division from the system clock, the written data is written according to a predefined data format, and a channel mark number ID is added. The buffer unit outputs a full or empty state indication signal, when the external device detects that the buffer unit is not empty, the external device sends a read signal to read the data of the buffer unit under the control of an externally provided read clock, namely, the measurement information is measured, and the buffer unit outputs the data.

The time-to-digital conversion method applying the FPGA-based time-to-digital converter comprises the following steps:

step one, utilizing an interpolation method to measure fine time;

the fine time measurement in the invention applies the time interpolation principle to interpolate the time of the clock period, namely, the time delay line of each stage is used for equally dividing the clock period, thereby greatly improving the precision of the time measurement. For example, if the system clock is 200MHz, i.e. the clock period is 5ns, the measurement accuracy that can be achieved after 50-level equal interpolation is performed on the system clock by 50 equal divisions is 100ps, and if the system clock is 100 equal divisions, the measurement accuracy that can be achieved is 50 ps.

And at the first rising edge of the clock signal after the Hit signal to be detected is input into the time delay line, latching the output signal of the time delay line by using a D flip-flop, namely a sampling circuit, in the same logic unit corresponding to the time delay line, so that the time information of the Hit signal to be detected transmitted on the time delay line can be judged and obtained from the latched data, and the time of the Hit signal to be detected arriving at different times transmitted on the time delay line is different, thereby measuring the time of the Hit signal to be detected arriving. In order to guarantee the processing time of the Hit signal to be detected each time, after the Hit signal to be detected is input, the output signal is latched by using the D flip-flops corresponding to the first stage of the time delay line, all the D flip-flops corresponding to the time delay line are closed (not enabled) on the second rising edge of the clock signal, and subsequent input signals are not processed. After the data latched by the D flip-flops is sent to the next-stage processing unit, all the D flip-flops corresponding to the time delay line are opened (enabled) to start the next time measurement.

Step two, encoding the locked data;

the latched data is thermometer code data, which is encoded to compress the width of the data bit number. The specific process of encoding is that a jump point of data is searched from thermometer code data output by fine time measurement, and the position information of the jump point is output in a binary form, for example, thermometer code data originally having 127 bit width is encoded into binary data having 7bit width: the output data of the fine time measurement is 111111000000000 from low order to high order, and the binary data of the encoded output is 0110 from low order to high order, namely decimal 6.

It can be encoded using various encoding algorithms, for example, using a binary search encoding scheme commonly used in ordinary analog-to-digital conversion (ADC). According to the basic thought of the binary search, firstly, checking intermediate data of output data of a time delay line, judging whether a Hit signal to be detected arrives at the intermediate data, and if so, continuously checking output data of the latter half part by using a binary search method; if not, the half-folded search method is continuously used for checking the output data of the first half part. The above steps are repeated until the exact end point of the Hit signal to be detected is found out, that is, the end point of the Hit signal to be detected transmitted on the time delay line when the time delay line is latched, so that the transmission time information of the Hit signal to be detected on the time delay line can be obtained. If the output data measured by the fine time is 111111000000000 from the low order to the high order, firstly judging whether the 8 th Bit (Bit) is 1, if so, continuing to use the halving search method in the second half part, and since 0 is not 1, continuing to use the halving search method in the first half part; then judging whether the 4 th Bit is 1, and continuously searching the second half part, namely the 5 th-7 th Bit because the Bit is 1; judging whether the 6 th Bit is 1 or not, and continuing to search the second half part because the Bit is 1; and judging that the 7 th Bit is 0, so that the transmission end point of the input signal to be detected on the time delay line is the 6 th Bit, and the binary data output by encoding is 0110 from the low Bit to the high Bit, namely decimal 6.

And processing the Hit signal measurement data to be measured by adopting a pipeline technology. The basic idea of pipelining is to break a process into several sub-processes, each of which can be effectively executed on its dedicated functional segment simultaneously with the other sub-processes, thereby reducing the dead time of the process. The invention uses the pipeline technology when encoding the fine time measurement output data, and the concrete processing process is as follows: under the control of a clock, the first-stage processing judges the first step of the coding scheme, the second-stage processing judges the second step of the coding scheme, and so on, the first-stage processing finally completes the whole half-seeking coding and outputs the coded data.

Step three, carrying out coarse time measurement by two high-speed synchronous counters under the normal phase system clock and the reverse phase system clock;

to obtain a robust and reliable coarse time measurement, two high-speed synchronous counters operating on the positive and negative system clocks are used to form the coarse time measurement unit, as shown in fig. 3 and 4. From the data obtained by the fine time measurement, whether the Hit signal to be measured arrives in the first half period or the second half period of the system clock can be judged, and if the Hit signal to be measured arrives in the first half period of the system clock, the counting value of a counter working under the reversed phase system clock is latched and selected as a coarse time measurement value; if the system clock is in the second half period, the counting value of the counter working under the positive phase system clock is latched and selected as the coarse time measurement value.

Step four, storing the digital information measured by the fine time measuring unit and the coarse time measuring unit into a data cache unit, and waiting for reading of an external device;

the fine time measurement and the coarse time measurement form a complete time measurement, digital information obtained by measurement is cached in a double-port FIFO according to a predefined data format, a write-in clock is obtained by frequency division from a system clock according to needs, a read clock is input from the outside to facilitate external data reading, and the read clock and the write-in clock can be the same clock. In the case of multiple channels, the data is buffered in the FIFO and the tag number ID of each channel is added. The information of the FIFO and the read control leave an interface from which the time measurement information can be read externally according to the read timing requirements of the FIFO.

In addition to the above functions, the present invention may also provide reset and enable control signals that allow a user to reset the entire time-to-digital converter as desired, and to enable and disable the operation of the time-to-digital converter as desired. For a multi-channel time-to-digital converter, some channels may be enabled but not others according to the needs of the user. In addition, the invention also provides detection information of each channel, and a high-level pulse is output when a to-be-detected input Hit signal is detected.

Because the delay sizes of the dedicated incoming lines in the FPGAs of different suppliers, different series, different capacities and different speed grades are different, the minimum measurement unit, the linear performance, the measurement accuracy and the cost of the time-to-digital converter realized by the FPGAs of different suppliers, different series, different capacities and different speed grades are different. A6-channel time-to-digital converter implemented on an ACEK1K series EP1K50TC144-1 device from Altera corporation has a minimum measurement cell (LSB) of 112.5 picoseconds, an Integral Nonlinearity (INL) of between-0.567/0.697 LSB, a Differential Nonlinearity (DNL) of between-0.416/0.783 LSB, a measurement accuracy of 81.519 picoseconds, and a cost of about 200 dollars. A32-channel time-to-digital converter is realized on a Virtex II series XC2V4000-6BF957 device of Xilinx company, the minimum measurement unit (LSB) of the converter is 69.444 picoseconds, the Integral Nonlinearity (INL) of the converter is between-2.003 and 1.855 LSB, the Differential Nonlinearity (DNL) of the converter is between-0.953 and 1.051 LSB, the measurement precision is 66.172 picoseconds, and the cost is about 3000 yuan.

Claims (7)

1. The [ claim 1 ] a time-to-digital converter based on FPGA, provided with a fine time measuring unit, a coding unit, a coarse time measuring unit and a data buffering unit, characterized in that the above units are all implemented in FPGA; wherein,

   the fine time measuring unit is cascaded into a time delay line by utilizing a special carry connecting line in the FPGA to perform time interpolation on a clock period, so that high-precision time-to-digital conversion is realized;

   the coding unit is used for coding the data output by the high-precision time-to-digital conversion, namely coding the data with wide output bit number and compressing the width of the data bit number;

   the coarse time measuring unit consists of two high-speed synchronous counters working under normal phase and reverse phase system clocks and is used for realizing coarse precision time-to-digital conversion;

   the data cache unit is composed of a first-in first-out queue FIFO and used for temporarily caching data, the measurement result is cached in the FIFO so as to wait for an external device to read the data according to the reading sequence of the cache unit, and the corresponding storage space of the cache unit is released after the data is read;

   during measurement, the fine time measurement unit utilizes a time delay line formed by cascading special carry connecting lines in the FPGA to perform time interpolation on a clock period to realize fine time measurement, the coarse time measurement unit utilizes two high-speed synchronous counters in the FPGA to perform cycle counting work under a normal phase clock and a reverse phase clock respectively, and meanwhile, a D trigger is used for latching a count value output by the counter; the sampling circuit of the time delay line outputs data to the coding unit for coding, and a selection signal is output during coding to select two count values under a positive phase clock and a negative phase clock in the coarse time measurement unit, and one count value is selected as a coarse time measurement value; the fine time measurement data and the coarse time measurement value which are output by the coding unit are written into the cache unit under the control of the control signal output by the coding unit by adding the channel number of each measurement channel, and the write clock is obtained by frequency division of the system clock; the buffer unit can automatically output full or empty state signals, and when the external part detects a non-empty state, the external part sends out read signals to read the data of the buffer unit under the control of a read clock provided by the external part, namely the measured time information.
2. An FPGA-based time-to-digital converter according to claim 1, wherein said fine time measurement unit is implemented by concatenating dedicated carry wires in the FPGA into time delay lines using multi-bit adders or carry-add primitives.
3. The FPGA-based time-to-digital converter according to claim 1, wherein said coding units are coded using a binary search coding scheme.
4. An FPGA-based time-to-digital converter as claimed in claim 1 or 3, characterized in that said coding unit is coded using pipelining.
5. An FPGA-based time-to-digital converter as claimed in claim 1, wherein said data buffer unit buffers data, and in the case of multiple channels, the measurement data of each channel is buffered in FIFO together with its own channel number tag ID.
6. The time-to-digital conversion method using the FPGA-based time-to-digital converter according to claim 1, wherein the method is implemented by the following steps:

   step one, utilizing an interpolation method to measure the fine time:

   the special carry connecting line in the FPGA is cascaded into a time delay line by utilizing a multi-bit adder or an addition carry primitive, namely a time interpolation chain, and time interpolation is carried out on a clock cycle, so that high-precision time-to-digital conversion of a signal to be detected is realized; the method comprises the steps that at the first rising edge of a clock signal after an input signal to be detected is input into a time delay line, a D trigger, namely a sampling circuit, in the same logic unit corresponding to the time delay line is used for latching an output signal of the time delay line, then the D trigger in the same logic unit corresponding to the first stage of the time delay line is used for latching the output signal, and all D triggers corresponding to the time delay line are closed at the next second rising edge of the clock signal;

   step (two), encoding the latched data:

   the thermometer code data output by the time delay line sampling circuit is encoded by using a binary search encoding scheme, and a pipeline technology is adopted during encoding;

   step three, carrying out coarse time measurement by two high-speed synchronous counters under the positive phase system clock and the negative phase system clock:

   in order to more reliably obtain the counting value when the input signal to be measured arrives, two counters working under a normal phase clock and a reverse phase clock are designed in the FPGA, and the stable and reliable counting value is judged and selected according to the data obtained by measuring the fine time and is used as a coarse time measuring value, so that the coarse precision time-digital conversion of the signal to be measured is realized;

   step (IV), storing the digital information measured by the fine time measuring unit and the coarse time measuring unit into a data cache unit, and waiting for the reading of an external device:

   the external device reads the time measurement information according to the read sequence of the FIFO.
7. An FPGA-based time-to-digital conversion method according to claim 6, characterized in that the method estimates the minimum measurement unit by the number of stages of the delay line used in two different clocks, and when the number of stages used in the time delay line is N1 in the case of the clock period T1 and N2 in the case of the clock period T2, the minimum measurement unit size is

   

Images