CN101453300B - Control system for space payload channel encoding - Google Patents

Control system for space payload channel encoding Download PDF

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CN101453300B
CN101453300B CN 200810182418 CN200810182418A CN101453300B CN 101453300 B CN101453300 B CN 101453300B CN 200810182418 CN200810182418 CN 200810182418 CN 200810182418 A CN200810182418 A CN 200810182418A CN 101453300 B CN101453300 B CN 101453300B
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data
unit
coding
system
control
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CN101453300A (en )
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孙辉先
安军社
汪大星
滕学剑
白云飞
陈晓敏
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中国科学院空间科学与应用研究中心
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Abstract

The invention relates to a space effective payload channel coding control system, which comprises a system clock unit, a data scheduling unit, an error correction coding unit, a data conversion unit, and a data aggregation unit, wherein the system clock unit is respectively and electrically connected with a speed regulation and control unit, the data scheduling unit, the error correction coding unit and an interface of the data conversion unit; the data scheduling unit schedules the data signal flow according to the load data traffic of various paths and by combining system speed regulation and control status signals of the speed regulation and control unit; the error correction coding unit receives the control of a task source signal C, reads load bus data converted by the data conversion unit, and implements interleaving channel coding on the load bus data; the data conversion unit receives the control of the data scheduling unit, and transmits various load data source signals B to a load data bus; and the data aggregation unit receives coded data controlled and generated by the error correction coding unit, and combines the coding data and a task source signal D into a data transmission frame which is then controlled and outputted through a port. The system is particularly suitable to be used by a spatial embedded system, and has high reliability and stability, small space resources required and low energy consumption.

Description

一种空间有效载荷信道编码控制系统 A spatial channel coding payload control system

技术领域 FIELD

[0001] 本发明涉及一种数字信号控制系统,特别是涉及一种适用于空间应用的嵌入式系统的、基于全数字逻辑电路的有效载荷信道编码控制系统。 [0001] The present invention relates to a digital signal control system, particularly to a space suitable for embedded system applications, the payload channel coding control system based on digital logic circuits.

背景技术 Background technique

[0002] 在空间信息通信过程中,为了获得一定编码增益,对于目前的有效载荷数据实施信道编码是十分必要的,但在实际空间应用过程中存在一些不足,例如2007年11月刊登在《机器人》第四卷第沈期上的文献1《适用于空间机器人遥操作系统数据通信的纠错编码》所记载的:该系统采用数字集成电路针对通信数据进行二进制比特串的表示形式转换工作,并且最终通过计算机软件实现信道的特定编码任务。 [0002] In the space of information and communication process in order to obtain a certain coding gain for the current payload data according to channel coding is necessary, but there are some deficiencies in the actual space application process, for example, in November 2007, published in the "robot "document on the fourth volume of the first sink 1" for space teleoperation error correction coding data communication system "described: the system uses a digital representation of an integrated circuit for a binary bit string of the communication data conversion work, and particular coding task ultimately channel by a computer software. 通过深入分析其信道编码实现过程,发现如下有待改进之处: By analyzing its channel coding process is implemented, the improvement was found to be as follows:

[0003] A、信道编码及其控制需要计算机系统及其软件协助工作; [0003] A, channel coding and control requires a computer system and its software assisted;

[0004] B、采用标准的数字集成电路以及计算机系统,实现信道编码转化及其控制,不但浪费空间资源,而且消耗较多能源; [0004] B, using standard digital integrated circuits and computer systems, to achieve transformation and channel coding control, not only a waste of space resources, and consumes more energy;

[0005] C、受空间系统资源限制,其纠错编码及其控制缺乏灵活性; [0005] C, by the system resource space limitations, which controls the error correction coding and the lack of flexibility;

[0006] D、信息处理速度难以适应高速率的发展需求。 [0006] D, information processing speed is difficult to meet the development needs of high rates.

发明内容 SUMMARY

[0007] 本发明的目的是克服采用标准的数字集成电路和计算机系统及其软件实现信道编码及其控制,不但浪费空间资源,而且消耗较多能源的缺陷;为了适用于嵌入式系统应用,从而提供一种基于全数字逻辑电路的空间有效载荷信道编码控制系统,该系统具有较高的可靠性和高速的信息处理能力。 [0007] The object of the present invention is to overcome the digital integrated circuits and computer system using standard software and channel coding and control, not only a waste of space resources, and energy consumption of more defects; for embedded system applications in order to space is provided a digital logic circuit payload channel coding based control system, the system having high reliability and high-speed information processing capability.

[0008] 为了实现上述目的,本发明提供了一种空间有效载荷信道编码控制系统,包括: [0008] To achieve the above object, the present invention provides a spatial channel coding payload control system, comprising:

[0009] 系统时钟单元1,为其提供用于运行的基本工作时钟;所述的系统时钟单元1分别与速率调控单元2、数据调度单元3、纠错编码单元4和数据转换单元5接口电连接; [0009] The system clock unit 1, to provide for running basic operation clock; the system clock rate regulation unit 1 and unit 2 respectively, data scheduling unit 3, an error correction coding unit 4 and data conversion interface circuit unit 5 connection;

[0010] 速率调控单元2,接受任务源信号A控制,切换系统输出数据速率,并与数据调度单元3和数据转换单元5以及数据聚合单元6接口电连接,为数据调度单元3提供系统速率调控状态信号,为数据聚合单元6提供数据输出速率信号,为数据转换单元5提供载荷时钟信号监测,并输出遥测信号F; [0010] Rate-control unit 2, receiving task source signal A controlled switching system output data rates, and connected to the data scheduling unit 3 and the data conversion unit 5, and data aggregation unit 6 interface circuit, the data scheduling unit providing system speed regulation 3 state signal, the data polymerized units 6 provides a data output rate signal, the clock signal to provide a load monitoring the data converting unit 5, and the output telemetry signals F.;

[0011] 数据调度单元3,根据各通路载荷数据输入流量,以及结合速率调控单元2的系统速率调控状态信号,调度数据转换单元5的载荷数据信号流向; [0011] The data scheduling unit 3, the system rate regulation unit 2 state signal, the payload data schedule data conversion unit according to each of the signal flow input paths payload data traffic, and the association rate regulation 5;

[0012] 纠错编码单元4,接受任务源信号C控制,设置纠错编码的交错深度,用于控制数据转换单元5转来的各通路的载荷输入数据实施纠错编码; [0012] The error correction encoding unit 4, the control signal C source accepts the task, provided the depth of interleaving of the error correction coding, the input data for controlling the load transferred to the converting unit 5 in the embodiment of error correction coding of each passage;

[0013] 数据转换单元5,接收各载荷数据源信号B,用于串行输入数据流的串/并转换及数据缓冲,提供各载荷数据输入状态,并接受数据调度单元3的控制,将各载荷数据转送至载荷数据总线;[0014] 数据聚合单元6,接收经过纠错编码单元4控制生成的纠错编码数据,与任务源信号D合成数据传输帧数据信号,经数据聚合单元6的端口E控制发送输出。 [0013] The data converting unit 5 receives each payload data source signal B, serial input data stream to serial / parallel conversion and data buffers, each providing payload data input state, and accepts data scheduling control unit 3, each payload data of the payload data transferred to the bus; 6, after receiving the error correction coding error correction encoded data generated by the control unit 4, and task D synthetic data source signal frame data signal transmitted via the data port polymerized units [0014] the data aggregation unit 6 E controls the transmission output.

[0015] 上述技术方案中,所述的速率切换单元2中包含了一组级联方式构建的同步计数电路,以及多路选择逻辑电路,由此控制速率切换;并且设置了五组由单稳态触发电路构成的信号速率检测电路,监控各载荷输入数据速率和输出的信道时钟速率的变化。 [0015] In the above technical solution, the rate of the switching unit 2 includes a set of synchronization counter circuit constructed in cascade, and a multiplexer select logic circuit, thereby controlling the rate of handover; and the group consisting of five provided monostable state rate detecting circuit trigger signal circuit configured to monitor changes of load input and output data rate of the channel clock rate.

[0016] 上述技术方案中,所述的数据调度单元3中包含了两个独立的8位信号锁存电路, 并且配置了数据调度部件,该功能单元根据锁存的当前各载荷数据输入状态,同时结合系统速率状态,输出载荷数据选取信号,由此控制各通路载荷数据流向。 [0016] The above technical solution, the data scheduling unit 3 includes two separate 8-bit signal of the latch circuit, and configured scheduling data means, each of the current load state of the unit data input of a latch, and combined with the system rate, the output signal selected payload data, thereby controlling the flow of payload data of each channel.

[0017] 上述技术方案中,所述的纠错编码交错单元4中包含了两组结构和功能对等同步运行的数据交错波盘电路,以及五组8位信号锁存电路和对应的信道编码电路,由此控制载荷数据进行信道编码的交错流转。 [0017] The above technical solution, the interleave error correction coding unit 4 contains two data interleaving circuit odds like structure and function of synchronized operation, and five sets of latch circuits and 8-bit signal corresponding to the channel coding circuit, whereby the load of the control data channel coding interleaving flow.

[0018] 上述技术方案中,所述的有效载荷数据转换单元5中包含了四个独立的8位串行至并行数据转换电路和对应的数据缓冲电路。 [0018] In the above aspect, the payload data conversion unit 5 contains four independent 8-bit serial to parallel data conversion circuits and a corresponding data buffer circuit.

[0019] 上述技术方案中,所述的数据聚合单元6中包含了数据聚合部件、伪随机化处理部件、数据帧同步部件以及8位并行至串行数据转换电路。 [0019] In the above technical solution, the data aggregation unit 6 comprises a polymeric component data, the pseudo random processing means, the synchronization data frame member 8 and the parallel to serial data conversion circuit. 数据聚合部件将系统勤务信息添加在每一经过交错编码的载荷数据帧起始部分,随后按位实施伪随机化操作,之后添加同步信息,最终完成数据并/串转换工作。 Data member polymerization system after each service information adding part load start interlaced coded data frame, then a pseudo-random bit operation embodiment, after addition of the synchronization information, and data is finalized / serial conversion work.

[0020] 本发明除系统时钟单元1外,其它电路如速率调控单元2、数据调度单元3、纠错编码交错单元4、数据转换单元5和数据聚合单元6集成在同一片FPGA中,用VHDL语言描述方式实现的。 [0020] The present invention is an addition to the system clock unit, other circuits such as a rate-control unit 2, a data scheduling unit 3, interleave error correction encoding unit 4, the data conversion unit 5 and data aggregation unit 6 integrated in a single FPGA, using VHDL language to describe the way to achieve.

[0021] 本发明的系统相对于已有技术具有如下优点: [0021] The system of the present invention over the prior art has the following advantages:

[0022] 对于本发明的技术方案与采用标准的数字集成电路以及计算机系统实现信道编码及其控制系统来说,由于本发明的技术方案是基于全数字逻辑电路,将电路如速率调控单元2、数据调度单元3、纠错编码交错单元4、数据转换单元5和数据聚合单元6集成在同一片FPGA中,用VHDL语言描述方式实现的。 [0022] For the aspect of the present invention is achieved using a standard digital integrated circuits and computer systems and channel coding and control system, since the aspect of the present invention is based on digital logic circuit, a circuit for rate regulation unit 2, the data scheduling unit 3, interleave error correction encoding unit 4, the data conversion unit 5 and data aggregation unit 6 integrated in a single FPGA, a manner described in the VHDL language. 所以特别适合于空间嵌入式系统的应用,而且可靠性和稳定性较高,所需空间资源少、能源消耗较低。 It is particularly suitable for space applications for embedded systems, and high reliability and stability, less space required resources, lower energy consumption. 就设计方法而言,易于VHDL语言描述实现,还可以根据空间任务需求,在线配置载荷数据调度方式、编码控制机制和调控数据输出速率。 In terms of design method, VHDL language easy to realize, may also be configured payload data scheduling, encoding and control mechanism in accordance with data output rate regulation space mission requirements, online.

附图说明 BRIEF DESCRIPTION

[0023] 图1是本发明的空间有效载荷信道编码控制系统组成图 [0023] FIG. 1 is a composition diagram of the present invention, the spatial channel coding payload control system

[0024] 图2是本发明的控制系统中使用的速率调控单元组成结构图 [0024] FIG 2 is a control system of the present invention is used in regulation of the rate of structural units of FIG.

[0025] 图3是本发明的控制系统中使用的数据调度单元组成结构图 [0025] FIG. 3 is a data configuration diagram of scheduling units in the control system of the present invention for use

[0026] 图4是本发明的控制系统中使用的纠错编码交错单元组成结构图 [0026] FIG 4 is a configuration diagram of a control system of units according to the present invention is used in the error correction encoding interlace

[0027] 图5是本发明的控制系统中使用的数据转换单元的组成结构图 [0027] FIG 5 is a configuration diagram of a data converting unit consisting of a control system used in the present invention

[0028] 图6是本发明的控制系统中使用的数据聚合单元的组成结构图 [0028] FIG. 6 is a diagram showing a data structure composed of polymerized units of a control system used in the present invention

具体实施方式 detailed description

[0029] 为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图和实施例进 [0029] To make the objectives, technical solutions and advantages of the present invention will become more apparent from, the accompanying drawings and the following embodiment Examples intake

5一步详细说明本发明。 5 of the present invention is described in further detail.

[0030] 参照图1,制作一种空间有效载荷信道编码控制系统,在该系统中系统时钟单元1 采用市场上采购的适合于空间应用的晶体振荡器,所述的系统时钟可至百兆赫兹,纠错编码的交错深度可达到5级,接收的载荷数据通路可根据所用的FPGA资源进行扩展,这对于本领域技术人员来说是可以胜任的。 [0030] Referring to FIG 1, a payload A spatial channel coding control system, the system uses a system clock unit purchasing on the market suitable for space applications crystal oscillator, the system clock up to hundreds of megahertz , error correction coding interleaving depth can reach 5, the received payload data path can be extended according FPGA resources used, which is capable of ordinary skill in the art. 该系统时钟单元1分别为速率调控单元2、数据调度单元3、纠错编码单元4和数据转换单元5提供基本工作时钟。 The system clock unit 1 2, respectively, the data scheduling unit 3, an error correction encoding unit 4 for the basic operation clock rate regulation unit and the data converting unit 5. 各有效载荷数据经过数据转换单元5规整,由数据调度单元3根据其状态控制数据的流向,经过纠错编码交错单元4控制数据帧按照交错方式形成编码数据帧,同时,速率调控单元2根据系统要求产生基带时钟, 最终数据聚合单元6将有效载荷数据整合成符合协议要求的基带信号。 Each payload data subjected to the data conversion unit 5 structured, controlled by the data scheduling unit 3 according to its state of the flow of data through the error correction encoding unit 4 controls the interleave encoded data frames forming a data frame in a staggered manner, while the rate-control unit 2 according to the system required to generate the baseband clock, the last data payload 6 polymerized units of the baseband signal into a data integration meet the protocol requirements.

[0031] 速率调控单元2的内部结构组成如图2所示,由计数器、速率调控部件2-8和速率检测部件电连接构成。 The internal structure of [0031] the composition rate regulation unit 2 shown in Figure 2, by a counter, and the rate of 2-8 rate detecting means electrically connected to the regulation member configured. 其中,计数器是两个以级联方式互联的8位同步计数器电路(即第一8位同步计数器电路2-1和第二8位同步计数器电路2-2~);多路选择逻辑电路构成速率调控部件;由五个单稳态触发电路电连接构成速率检测部件(即附图2中的速率检测电路2-3、2-4、2-5、2-6和速率检测电路2_7)。 Wherein the counters are interconnected in cascade two 8-bit sync counter circuit (i.e., a first 8-bit sync counter circuit 21 and the second synchronous counter circuits 8 ~ 2-2); multiplexer logic configured rate regulation member; five monostable circuit means electrically connected to the trigger rate detector configuration (i.e., in the drawings rate and a rate detection circuit detecting circuit 2_7 2-3,2-4,2-5,2-6). 8位同步计数电路2_1和2_2以系统时钟作为工作的激励信号,速率调控部件根据系统对速率的设定,选取分频链路;同时,速率检测部件对四路载荷数据信号速率和实际选用的信道时钟速率进行监测,并为系统提供遥测信息。 8-bit sync counter circuit 2_1 and 2_2 as the excitation signal to the system clock operating rate regulation member system according to the rate set, the link selection division; simultaneously, means for detecting the rate of four data signal payload rate and the actual selection of monitoring the channel clock rate, and provide information to the telemetry system.

[0032] 数据调度单元3的内部结构组成如图3所示,主要由两个8位数据锁存电路与数据调度部件3-3电连接构成。 The internal structure [0032] The scheduling unit 3 composed of data shown in Figure 3, mainly by two electrical data latch circuit 8 and the data scheduling unit 3-3 connected configuration. 其中,第一8位数据锁存电路3-1用于监测当前各载荷数据输入状态,当任意载荷数据流达到各自设定流量时,将使第一8位数据锁存电路3-1相应信号置位,数据调度部件根据各载荷数据输入状态,同时结合系统速率状态,输出各载荷通路切换信息至第二8位数据锁存电路3-2,由此控制各通路载荷数据流的通量以及相互之间的比例关系。 Wherein, the first 8-bit data latch circuit 3-1 for monitoring current states of the respective input data load, when either the payload data stream when each reaches a set flow rate, will cause the first 3-1 signal corresponding data latch circuit 8 set, the data in each payload data according to the scheduling section input state, combined with the system rate state, the output of each load path switching message to the second 8-bit data latch circuit 3-2, whereby the respective control flux paths of payload data stream and proportional relationship between each other.

[0033] 纠错编码交错单元4的内部结构组成如图4所示,主要由两组数据交错部件、五组8位数据锁存电路和五组信道编码电路电连接构成。 [0033] The internal structure of the interleave error correction encoding unit 4 shown in Figure 4 consisting mainly by two sets of data interleaving means, five groups of 8-bit data latch circuits, and five sets of channel coding circuit electrically interconnected. 其中,数据交错部件是两组结构和功能对等、同步运行的数据交错波盘电路,按照系统预先设定的交错深度,选定五组8位数据锁存电路(即附图4中所示的锁存电路4-3、锁存电路4-5、锁存电路4-7、锁存电路4_9、锁存电路4-11)及其对应信道编码电路的配置(即附图4中所示的信道编码电路4-4、信道编码电路4-6、信道编码电路4-8、信道编码电路4-10、信道编码电路4-12)。 Wherein the two members are interleaved data structure and function and the like, data interleaving odds synchronous operation circuit, in accordance with a predetermined interleaving depth system, five groups of 8-bit data latch circuit selected (i.e. 4 shown in the drawings the latch circuit 4-3, 4_9, 4-11) and the channel coding configuration corresponds to a latch circuit the latch circuit 4-5, the latch circuit 4-7, the latch circuit (i.e., 4 shown in the drawings channel coding circuit 4-4, the channel coding circuit 4-6, the channel coding circuit 4-8, the channel coding circuits 4-10, 4-12 channel coding circuit). 数据交错部件4-1控制载荷数据按照锁存电路和信道编码电路序号,顺序从一个编码器转到另一个编码器,其间,数据交错部件4-2同步地控制数据从相应编码器输出,并且二数据交错部件配合控制,将生成的信道编码信息衔接在各载荷数据帧的结尾部分,从而实现以交错的方式完成对载荷数据帧的编码。 4-1 the control data interleaving means in accordance with the payload data latch circuit and the channel coding circuit number, sequence from one encoder to another encoder, therebetween, 4-2 in synchronization with data interleaving means outputs control data from the respective encoders, and interleaving second data with the control member, the channel encoded information generated at the end portion of each engagement frame payload data, thereby achieving a staggered manner to complete the payload data frame to be encoded. 为适应空间通信应用,编码电路选用符合CCSDS(国际空间数据系统咨询委员会)标准的REED(瑞德)-SOLOMON(所罗门)(255,223)编码方式。 To meet the space communications applications, coding circuit selected in line with CCSDS (International Advisory Committee for Space Data Systems) standards REED (Reid) -SOLOMON (Solomon) (255,223) encoding.

[0034] 数据转换单元5的内部结构组成如图5所示,主要由4个独立的8位串/并转换电路和对应的数据缓冲电路电连接构成,其中4个独立的8位串/并转换电路包括第一8 位串/并转换电路5-1、第二8位串/并转换电路5-2、第三8位串/并转换电路5-3、第四8位串/并转换电路5-4,以及对应的数据缓冲电路包括第一数据缓冲电路5-5、第二数据缓冲电路5-6、第三数据缓冲电路5-7、第四数据缓冲电路5-8 ;其功能将各载荷串行数据转换成并行数据,提供各载荷数据输入状态,并根据载荷数据选取信号,将载荷数据引至载荷数据总线。 The internal structure of [0034] the composition of the data converting unit 5 shown in Figure 5, mainly consists of four separate 8-bit serial / parallel conversion circuit and a corresponding data buffer circuit is electrically connected configuration, four separate 8-bit serial / 8 conversion circuit comprises a first serial / parallel converting circuit 5-1, a second eight serial / parallel conversion circuits 5-2, 8 third serial / parallel converting circuit 5-3, a fourth eight serial / 5-4 circuit and a corresponding data buffer circuit includes a first data buffer circuit 5-5, 5-6 of the second data buffer circuit, the third data buffer circuits 5-7, 5-8 of the fourth data buffer circuit; functional each load converting serial data into parallel data to provide payload data of each input state, and select a signal according to the load data, the payload data lead to the load data bus.

[0035] 数据聚合单元6的内部结构组成如图6所示,主要由数据聚合单元6-1、伪随机化电路6-2、数据帧同步电路6-3和8位并/串转换电路6-4电连接构成;其中,数据聚合单元6-1接收8位并行的特定长度的系统勤务信息,以及接收8位并行的经过交错编码的载荷数据帧,并将系统勤务信息添加在每一经过交错编码的载荷数据帧起始部分,随后从首位开始按位实施与伪随机化序列的模2加操作,伪随机化序列的生成多项式符合CCSDS-A0S标准的定义,之后再将32比特同步信息添加在编码后的载荷数据帧的头部,最终完成数据帧的并/串转换工作,从而形成串行的基带数据信号,这些对于本领域技术人员来说是可以胜任的。 [0035] The internal data structure composed of polymerized units 6 shown in Figure 6, it consists of data polymerized units 6-1, 6-2 pseudorandom circuit, a data frame synchronization circuit 6-3 and 8-bit parallel / serial converter circuit 6 -4 electrically connected to form; wherein the data aggregation unit 6-1 receives the 8-bit parallel information service system of a particular length, and after receiving eight parallel interlaced coded payload data frame, the information service system and added after each beginning portion interleaved payload data frame coding, then start from the first embodiment modulo pseudo random bit sequence of the add operation 2, the pseudo-random sequence generation polynomial meet the definition of CCSDS-A0S standard, then after 32 bits of synchronization information payload header added to the data frame encoded, the final completion of the parallel / serial conversion work data frame, thereby forming a serial baseband data signal, those of ordinary skill in the art is competent.

[0036] 在具体实施例系统中,系统时钟频率设为η = 12MHz,按照2的整数幂次分频调控输出信道的基带速率,载荷信源设定为m = 4个通路;纠错编码的交错深度设置为i = 2 ; 输出数据帧长度为1 = 512字节。 [0036] In a particular embodiment of the system, the system clock frequency is set to η = 12MHz, according to an integer divide-control channel baseband output power of speed, load the source is set to m = 4 passageways; error correction coded interleaving depth is set to i = 2; = 1 output data frame length is 512 bytes.

[0037] 在本实施例中除系统时钟单元1外,其它电路如速率调控单元2、数据调度单元3、 纠错编码交错单元4、数据转换单元5和数据聚合单元6集成在同一片FPGA中,用VHDL语言描述方式实现的。 [0037] In addition to the system clock unit 1, other circuits such as a rate-control unit 2, a data scheduling unit 3, interleaved error correction encoding unit 4 in the present embodiment, the data conversion unit 5 and the data aggregation unit 6 integrated in a single FPGA using VHDL language to describe the way to achieve.

Claims (9)

  1. 1. 一种空间有效载荷信道编码控制系统,包括:系统时钟单元(1),为系统提供用于运行的基本工作时钟;所述的系统时钟单元(1)分别与速率调控单元O)、数据调度单元(3)、纠错编码单元(4)和数据转换单元(¾接口电连接;速率调控单元(2),接受任务源信号A控制,切换系统输出数据速率,并与数据调度单元⑶和数据转换单元(5)以及数据聚合单元(6)接口电连接,为数据调度单元(3)提供系统速率调控状态信号,为数据聚合单元(6)提供数据输出速率信号,为数据转换单元(5) 提供载荷时钟信号监测;数据调度单元(3),根据各通路载荷数据输入流量,以及结合速率调控单元O)的系统速率调控状态信号,调度数据转换单元(5)的载荷数据信号流向;纠错编码单元G),接受任务源信号C控制,设置纠错编码的交错深度,用于控制数据转换单元(¾转来的 A spatial channel coding payload control system, comprising: a system clock unit (1), the system provides the basic clock for operating the work; said system clock unit (1) to the rate-control unit are O), data scheduling unit (3), error correction encoding means (4) and a data converting unit (¾ electrically connected to the interface; rate regulation unit (2), the task acceptance control A signal source, the switching system, output data rates, and the data scheduling unit and ⑶ a data converting unit (5) and a data polymerized units (6) connector electrically connected, a system rate-control state signal is a data scheduling unit (3), provides a data output rate signal data polymerized units (6), a data converting unit (5 ) providing a load clock signal monitoring; data scheduling unit (3), in accordance with various passages payload data input flow, and binding rate regulation unit O) system rate-control state signal, schedule data converting unit (5) is a load data signal flow; correction error encoding unit G), a source receiving the task control signal C, provided the error correction coding interleaving depth, for controlling the data conversion unit (¾ transferred to the 各通路的载荷输入数据实施纠错编码;数据转换单元(5),接收各载荷数据源信号(B),用于串行输入数据流的串/并转换和数据缓冲,提供各载荷数据输入状态,并接受数据调度单元(3)的控制,将各载荷数据转送至载荷数据总线;数据聚合单元(6),接收经过纠错编码单元(4)控制生成的纠错编码数据,与任务源信号D合成数据传输帧数据信号,经数据聚合单元(6)的端口E控制发送输出。 The load path of each input data error correction coding; data converting unit (5) for receiving respective payload data source signal (B), the serial input data stream for series / parallel conversion and data buffers, each providing payload data input state and receive data scheduling control unit (3), each of the payload data to the payload data transfer bus; data polymerized units (6), after receiving the error correction coding unit (4) controls the error correction encoded data generated by the task source signal D synthetic data transmission frame data signal, the data aggregation unit (6) controls the transmission output port E.
  2. 2.根据权利要求1所述的空间有效载荷信道编码控制系统,其特征在于,所述的速率调控单元O)由计数器、速率调控部件和速率检测部件电连接构成;所述的计数器是两个以级联方式互联的8位同步计数器电路;所述的速率调控部件由多路选择逻辑电路构成; 所述的8位同步计数电路以系统时钟作为工作的激励信号,速率调控部件根据系统对速率的设定,选取分频链路;同时,速率检测部件对四路载荷数据信号速率和实际选用的信道时钟速率进行监测,并为系统提供遥测信息。 The spatial channel coding payload control system according to claim 1, wherein said rate regulation means O) by the counter, and the speed regulation rate detecting means constituting means electrically connected; said two counter 8 in cascade interconnected synchronous counter circuit; said rate regulation member selected by the multiplexer logic circuit; synchronizing the counting circuit 8 as an excitation signal to the system operating clock rate as the system speed regulation member setting, select the frequency division link; the same time, four signal payload data rate and the actual selection of the channel clock rate detecting means for monitoring a rate, and to provide information to the telemetry system.
  3. 3.根据权利要求1所述的空间有效载荷信道编码控制系统,其特征在于,所述的数据调度单元(3)由两个8位数据锁存电路与数据调度部件3-3电连接构成;由此控制各通路载荷数据流的通量以及相互之间的比例关系。 According to claim 1, wherein said spatial channel coding payload control system, wherein said data scheduling unit (3) consists of two 8-bit data latch electrical circuit connected to the data scheduling unit configured 3-3; thereby controlling the proportional relationship between the flux path payload data streams and to each other.
  4. 4.根据权利要求1所述的空间有效载荷信道编码控制系统,其特征在于,所述的纠错编码交错单元由两组数据交错部件、五组8位数据锁存电路和五组信道编码电路电连接构成;其中,数据交错部件是两组结构和功能对等、同步运行的数据交错波盘电路,按照系统预先设定的交错深度,选定五组8位数据锁存电路及其对应信道编码电路的配置。 The spatial channel coding payload control system according to claim 1, wherein said error correction encoding means interleave units, five groups of 8-bit data latch circuits, and five sets of channel coding interleaving circuit consists of two sets of data electrical connection configuration; wherein the two members are interleaved data structure and function and the like, data interleaving odds synchronous operation circuit, in accordance with a predetermined interleaving depth system, the selected set of five data latch circuit 8 and the corresponding channel encoding circuit configuration.
  5. 5.根据权利要求4所述的空间有效载荷信道编码控制系统,其特征在于,所述的信道编码电路选用符合国际空间数据系统咨询委员会标准的瑞德-所罗门(255,22;3)编码方式。 5. Space Reid payload channel coding control system according to claim 4, wherein the channel coding circuit used standard Advisory Committee on International Space Data Systems - Solomon (255,22; 3) encoding .
  6. 6.根据权利要求5所述的空间有效载荷信道编码控制系统,其特征在于,所述的数据转换单元(5)中包含了数组数据串/并转换电路和对应的数据缓冲电路。 6. The space 5 of the payload channel coding control system as claimed in claim, wherein said data converting unit includes an array of data strings (5) in / parallel converting circuit and a corresponding data buffer circuit.
  7. 7.根据权利要求1所述的空间有效载荷信道编码控制系统,其特征在于,所述的数据聚合单元(6)由数据聚合电路、伪随机化电路、数据帧同步电路和8位并/串转换电路电连接构成。 The spatial channel coding payload control system according to claim 1, wherein said data polymerized units (6) by the data circuit polymerization, the pseudo-randomization circuit, a data frame synchronization circuit 8 and a parallel / serial conversion circuit is electrically connected configuration.
  8. 8.根据权利要求1所述的空间有效载荷信道编码控制系统,其特征在于,所述的速率调控单元O)、数据调度单元(3)、纠错编码交错单元G)、数据转换单元(¾和数据聚合单元(6)集成在同一片可编程逻辑阵列FPGA器件中,用VHDL语言描述方式实现。 The spatial channel coding payload control system according to claim 1, characterized in that said regulation means O rate), the data scheduling unit (3), error correction encoding interleave unit G), a data conversion unit (¾ data and polymerized units (6) integrated in a programmable logic array (FPGA) device, implemented in the way described in VHDL.
  9. 9.根据权利要求1所述的空间有效载荷信道编码控制系统,其特征在于,所述的系统时钟至百兆赫兹,纠错编码的交错深度达到5级,接收的载荷数据通路根据所用的FPGA资源进行扩。 9. The spatial channel coding payload control system of claim 1, wherein said system clock to hundreds of megahertz, error correction encoding interleaving depth of five, received payload data path depending upon the FPGA resources for expansion.
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