CN102073008B

CN102073008B - On-chip clock uncertainty measurement circuit device and system

Info

Publication number: CN102073008B
Application number: CN 201010534782
Authority: CN
Inventors: 于航; 杨旭
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2010-11-08
Filing date: 2010-11-08
Publication date: 2013-05-01
Anticipated expiration: 2030-11-08
Also published as: CN102073008A

Abstract

The invention provides an on-chip clock uncertainty measurement circuit device. The device comprises a delay circuit and a detection unit, wherein the delay circuit comprises a rough adjustment circuit and a fine adjustment circuit; two paths of clock signals A and B to be measured from two different measurement points of the same time source on a chip are roughly adjusted and delayed by the rough adjustment circuit; the roughly adjusted clock signals A and B are finely adjusted and delayed by the fine adjustment circuit; the phases of the finely adjusted clock signals A and B are detected by the detection unit; and the clock skew of the clock signals A and B is calculated when the phases of the finely adjusted clock signals A and B are the same. The invention also provides a measurement system which comprises the measurement circuit device and a ruler circuit. In the invention, on-chip measurement is performed on the clock skew and even clock jitter by using a composite non-linear delay line, so the measurement accuracy is high and the required data quantity is small.

Description

The metering circuit Apparatus and system of clock uncertainty on the sheet

Technical field

The present invention relates to the field of measuring technique of chip clock uncertainty, particularly relate to metering circuit Apparatus and system on a kind of sheet that can measure clock jitter even clock jitter of microprocessor.

Background technology

Computing machine many times needs to use clock now, for example, guarantees that many operations are according to correctly occurring in sequence or occuring synchronously.Therefore, approaching synchronously work of clock self is very important.Typically, two clocks are not ideal synchronisation usually, and have timing difference between the clock.In addition, timing difference changed along with the time between two clocks.This variation of clock timing difference is called as clock skew or clock jitter (clock skew).Many computing machines regularly agreement need to be such as the information of the time deviation between two clocks.

Uncertainty (the On-Chip Clock Uncertainty Measurement) system of measuring clock on the sheet is suitable for processing a large amount of data, and this design for Measurability more is applicable to testability chip and large-scale production simultaneously.

As shown in Figure 1, the existing upper uncertain system of measuring clock includes (the International Business Machines Corporation by International Business Machine Corporation (IBM), IBM Corporation) time-based digital quantizer (Time-to-Digital Conver ter, TDC) the SKITTER circuit of principle design, it is the present widely used upper uncertain system of measuring clock.

This SKITTER circuit comprises the lag line (DelayLine, DL) that two phase inverters by identical low fan-out load (INV) form, and this lag line long enough is to guarantee still can hold the clock delay at least one cycle when frequency of operation is minimum; Then utilize relative clock to pass through D type flip-flop (D type flip-flop, DFF) to delay line samples, sampled result is sent into scan chain (Scan Chain), obtains scanning result as shown in Figure 2, in order to follow-up data analysis and operation.

This SKITTER circuit is analyzed for independent one group of clock data, the data accumulative total in several cycles of carrying out, if the situation that length changes appears in the clock period, then explanation has detected the clock jitter in the circuit (jitter), and its size can calculate by the delay of phase inverter (INV) and the progression of beating.Analyze simultaneously for two groups of clock datas, if the same period of two clocks illustrates there is clock jitter (skew) between them that along there being phase differential its size also can calculate by the delay of phase inverter (INV) and the progression that differs.

SKITTER circuit one has 128 grades of phase inverters (INV) in the design of IBM, and every grade delay is 5-8 psec (picosecond, PS), and this also is the measuring accuracy of this circuit.This shows that the measuring accuracy of this circuit can be subject to the restriction of technique.

A kind of new circuit structure has been proposed: vernier lag line (Vernier Delay Line in order to improve measuring accuracy, VDL), as shown in Figure 3, the phase inverter (INV) that forms two lag lines postpones different, if difference is τ, to another clock signal sampling, each time sampling all can have a size to equal the poor accumulation of fine delay of τ, is similar to the principle of vernier caliper by a lag line for clock signal so.If the clock jitter between two clock signals (skew) is Tskew, the length of lag line should be at least Tskew/ τ so, finds out that thus this circuit scale is excessive.In addition because technique, voltage and temperature deviation (Process, Voltage and Temperature Variation, the impact of factor such as PVT), there is certain aberrations in property between the discrete phase inverter (INV), can make measuring accuracy have the error of PS magnitude, so this circuit is difficult to play desirable effect in actual applications.

Also there is the people once to propose the method for over-sampling (Sub-Sampling), namely with the low-frequency sampling signal clock signal to be measured sampled, calculate clock jitter (skew) according to Principle of Statistics.But this method need to need to introduce the clock of another one frequency simultaneously to the storing and calculating of mass data, and there is very large difficulty in practice in this, does not therefore also have at present large-scale industrial application.

The analysis found that existing these technology have mainly adopted the delayed mode of single linear to regulate clock, the subject matter that faces is exactly that measurement range and measuring accuracy are less, and required data volume to be processed and needed circuit scale are all also larger simultaneously.And long lag line also can be introduced larger noise.And the circuit for resemble SKITTER too relies on technique, needs to adopt specific technique can realize its measuring accuracy, does not have universality.

Summary of the invention

The object of the present invention is to provide metering circuit device and the system of a kind of upper clock uncertainty, it adopts a kind of composite non-linear lag line to come clock jitter even clock jitter are carried out measuring on the sheet, and measuring accuracy is high, and the desired data amount is little.

For realizing the metering circuit device of a kind of upper clock uncertainty that the object of the invention provides, it is characterized in that: comprise delay circuit and detecting unit; Described delay circuit comprises coarse adjustment circuit and fine tuning circuit; Two-way clock signal A to be measured and clock signal B from two different measuring points of same time source on the sheet; Described delay circuit postpones clock signal A and clock signal B:

After through described coarse adjustment circuit clock signal A and clock signal B coarse adjustment being postponed, clock signal A and the clock signal B of described fine tuning circuit after to coarse adjustment carries out fine tuning and postpones; Detecting unit detects the phase place of the clock signal A after fine tuning and clock signal B;

When the clock signal A after fine tuning is identical with clock signal B phase place, according to coarse adjustment delay and the fine tuning delay of the clock signal A after the fine tuning and clock signal B, calculate the clock jitter of clock signal A and clock signal B.

Above technical scheme can also further be improved in the following manner.

Described coarse adjustment circuit is the coarse adjustment unit, and described fine tuning circuit is 2n+1 differential delay unit in parallel, and wherein, n is natural number; After through described coarse adjustment unit clock signal A and clock signal B coarse adjustment being postponed, the clock signal A after the coarse adjustment and clock signal B are divided into 2n+1 road signal in parallel separately; Then, respectively described 2n+1 road signal in parallel is carried out fine tuning in a pair of 2n+1 of being input to differential delay unit in parallel in twos; The differential delay unit of described 2n+1 parallel connection is n: n-1 to the poor ratio of delay of the two-way clock signal formation of process: ...: 0: ... :-(n-1) :-n.

Described differential delay unit comprises the first fine tuning unit and the second fine tuning unit; Clock signal A after the coarse adjustment and clock signal B carry out fine tuning by the first fine tuning unit and the second fine tuning unit respectively; The first fine tuning unit in 2n+1 differential delay unit and the second fine tuning unit are respectively n to the delay ratio that two paths of signals forms respectively: 0; (n-1): 0; ...; 0: 0; ... 0: (n-1); 0: n.

For realizing the measuring system of a kind of upper clock uncertainty that the object of the invention provides, it is characterized in that: the metering circuit device and the scale circuit that comprise clock uncertainty on the sheet; The metering circuit device of described upper clock uncertainty comprises delay circuit and detecting unit; Described delay circuit comprises coarse adjustment circuit and fine tuning circuit; Two-way clock signal A to be measured and clock signal B from two different measuring points of same time source on the sheet; Described delay circuit postpones clock signal A and clock signal B:

After through described coarse adjustment unit clock signal A and clock signal B coarse adjustment being postponed, the clock signal A after the coarse adjustment and clock signal B are divided into 2n+1 road signal in parallel separately; Then, respectively described 2n+1 road signal in parallel is carried out fine tuning in a pair of 2n+1 of being input to differential delay unit in parallel in twos; The differential delay unit of described 2n+1 parallel connection is n: n-1:... to the poor ratio of delay of the two-way clock signal formation of process: 0: ... :-(n-1) :-n; Detecting unit detects the phase place of the clock signal A after fine tuning and clock signal B;

When the clock signal A after fine tuning is identical with clock signal B phase place, according to coarse adjustment delay and the fine tuning delay of the clock signal A after the fine tuning and clock signal B, calculate the clock jitter of clock signal A and clock signal B;

Described scale circuit comprises delay cell ring oscillator and differential delay unit ring oscillator; Described delay cell ring oscillator is used for measuring the actual size of the metering circuit device coarse adjustment precision of clock uncertainty on the sheet, and described differential delay unit ring oscillator is used for measuring the described upward actual size of the metering circuit device fine tuning precision of clock uncertainty.

Beneficial effect of the present invention: the metering circuit Apparatus and system of a kind of upper clock uncertainty of the present invention, it is few to have the control data, and measurement range is large, and the measuring accuracy high can reduce the area of side circuit in addition to a certain extent.

Description of drawings

Fig. 1 is the SKITTER circuit diagram of time-based digital quantizer principle design of the prior art;

Fig. 2 is the sampling synoptic diagram of circuit shown in Figure 1;

Fig. 3 is vernier delay line synoptic diagram of the prior art;

Fig. 4 is the circuit diagram of the metering circuit device of of the present invention upper clock uncertainty;

Wherein,

The metering circuit of 1 clock jitter and clock jitter:

111 first MUX, 112 second MUX;

121 first coarse adjustment unit input buffers, 122 second coarse adjustment unit input buffers;

131 first coarse adjustment unit, 132 second coarse adjustment unit;

141 first fine tuning input buffers, 142 second fine tuning input buffers;

15 differential delay unit;

Fig. 5 is the circuit diagram of the first coarse adjustment unit shown in Figure 4;

Fig. 6 is the circuit diagram of realizing the differential delay unit that many groups are in parallel by increasing load capacitance shown in Figure 4;

Fig. 7 is the circuit diagram of scale circuit of the present invention;

Fig. 8 is the circuit diagram of the alternative controller of Sheffer stroke gate of the present invention (NAND);

Fig. 9 is the synoptic diagram of the mutual symmetry structure of Sheffer stroke gate of the present invention (NAND);

Figure 10 is the synoptic diagram that has adopted the inverter structure of Metal-oxide-semicondutor field effect transistor (metal-oxide-semiconductor) load of the present invention;

Figure 11 is the circuit diagram of phase detector of the present invention.

Embodiment

In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the of the present invention upper uncertain metering circuit Apparatus and system of clock is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.

The metering circuit Apparatus and system of clock uncertainty on the sheet of the embodiment of the invention has utilized the principle of delay phase-locked loop (Delay-Locked Loop).The measuring system of clock uncertainty on the sheet of the embodiment of the invention comprises two parts: the metering circuit device 1 of clock uncertainty on a slice (Skew and Jitter Measurement, SJM); With a scale circuit (Ring).

Wherein, the metering circuit device of clock uncertainty on the sheet is for clock jitter (skew) and the clock jitter (jitter) of measuring clock on the sheet; Comprise delay circuit (comprising coarse adjustment circuit and fine tuning circuit), detecting unit and sampling unit.The coarse adjustment circuit is the even-multiple (precision that is the coarse adjustment circuit is the delay D of basic delay cell (DC)) of the delay D of basic delay cell (DC) to the delay of clock signal, and the fine tuning circuit is to the delay of the clock signal delay D (being that the precision of fine tuning circuit is less than the delay D of basic delay cell (DC)) less than basic delay cell (DC).

The metering circuit device of a kind of upper clock uncertainty is characterized in that:

Comprise delay circuit and detecting unit; Described delay circuit comprises coarse adjustment circuit and fine tuning circuit; Two-way clock signal A to be measured and clock signal B from two different measuring points of same time source on the sheet; Described delay circuit postpones clock signal A and clock signal B:

Each described differential delay unit comprises the first fine tuning unit and the second fine tuning unit; Clock signal A after the coarse adjustment and clock signal B carry out fine tuning by the first fine tuning unit and the second fine tuning unit respectively; The first fine tuning unit in 2n+1 differential delay unit and the second fine tuning unit are respectively n to the delay ratio that two paths of signals forms respectively: 0; (n-1): 0; ...; 0: 0; ... 0: (n-1); 0: n.

Described detecting unit is 2n+1 phase detector, and a described 2n+1 phase detector is connected with 2n+1 differential delay unit respectively; Described phase detector after to fine tuning clock signal A and clock signal B relatively phase place successively,

output

0 or 1.

(can only judge fine tuning after appear in 0 and 1 boundary process identical with clock signal B phase place of clock signal A) appears 0 when 1 has a common boundary in the output of described phase detector, and the clock jitter of clock signal A and clock signal B (can only be similar to and get) adds that to the difference of the delay of two-way clock signal two differential delay unit that output 0 and 1 has a common boundary are to the mean value of the difference of the delay of two-way clock signal for the coarse adjustment unit.

The scale circuit comprises two ring oscillators (Ring Oscillator): delay cell ring oscillator (Ring_DC) and differential delay unit ring oscillator (Ring_SDC).Delay cell ring oscillator (Ring_DC) is for the actual delay D reality of measuring basic delay cell (DC), the i.e. actual size of the metering circuit device coarse adjustment precision of clock uncertainty on the sheet; Differential delay unit ring oscillator (Ring_SDC), the effective unit that is used for measurement differential delay unit (SDC) postpones poor d in fact, i.e. the actual size of the metering circuit device fine tuning precision of clock uncertainty on the sheet.

Preferably, (the Skew and Jitter Measurement of the metering circuit device 1 of clock uncertainty on the sheet, SJM), as shown in Figure 4, comprise coarse adjustment unit 13 (being the coarse adjustment circuit), the differential delay unit 15 of 9 groups of parallel connections (being the fine tuning circuit), 9 phase detectors (PD) (being detecting unit), 9 D type flip-flop (DFF) (being sampling unit) that link to each other with phase detector;

Two-way clock signal (clock signal A and clock signal B) from two different measuring points of same time source on the sheet, the clock signal of coarse adjustment is input to phase detector (PD) and D type flip-flop, and (clock signal of coarse adjustment is used for controlling the phase demodulation process of phase detector and the sampling of trigger, belong to prior art, no further details to be given herein); Clock signal after the fine tuning is input to phase detector (PD) carries out phase demodulation, D type flip-flop (DFF) is taken a sample to identified result; Clock signal A after the output display of D type flip-flop (DFF) is delayed and clock signal B phase-locking are when (0 and 1 boundary appears in the output that is the D type flip-flop), according to the output of D type flip-flop (DFF), calculate the time deviation of two clock signals (clock signal A and clock signal B) of same time source.

Wherein, as shown in Figure 4, coarse adjustment unit 13 comprises the first coarse adjustment unit 131 and the second coarse adjustment unit 132, and clock signal A and clock signal B carry out coarse adjustment by the first coarse adjustment unit 131 and the second coarse adjustment unit 132 respectively.The first coarse adjustment unit 131 and the second coarse adjustment unit 132 all adopt 4 bit digital pilot delay lines (DCDL-4), 4 bit digital pilot delay lines adopt the scale-of-two control structure, and its advantage is can be less with less control signal step size but delay that scope is larger.

As shown in Figure 5,4 bit digital pilot delay lines of the first coarse adjustment unit 131 are composed in series with binary form by 4 groups of delay cells.

Described 4 groups of delay cells are respectively 16 grades of delay cells (DC * 16), 8 grades of delay cells (DC * 8), 4 grades of delay cells (DC * 4) and 2 grades of delay cells (DC * 2); 16 grades of delay cells (DC * 16) comprise the basic delay cell of 16 series connection, and other grades delay cell in like manner.Link to each other with alternative controller (MUX2) after every group of delay cell and the transmission line parallel connection, digital controlled signal (the CA16 of 4 groups of delay cells, CA8, CA4, CA2) be input to respectively corresponding alternative controller (MUX2), by digital controlled signal control respective sets delay cell.Digital controlled signal is provided by scan chain.Adopting scan chain control figure control lag is prior art, and non-the present invention's emphasis only uses as a kind of instrument herein, will not describe in detail herein.

During control: CA16=1, the delay that expression is produced by 16 grades of delay cells counts the delay of DCDL_4; CA16=0, the delay that expression is produced by 16 grades of delay cells is not counted in the delay of DCDL_4.In like manner, 8 grades of delay cells of CA8 control; CA4 controls 4 grades of delay cells; CA2 controls 2 grades of delay cells.If the delay of 1 grade of basic delay cell (DC) be D (in the present embodiment, the unit of the delay of 1 grade of basic delay cell is psec, wherein 1,000,000,000,000 psec=1 second), the combination of these 4 groups of delay cells arbitrary integer that DCDL_4 is formed between the 0-15 of 2D doubly postpones so.

As shown in Figure 4, differential delay unit (Subtracted Delay Cell, SDC) 15 realized by parallel form.Adopt parallel-connection structure not need the differential delay unit is controlled on the one hand, reduced control bit, control difficulty and Measuring Time; Can realize less delay on the other hand, increase measuring accuracy.

Preferably, the clock signal A after coarse adjustment is divided into odd number road S=2n+1 (A1, A2, A3 ...; N=1,2,3 ...), through the clock signal B of coarse adjustment be divided into odd number road S=2n+1 (B1, B2, B3 ...; N=1,2,3 ...).Then in twos (A1 and B1, A2 and B2, A 3 and B3 ...) be input to odd number group (S=2n+1, n=1,2,3......) differential delay unit in parallel carries out fine tuning; Through odd number group (S=2n+1, n=1,2, after 3......) differential delay unit fine tuning in parallel postponed, the differential delay unit of described 2n+1 parallel connection was n: n-1 to the poor ratio of delay of the two-way clock signal formation of process: ...: 0: ... :-(n-1) :-n.In the present embodiment, S=2n+1=9, i.e. n=4.Preferably, in order to realize precision less than the delay D (i.e. the delay of a door) of 1 grade of basic delay cell (DC), the present invention realizes the differential delay unit by the mode that increases load capacitance.

Preferably, as shown in Figure 4, S=2n+1=9, i.e. n=4.After the fine tuning of the differential delay unit of 9 groups of parallel connections postponed, the differential delay unit of described 9 groups of parallel connections was 4: 3: 2 to the poor ratio of delay of the two-way clock signal formation of process: 1: 0 :-1 :-2 :-3 :-4.

The first fine tuning unit in 2n+1 differential delay unit and the second fine tuning unit were respectively 4: 0 the delay ratio that two paths of signals forms respectively; 3: 0; 2: 0; 1: 0; 0: 0; 0 :-1; 0 :-2; 0 :-3; 0 :-4.

As shown in Figure 6, SDC_4, SDC_3, SDC_2, SDC_1 and SDC_R have increased by 4 at front two-stage DC output terminal respectively, 3,2,1 and 0 grade of Metal-oxide-semicondutor field effect transistor (metal-oxide-semiconductor) load, because shunt capacitance is linear increasing, in Fig. 49 kinds make up (SDC_4 so, SDC_R), (SDC_3, SDC_R), (SDC_2, SDC_R), (SDC_1, SDC_R), (SDC_R, SDC_R), (SDC_R, SDC_1), (SDC_R, SDC_2), (SDC_R, SDC_3) reach (SDC_R, SDC_4), the differential delay unit of 9 groups of parallel connections of clock signal A and clock signal B is 4: 3: 2 to the poor ratio of delay of the two-way clock signal formation of process after fine tuning: 1: 0 :-1 :-2 :-3 :-4.The poor d of the unit delay of this differential delay unit is determined by the load capacitance size, can realize one group of accurate little delay cell.The delay difference that the two-way clock signal of process is formed that is 9 groups of differential delay unit shown in Figure 4 Wei 4d, 3d, 2d, 1d, 0,-1d,-2d ,-3d ,-4d, after the fine tuning of the differential delay unit of 9 groups of parallel connections postponed, the differential delay unit of described 9 groups of parallel connections was 4: 3: 2 to the poor ratio of delay of the two-way clock signal formation of process: 1: 0 :-1 :-2 :-3 :-4.

More preferably, Metal-oxide-semicondutor field effect transistor (metal-oxide-semiconductor) size among the present invention is identical with the Metal-oxide-semicondutor field effect transistor (metal-oxide-semiconductor) among the DC, so also can avoid the too great deviations that causes because of technique.Determining of the single number of tuples of differential delay in parallel can postpone D by the emulation of basic delay cell (DC) _EmulationThe poor d of emulation unit delay with the differential delay unit of parallel connection _EmulationObtain, the group of differential delay unit in parallel is counted S (being 2n+1), then needs to satisfy the requirement of formula (1):

There is not the measurement dead angle in the guarantee circuit like this, if this condition can not satisfy, possibly can't observe so 0 and 1 shown in the table 1 (the Output rusults algorithm table of comparisons of metering circuit SJM) and have a common boundary, and just can't read concrete measured value yet.But S is also unsuitable excessive, otherwise can waste resource, adopts following formula to calculate in the embodiment of the invention and determines that the group of the differential delay unit of final parallel connection counts S:

Wherein,

It is the implication that rounds up.

In the time of the number of calculating group herein, be to calculate D according to the parameter that technique provides _EmulationAnd d _EmulationObtaining by emulation, is not actual numerical value, when actual design, also needs to increase certain design remaining.

Owing to increased capacitive load, unavoidably can change the flip-flop transition (transition) of clock, in order to reduce impact, preferably, adopt the complementary load capacitance of NP among the present invention, wherein, NP represents N-type metal-oxide-semiconductor and P type metal-oxide-semiconductor, and N, P have represented the feature structure of metal-oxide-semiconductor; Can guarantee that like this rising edge with negative edge flip-flop transition (transition) identical variation occured when clock signal was passed through, again through the shaping of back two-stage DC, the clock signal flip-flop transition (transition) of final output and input clock signal basic identical (rise time or the fall time of two clocks are basic identical, can guarantee higher measuring accuracy like this).

The clock signal of coarse adjustment is input to phase detector (PD) and D type flip-flop (clock signal of coarse adjustment is used for controlling the phase demodulation process of phase detector and the sampling of trigger, belongs to prior art, and no further details to be given herein); Clock signal after the fine tuning is input to phase detector (PD) carries out phase demodulation, through behind the phase demodulation, (output that makes phase detector can only be 0 or 1 to be prior art in identified

result output

0 or 1, non-the present invention's emphasis, only use as a kind of instrument herein, will not describe in detail herein), D type flip-flop (DFF) is taken a sample to identified result; Clock signal A after the output display of D type flip-flop (DFF) is delayed and clock signal B phase-locking are when (0 and 1 boundary appears in the output that is the D type flip-flop), according to the output of D type flip-flop (DFF), calculate the time deviation of two clock signals (clock signal A and clock signal B) of same time source.

The mode of operation of the metering circuit device of clock uncertainty is controlled by mode of operation control signal (OC represents in Fig. 4) on the sheet.When OC=1, be in sampling and surveying work pattern, this moment, data continued to beat, and can not read;

When OC=0, be in the output services pattern, this moment can reading out data.

The use of the metering circuit device 1 of clock uncertainty on the sheet, basic process is roughly as follows: the switch that utilizes the two-way clock signal control circuit, need to select the two-way clock signal of measurement, then regulate the digital controlled signal that scan chain arranges the coarse adjustment unit, observe afterwards measurement result (outputs of 9 D type flip-flop):

The output of 9 D type flip-flop occurs 0 and 1 and has a common boundary, and according to the output of D type flip-flop (DFF), calculates the time deviation of two clock signals (clock signal A and clock signal B) of same time source.

The output of 9 D type flip-flop does not occur 0 and 1 and has a common boundary, and needs to regulate the digital controlled signal that scan chain arranges the coarse adjustment unit, realizes remeasuring.The according to the observation output of 9 D type flip-flop, key joint scan chain arranges the digital controlled signal of coarse adjustment unit repeatedly, finally obtains comprising the output of 0 and 19 D type flip-flop of having a common boundary.

In the present embodiment, output according to D type flip-flop (DFF), the method of time deviation of two clock signals that calculates same time source is as follows: have 3 groups of 27 output signals (3 groups is continuous 3 cycles of representative) after corresponding D type flip-flop (DFF) is taken a sample, represent respectively the clock signal to be measured measurement in continuous three cycles.

Three groups of signals are relatively independent, and appearance form and measured value thereof that every group of output signal is possible are as shown in the table.

The Output rusults algorithm table of comparisons (table 1) of metering circuit SJM

Q4VX～Q4NVX	Skew (CKA-CKB) (X=1,2 or 3, error is 0.5d)
		000000000	After delayed, CKB is prior to CKA, and skew is excessive, can't reading, need resurvey
000000001	(NA-NB)×D-3.5×d
		000000011	(NA-NB)×D-2.5×d
000000111	(NA-NB)×D-1.5×d
		000001111	(NA-NB)×D-0.5×d
000011111	(NA-NB)×D+0.5×d
		000111111	(NA-NB)×D+1.5×d
001111111	(NA-NB)×D+2.5×d
		011111111	(NA-NB)×D+3.5×d
111111111	After delayed, CKA is prior to CKB, and skew is excessive, can't reading, need resurvey

If after delayed, clock signal A is during prior to clock signal B, and the identified result of phase detector is 0, and then the output of D type flip-flop (DFF) is 0; Then work as clock signal B prior to clock signal A, the identified result of phase detector is 1, and then the output of D type flip-flop (DFF) then is 1.Have a

common boundary

0 and 1 in the output of D type flip-flop (DFF) (namely 0 and 1 Transforms between time), two clock signal phases are synchronous.Therefore,

The output of described D type flip-flop (DFF) (output be the identified result of phase detector) occurs 0 and 1 when having a common boundary, and to be the coarse adjustment unit add that to the difference of the delay of two-way clock signal two differential delay unit that

output

0 and 1 has a common boundary are to the mean value of the difference of the delay of two-way clock signal to the clock jitter of clock signal A and clock signal B.

Shown in as above showing,

When Q4VX-Q4NVX is output as 000000001, namely

Q4VX is output as 0, Q3VX and is output as 0, Q2VX and is output as 0, Q1VX and is output as 0,

Q0VX is output as 0,

Q1NVX is output as 0, Q2NVX and is output as 0, Q3NVX and is output as 0, Q4NVX and is output as 1.

Q3NVX is output as at 0 o'clock, and the difference of the delay of clock signal A and clock signal B is on this path: (NA-NB) * and D-3 * d;

Q4NVX is output as at 1 o'clock, and the difference of the delay of clock signal A and clock signal B is on this path: (NA-NB) * and D-4 * d;

Time deviation between actual clock signal A and the clock signal B is:

(NA-NB)×D+(-3×d-4×d)/2＝(NA-NB)×D-3.5×d

Namely work as Q4VX-Q4NVX and be output as 000000001, the time deviation (NA-NB) between clock signal A and the clock signal B * D-3.5 * d.

When the output of Q4VX-Q4NVX does not occur 0 and 1 when having a common boundary, namely delayed after, clock signal A the identical situation of phase place do not occur with clock signal B.When boundary between 0 and 1 does not appear in the output of Q4VX-Q4NVX, need to regulate the digital controlled signal that scan chain arranges the coarse adjustment unit, realize remeasuring.The digital controlled signal that scan chain arranges the coarse adjustment unit is regulated in the according to the observation output of 9 D type flip-flop repeatedly, finally obtains comprising the output of 0 and 19 D type flip-flop of having a common boundary.Adopting scan chain control figure pilot delay line is prior art, and non-the present invention's emphasis only uses as a kind of instrument herein, will not describe in detail herein.

When Q4VX-Q4NVX is output as other situations, in like manner, can calculate the time deviation between clock signal A and the clock signal B.

Otherwise also set up.

Wherein, NA, NB are respectively the quantity of DC among two DCDL_4 of A, B, are expressed as:

N _A＝CA16×16+CA8×8+CA4×4+CA2×2

N _B＝CB16×16+CB8×8+CB4×4+CB2×2

N _AThe quantity that 4 bit digital pilot delay lines of the first coarse adjustment unit 131 count the delay of DCDL_4; N _BThe quantity that 4 bit digital pilot delay lines of the second coarse adjustment unit 132 count the delay of DCDL_4;

The digital controlled signal of 4 bit digital pilot delay lines of the first coarse adjustment unit 131 and the second coarse adjustment unit 132 is provided by scan chain, can obtain digital controlled signal (CA16, CA8 according to scan chain, CA4, CA2 and CB16, CB8, CB4, CB2) value, thereby calculate N _AAnd N _BValue.

D is the delay of basic delay cell (DC), d is that the unit delay of differential delay unit is poor (in the present embodiment, the poor unit of the unit delay of differential delay unit is femtosecond, wherein 0.001 psec=1 femtosecond), they represent respectively the precision of SJM circuit coarse adjustment and the precision of fine tuning.The actual delay D of the basic delay cell (DC) of scale circuit measuring is real, be updated in the above-mentioned formula with the poor d of effective unit delay of differential delay unit (SDC) real (concrete measuring method is described in detail hereinafter), can draw the time deviation between clock signal A and the clock signal B.

Described phase detector carries out the phase bit comparison to continuous three cycles of two-way clock signal respectively, three groups of output signals of 2n+1 D type flip-flop (DFF) output (output be the identified result of phase detector), the figure place that changes according to 0 and 1 adjacent position of three groups of output signals, if the maximum figure place of beating is M (according to the maximum number of digits of

output

0 and 1 variation of having a common boundary of D type flip-flop (DFF)), calculate the clock jitter t of two clock signals to be measured _JitterFor: t _Jitter=M * d,

Wherein, d is that the unit delay of differential delay unit of described parallel connection is poor.

Wherein, M is by obtaining with the Output rusults of observing different cycles D type flip-flop.In this example, M both had been the Output rusults in continuous three cycles figure place of beating.The effective unit of the differential delay unit (SDC) of scale circuit measuring is postponed poor d real (concrete measuring method is described in detail hereinafter) be updated in the above-mentioned formula, can draw the time jitter (jitter) between clock signal A and the clock signal B.

Since when circuit is worked under different voltages, temperature conditions, the actual delay D of basic delay cell (DC) _RealPostpone poor d with the effective unit of differential delay unit (SDC) _RealBe different, therefore need to measure actual D _RealAnd d _Real

Consider that measuring clock on the sheet may cause resultant error larger because of noise complete cycle, therefore adopt two ring oscillator Ring-DC and Ring-SDC to measure respectively metering circuit device (SJM) coarse adjustment of clock uncertainty on the sheet and the actual size of fine tuning precision among the present invention, namely the actual delay D of basic delay cell (DC) _RealPostpone poor d with the effective unit of differential delay unit (SDC) _RealThe circuit structure of ring oscillator as shown in Figure 7.

Here the pin that needs the multiplexing microprocessor chip of Ring is externally exported waveform, recycles its cycle of outside oscilloscope measurement.Adopt this form, output signal will be through one section printed circuit board (Printed Circuit Board, PCB) cabling, therefore output signal frequency can not excessive (100MHz be higher with interior accuracy), so Ring adopts the form of 161 grades of series connection among the present invention, and output waveform carried out 16 frequency divisions, final output signal.

In order to reduce the deviation of device as far as possible; well simulate basic delay cell (DC) and differential delay unit (SDC); do not adopt the denoising protection among two ring oscillator Ring-DC and the Ring-SDC, but add between the VDD-to-VSS electric capacity (DECAP) to weaken the impact of power supply noise.

If the cycle of the delay cell ring oscillator Ring_DC that measures is T _DC, the cycle of differential delay unit ring oscillator Ring_SDC is T _SDC, the progression of two ring oscillators is N, passes through simultaneously P frequency division (embodiment of the invention is 16 frequency divisions), can try to achieve so actual delay and be:

Preferably, in the embodiment of the invention, N=161, P=16.

Preferably, in the time of on the sheet on the time-card measuring system also comprise the first MUX 111 and the second MUX 112, the first coarse adjustment unit input buffer 121 and the second coarse adjustment unit input buffer 122, the first fine tuning input buffers 141 and the second fine tuning input buffer 142.

Behind the active circuit, the two-way clock signal of same time source (using respectively clock signal A and clock signal B), three signals of every group of clock signal input to be measured, use respectively CK1A, CK2A, CK3A, CK1B, CK2B, CK3B represent) at first respectively through the first MUX 111 and the second MUX 112, need to select the signal of measurement, and signal is carried out pre-shaping; Then respectively through the first coarse adjustment unit input buffer 121 and the second coarse adjustment unit input buffer 122, signal is carried out shaping; Signal sequence after the shaping carries out coarse adjustment through the first coarse adjustment unit 131 and the second coarse adjustment unit 132 to the phase place of two groups of clock signals;

142 pairs of clock signals through coarse adjustment of the first fine tuning input buffer 141 and the second fine tuning input buffer are carried out again shaping; Clock signal warp through again shaping is too much organized differential delay unit 15 in parallel, carries out fine tuning.

Preferably, alternative controller (MUX2) adopts the alternative controller (MUX2) based on Sheffer stroke gate (NAND), as shown in Figure 8.The benefit that adopts this structure be exactly clock signal flip-flop transition (transition) within it in section's transmission course with in DC, be consistent.MUX2 is most important in DCDL, because all DC are consistent, if the structure of MUX2 is improper, and the consistance of flip-flop transition (transition) of probably can destroying clock when propagating.

Preferably, Sheffer stroke gate (NAND) adopts the mutual symmetry structure, as shown in Figure 9.The physical property of two input ports is strict symmetrical in this structure, can guarantee so can not change because of the order of clock port the flip-flop transition (transition) of clock signal.Consider that two input ports of Sheffer stroke gate (NAND) all might become clock path, Sheffer stroke gate (NAND) does not adopt CMOS structure commonly used.

The selection of basic delay cell (DC):

Because DCDL_4 and DCDL_3 adopt scale-of-two to regulate pattern, control signal is less, so in the embodiment of the invention, preferably, uses phase inverter (INV) as basic delay cell.

As another kind of embodiment, preferably, when more such as control signal, can use Sheffer stroke gate (NAND) as basic delay cell, but Metal-oxide-semicondutor field effect transistor (metal-oxide-semiconductor) is more in the Sheffer stroke gate (NAND), can more introducing noises.

Preferably, basic delay cell (DC) has adopted phase inverter (INV) structure of band Metal-oxide-semicondutor (N-Mental-Oxide-Semiconductor, NMOS) field effect transistor load, as shown in figure 10.Namely under the NMOS of phase inverter (INV), increase the NMOS of a same size conducting.This structure has two advantages: the one, and the transport property of simulation Sheffer stroke gate (NAND) guarantees the consistance of whole DCDL; The 2nd, this structure is almost symmetry for the transport property of rising edge clock signal and negative edge.Load capacitance effect among Figure 10 has two: the one, and the capacitive load of the whole DCDL of balance; The 2nd, suitably increase the delay of single DC, to reduce the length of DCDL.Especially in the present invention, DCDL adopts binary regulative mode, and the increase of each length all is at double.

As the basic composition unit of DCDL, DC also is the key that determines DCDL length.When definite DCDL length, need to consider the delay that circuit (be quick mode (Fast Corner) 1.2V-40 ℃ for embodiment of the invention) under condition extremely fast produces, enough cover predetermined measurement range under all conditions with the DCDL length that guarantees finally to obtain.

The selection of phase detector (PD):

Because the present invention adopts phase detector to judge whether the clock signal after the delay is synchronous, so the accuracy of phase detector will have a strong impact on measurement result, also be a most complicated module of the present invention.

Preferably, phase detector of the present invention adopts the master-slave flip-flop of level Four SR latch (SR_Latch) series connection as phase detector, and as shown in figure 11, phase detector and trigger all need clock to control.Here clock signal has generated four clock signals after utilizing coarse adjustment, be respectively C1, C2, C3 and C4, wherein C1, C2, C3 are used for phase detector, and C4 is used for trigger, clock C4 and C1 before, C2, C3 homology mainly are because the sampling of trigger is wanted and the phase detector of front guarantees the regular hour relation, and be correct to guarantee output.。

The structure of level Four SR Latch series connection, spatially prolong SR Latch to exchange the phase demodulation time for, the metastable state of avoiding occurring (single SR_Latch structure, when two input signals along too near the time, SR Latch may enter metastable state), the correctness of assurance phase demodulation.This also requires gate leve device on the critical path rising edge clock signal and negative edge to be had the transport property of balance, therefore, all Sheffer stroke gates (NAND) also adopt the mutual symmetry structure among the MUX2 in the circuit, the phase inverter that adds the NMOS load (INV) structure before the phase inverter of balanced logic (INV) adopts.

The sampled signal of phase detector is the high level useful signal, so the position of the rising edge of signal and negative edge just becomes particularly important.In order to guarantee the phase demodulation time of three semiperiods, need the high level of sampled signal C1, C2, C3 to be contained within the high level of clock input signal, and maintain a certain distance, do not overlap mutually, can prevent that like this clock signal to be measured from directly passing SR Latch, avoid logic error.But can not be by in advance because signal can only be delayed, the negative edge that sampled signal C1 is the fastest must be through the delay of one-level Sheffer stroke gate (NAND) and one-level NOR, and the delay of one-level SR Latch is less than one-level Sheffer stroke gate (NAND), this negative edge that just requires to be sampled signal is served evening, two kinds of solutions are generally arranged: the one, before first order SR Latch, add impact damper (buffer), the 2nd, after SR Latch, add buffer.The present invention is that the input end from SDC draws signal as the sampled signal of PD, utilizes SDC as front buffer (buffer), can reduce circuit scale like this.

Preferably, consider applicability and portable problem, load capacitance is used metal-oxide-semiconductor electric capacity.

More preferably, the transistor size on the clock critical path is all identical, and transistorized breadth length ratio is moderate, and channel direction is identical, and metal routing is not established in the active area top;

More preferably, the grid of one dimension symmetry is adopted in arbitrary gate circuit inside of the embodiment of the invention, and increases empty grid (Dummy) at the transistor edge, to guarantee strict symmetry;

More preferably, MUX2 of the invention process and based on the phase detector (SRPD) of SR latch, the via hole of the metal level at wire place, the length of metal routing, width, direction, process all guarantees symmetrical balance as far as possible.

Measurement metering circuit device and the system of a kind of of the embodiment of the invention upper clock uncertainty, it is few to have the control data, and measurement range is large, and the measuring accuracy high can reduce the area of side circuit in addition to a certain extent.

For example after tested, SKITTER circuit of the prior art, every grade of measuring accuracy is 8ps, totally 128 grades, so finally need 256 signals, measurement range is ± 1024ps.And employing the present invention, if scale-of-two numerical control lag line one-level postpones to be 35ps, totally 5 grades, measurement range is exactly 1085ps so; The variable gradient of the differential delay line that the back is parallel is 4ps, and measuring accuracy is 4ps just so, and desired signal quantity is

Individual, 21+5*2=31 altogether of final desired signal.Like this with prior art relatively clearly:

SKITTER has realized measurement range 1024ps, measuring accuracy 8ps with 256 signals.

The present invention has realized measurement range 1085ps, measuring accuracy 4ps with 31 signals.

The metering circuit Apparatus and system of clock uncertainty on the sheet of example of the present invention, it is few to have the control data, and measurement range is large, and the measuring accuracy high can reduce the area of side circuit to a certain extent.

Should be noted that at last that obviously those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification.

Claims

1. the metering circuit device of clock uncertainty on the sheet is characterized in that:

Described coarse adjustment circuit is the coarse adjustment unit, and described fine tuning circuit is 2n+1 differential delay unit in parallel, and wherein, n is natural number;

2. the metering circuit device of according to claim 1 upper clock uncertainty is characterized in that:

After through described coarse adjustment unit clock signal A and clock signal B coarse adjustment being postponed, the clock signal A after the coarse adjustment and clock signal B are divided into 2n+1 road signal in parallel separately; Then, respectively described 2n+1 road signal in parallel is carried out fine tuning in a pair of 2n+1 of being input to differential delay unit in parallel in twos; The differential delay unit of described 2n+1 parallel connection is n: n-1 to the poor ratio of delay of the two-way clock signal formation of process: ...: 0: ... :-(n-1) :-n.

3. the metering circuit device of according to claim 2 upper clock uncertainty is characterized in that:

Described differential delay unit comprises the first fine tuning unit and the second fine tuning unit; Clock signal A after the coarse adjustment and clock signal B carry out fine tuning by the first fine tuning unit and the second fine tuning unit respectively;

The first fine tuning unit in 2n+1 differential delay unit and the second fine tuning unit are respectively n to the delay ratio that two paths of signals forms respectively: 0; (n-1): 0; ...; 0: 0; ... 0: (n-1); 0: n.

4. it is characterized in that according to claim 2 or the metering circuit devices of 3 described upper clock uncertainties:

Described detecting unit is 2n+1 phase detector, and a described 2n+1 phase detector is connected with 2n+1 differential delay unit respectively;

Described phase detector after to fine tuning clock signal A and clock signal B relatively phase place successively, output 0 or 1.

5. the metering circuit device of according to claim 4 upper clock uncertainty is characterized in that:

The output of described phase detector occurs 0 and 1 when having a common boundary, and to be the coarse adjustment unit add that to the difference of the delay of two-way clock signal two differential delay unit that output 0 and 1 has a common boundary are to the mean value of the difference of the delay of two-way clock signal to the clock jitter of clock signal A and clock signal B.

6. the metering circuit device of according to claim 2 upper clock uncertainty is characterized in that:

Described coarse adjustment unit comprises the first coarse adjustment unit and the second coarse adjustment unit; Clock signal A and clock signal B carry out coarse adjustment by the first coarse adjustment unit and the second coarse adjustment unit respectively;

Described the first coarse adjustment unit and the second coarse adjustment unit are 4 bit digital pilot delay lines, and described 4 bit digital pilot delay lines are the scale-of-two control structure.

7. the metering circuit device of according to claim 6 upper clock uncertainty is characterized in that:

Described 4 bit digital pilot delay lines comprise basic delay cell, and the emulation of described basic delay cell postpones D emulation;

The poor d emulation of the emulation unit delay of the differential delay unit of described parallel connection, the group of the differential delay unit of described parallel connection is counted S=2n+1, satisfies the requirement of following formula:

8. the metering circuit device of according to claim 6 upper clock uncertainty is characterized in that:

Described 4 bit digital pilot delay lines comprise basic delay cell, and the emulation of described basic delay cell postpones D _Emulation

The poor d of emulation unit delay of the differential delay unit of described parallel connection _Emulation, the group of the differential delay unit of described parallel connection is counted S=2n+1, satisfies the requirement of following formula:

Wherein,

It is the implication that rounds up.

9. the metering circuit device of according to claim 4 upper clock uncertainty is characterized in that:

Described phase detector carries out the phase bit comparison to continuous three cycles of two-way clock signal respectively, 2n+1 phase detector exported three groups of output signals, according to the figure place that 0 and 1 adjacent position of three groups of output signals changes, establishing the figure place that 0 and 1 maximum adjacent position changes is M; Calculate the clock jitter t of two clock signals to be measured _JitterFor: t _Jitter=M * d;

10. it is characterized in that according to claim 7 or the metering circuit devices of 8 described upper clock uncertainties:

Described basic delay cell is the phase inverter with the load of Metal-oxide-semicondutor field effect transistor.

11. the metering circuit device of according to claim 2 upper clock uncertainty is characterized in that:

The differential delay unit of described parallel connection is realized by the mode that increases load capacitance.

12. the metering circuit device of according to claim 4 upper clock uncertainty is characterized in that:

Described phase detector is the phase detector with the master-slave flip-flop of level Four S R series of latches.

13. the measuring system of clock uncertainty on the sheet is characterized in that:

The metering circuit device and the scale circuit that comprise clock uncertainty on the sheet;

The metering circuit device of described upper clock uncertainty comprises delay circuit and detecting unit; Described delay circuit comprises coarse adjustment circuit and fine tuning circuit; Two-way clock signal A to be measured and clock signal B from two different measuring points of same time source on the sheet; Described delay circuit postpones clock signal A and clock signal B:

After through described coarse adjustment unit clock signal A and clock signal B coarse adjustment being postponed, the clock signal A after the coarse adjustment and clock signal B are divided into 2n+1 road signal in parallel separately; Then, respectively described 2n+1 road signal in parallel is carried out fine tuning in a pair of 2n+1 of being input to differential delay unit in parallel in twos; The differential delay unit of described 2n+1 parallel connection is n: n-1 to the poor ratio of delay of the two-way clock signal formation of process: ...: 0: ... :-(n-1) :-n; Detecting unit detects the phase place of the clock signal A after fine tuning and clock signal B;

14. the measuring system of according to claim 13 upper clock uncertainty is characterized in that:

Described detecting unit is 2n+1 phase detector, and a described 2n+1 phase detector is connected with 2n+1 differential delay unit respectively; Described phase detector after to fine tuning clock signal A and clock signal B relatively phase place successively, output 0 or 1;

15. the measuring system of according to claim 13 upper clock uncertainty is characterized in that:

Described coarse adjustment unit comprises basic delay cell, and the actual delay of described basic delay cell is D _Real, the effective unit of described differential delay unit postpones the poor d that is _Real

N is the progression of ring oscillator, T _DCBe the cycle of delay cell ring oscillator, T _SDCBe the cycle of differential delay unit ring oscillator, P is the number of times of frequency division.