TWI637185B - Built-in self test (bist) circuit for clock jitter - Google Patents

Abstract

A built-in self-test circuit for clock jitter, comprising a clock receiving circuit, a timing circuit and a jitter determining circuit. The clock receiving circuit performs the operation (a): generating a start signal and a stop signal according to the clock signal, wherein the stop signal is behind the start signal for one or more cycles. Timing circuit performs operation (b): detects the first time difference between the start signal and the stop signal. The clock receiving circuit and the timing circuit respectively perform operations (a) and (b) a plurality of times to generate a plurality of second times. The jitter determination circuit calculates a reference value based on the second time, calculates a jitter threshold based on the reference value, obtains at least one extreme value in the second time, and calculates a jitter amount based on the extreme value. If the amount of jitter is less than the jitter threshold, the jitter judging circuit outputs a pass signal.

Description

Built-in self-test circuit for clock jitter

The present invention relates to a built-in self test (BIST) circuit, and more particularly to a built-in self-test circuit for a clock jitter.

A clock generation circuit, such as a phase lock loop (PLL) or a delay line loop (DLL), is used to generate a low jitter clock signal. Such a clock generation circuit can be applied to a wide variety of products, such as a transmitting end and a receiving end for serial transmission. However, generally, when testing a product having a clock generation circuit, the detection instrument used can only detect the frequency of the clock and cannot detect the jitter of the clock. Therefore, if a built-in self-test circuit can be set next to the clock generation circuit to detect the jitter of the clock, it will be of great help to the detection of the product.

The invention provides a built-in self-test circuit for clock jitter, which is suitable for a clock signal, which has a period. The built-in self-test circuit includes a clock receiving circuit, a timing circuit and a jitter judging circuit. Clock receiving circuit Receiving the clock signal and performing the operation (a): generating a start signal and a stop signal according to the clock signal, wherein the stop signal is behind the start signal for one or more cycles. The timing circuit receives the start signal and the stop signal, and performs operation (b): detecting the first time difference between the start signal and the stop signal. The clock receiving circuit and the timing circuit respectively perform operations (a) and (b) a plurality of times to generate a plurality of second times, the second times including the first time described above. The jitter determination circuit calculates a reference value based on the second time and calculates a jitter threshold based on the reference value. The jitter determination circuit takes at least one extreme value of the second time and calculates the amount of jitter based on the extreme value. The jitter judging circuit judges whether the jitter amount is smaller than the jitter threshold value, and if the jitter amount is smaller than the jitter threshold value, the jitter judging circuit outputs the pass signal.

In some embodiments, the reference value is an average of the second time, and the jitter determination circuit multiplies the reference value by a preset value to obtain a jitter threshold.

In some embodiments, the at least one extreme value described above includes a maximum and a minimum of the second time. The jitter judging circuit subtracts the minimum value from the maximum value to obtain the amount of jitter.

In some embodiments, the jitter determination circuit described above calculates an average of the maximum value and the minimum value to obtain a reference value, and multiplies the reference value by a preset value to obtain a jitter threshold.

In some embodiments, the preset values described above are programmable, and the preset values are one of 0.25, 0.125, 0.0625, and 0.03125.

In some embodiments, the jitter determination circuit includes a first temporary storage a device for storing a maximum value; a second register for storing a minimum value; and a calculation circuit.

In some embodiments, the clock receiving circuit described above includes first to third flip-flops. The input end of the first flip-flop is coupled to the high-level voltage, and the trigger end is coupled to the clock signal. The input end of the second flip-flop is coupled to the positive-phase output end of the first flip-flop, the trigger end is coupled to the clock signal, and the positive-phase output terminal outputs the start signal. The input end of the third flip-flop is coupled to the positive-phase output end of the second flip-flop, the trigger end is coupled to the clock signal, and the positive-phase output terminal outputs the stop signal.

In some embodiments, the timing circuit described above includes first to second oscillators. The first oscillator receives the start signal and is driven by the start signal. The second oscillator receives the stop signal and is driven by the stop signal, wherein the oscillation frequency of the second oscillator is greater than the oscillation frequency of the first oscillator.

In some embodiments, the timing circuit described above further includes the following components. The input end of the fourth flip-flop is coupled to the output end of the first oscillator, and the trigger end is coupled to the output end of the second oscillator. The input end of the fifth flip-flop is coupled to the non-inverting output of the fourth flip-flop, and the trigger end is coupled to the output of the second oscillator. The first input end of the NAND gate is coupled to the inverting output end of the fourth flip flop, and the second input end is coupled to the positive phase output end of the fifth flip flop. The timing end of the timer is coupled to the fixed voltage, the trigger end is coupled to the output end of the second oscillator, and the reset end is coupled to the output end of the anti-gate.

In some embodiments, the reset ends of the first flip-flop, the second flip-flop, and the third flip-flop are coupled to the output of the anti-gate.

The built-in self-test circuit proposed by the embodiment of the invention can be used to detect whether the jitter of the clock signal conforms to the standard.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧ Built-in self-test circuit

110‧‧‧clock receiving circuit

111~113, 124, 125‧‧‧ forward and reverse

120‧‧‧Timekeeping Circuit

121, 122‧‧‧ oscillator

126‧‧‧Anti-gate

127‧‧‧Timer

130‧‧‧Jitter judgment circuit

131, 132‧‧‧ register

133‧‧‧Computation circuit

CLK‧‧‧ clock signal

START‧‧‧Start signal

STOP‧‧‧ stop signal

D‧‧‧ input

Q‧‧‧Phase phase output

‧‧‧inverted output

RST‧‧‧Reset

OscA, OscB‧‧‧ oscillation signal

A, B‧‧‧ signal

RSTN‧‧‧Reset signal

UP‧‧‧Timed end

T1‧‧‧ first time

T2, T3‧‧‧ time

T4~T6‧‧‧ time point

FIG. 1 is a block diagram showing a built-in self-test circuit 100 in accordance with an embodiment.

2 and FIG. 3 are timing diagrams of signals in FIG. 1 according to an embodiment.

The terms "first", "second", "etc." used in this document are not intended to mean the order or the order, and are merely to distinguish between elements or operations described in the same technical terms. In addition, as used herein, "coupled" may mean that two elements are electrically connected, either directly or indirectly. That is, when the following description "the first object is coupled to the second object", other items may be disposed between the first object and the second object.

1 is a block diagram showing a built-in self test (BIST) circuit 100 for detecting whether a jitter in a clock signal CLK conforms to a standard, according to an embodiment. For example, it is determined whether the amount of jitter of the clock signal CLK is less than 3% or the like. The clock signal CLK is from any suitable clock generation circuit, such as a phase locked loop, a delay line loop, an oscillator, etc., but the present invention does not limit the source of the clock signal CLK. Built-in self-test circuit 100 includes clock reception The circuit 110, the timing circuit 120, and the jitter determination circuit 130.

The clock receiving circuit 110 is configured to receive the clock signal CLK and perform an operation (a): generating a start signal START and a stop signal STOP according to the clock signal CLK. The stop signal STOP is behind the start signal START for one cycle, which refers to the period of the clock signal CLK. It is worth noting that the period of the clock signal CLK may change with time due to jitter, but this does not affect the operation of the clock receiving circuit 110. Specifically, the clock receiving circuit 110 includes a first flip-flop 111, a second flip-flop 112, and a third flip-flop 113. The input terminal D of the first flip-flop 111 is coupled to the high-level voltage (ie, logic "1"), and the trigger terminal (also referred to as the clock-end terminal) is coupled to the clock signal CLK. The input terminal D of the second flip-flop 112 is coupled to the positive-phase output terminal Q of the first flip-flop 111, the trigger terminal is coupled to the clock signal CLK, and the positive-phase output terminal Q outputs the start signal START. The input terminal D of the third flip-flop 113 is coupled to the positive-phase output terminal Q of the second flip-flop 112, the trigger terminal is coupled to the clock signal CLK, and the positive-phase output terminal Q outputs the stop signal STOP. Referring to FIG. 1 and FIG. 2 simultaneously, when the clock signal CLK forms the first rising edge, the positive phase output terminal Q of the first flip-flop 111 outputs a high level, and the second flip-flop 112 and the third positive and negative elements The positive phase output terminal Q of the device 113 outputs a low level. When the clock signal CLK forms a second rising edge, the positive phase output terminal Q of the first flip-flop 111 still outputs a high level, but the positive phase output terminal Q of the second flip-flop 112 is converted from a low level to a high level. The level (forming a rising edge), the positive phase output terminal Q of the third flip-flop 113 outputs a low level. When the clock signal CLK forms a third rising edge, the positive phase output terminal Q of the first flip-flop 111 still outputs a high level, and the positive phase output terminal Q of the second flip-flop 112 outputs a high level. Three-reactor 113 The positive phase output Q is converted from a low level to a high level (forming a rising edge). Thereby, the rising edge of the stop signal STOP is one cycle behind the rising edge of the start signal START.

The timer circuit 120 receives the start signal START and the stop signal STOP, and performs operation (b): detecting the first time T1 between the start signal START and the stop signal STOP. That is, the timing circuit 120 is used to calculate the length of time of one cycle. In this embodiment, the timing circuit 120 includes a Vernier-based time to digital converter. Specifically, the timing circuit 120 includes a first oscillator 121, a second oscillator 122, a fourth flip-flop 124, a fifth flip-flop 125, an inverse gate 126, and a timer 127. The first oscillator 121 and the second oscillator 122 are, for example, ring oscillators, but in other embodiments, an inductor-capacitor (LC) oscillator or other suitable oscillator may also be used, and the present invention is not limited thereto. . The first oscillator 121 receives the start signal START and is driven by the rising edge of the start signal START to output the oscillation signal OscA. The second oscillator 122 receives the stop signal STOP and is driven by the rising edge of the stop signal STOP to output the oscillation signal OscB. The oscillation frequency of the second oscillator 122 is greater than the oscillation frequency of the first oscillator 121. For example, the oscillation frequency of the second oscillator 122 is 1% to 8% more, but the invention is not limited thereto. The input terminal D of the fourth flip-flop 124 is coupled to the output of the first oscillator 121 to receive the oscillation signal OscA, and the trigger terminal is coupled to the output of the second oscillator 122 to receive the oscillation signal OscB, the positive phase output terminal. Q outputs signal B. The input terminal D of the fifth flip-flop 125 is coupled to the positive-phase output terminal Q of the fourth flip-flop 124, and the trigger terminal is coupled to the output terminal of the second oscillator 122 to receive the oscillation signal OscB, and the positive-phase output terminal Q Then the signal A is output. The first input end of the NAND gate 126 is coupled to the inverted output end of the fourth flip flop 124 The second input terminal is coupled to the positive phase output terminal Q of the fifth flip-flop 125 to receive the signal A, and the gate 126 outputs the reset signal RSTN. The timing terminal UP of the timer 127 is coupled to a fixed voltage (for example, a high level), the trigger terminal is coupled to the output end of the second oscillator 122 to receive the oscillation signal OscB, and the reset terminal RST is coupled to the reverse gate. The output of 126 receives the reset signal RSTN.

The operation principle of the timing circuit 120 is as follows, please refer to FIG. 1 and FIG. 2 at the same time. The first oscillator 121 starts to oscillate when the start signal START forms a rising edge, and the second oscillator 122 starts to oscillate when the end signal STOP forms a rising edge, so the oscillation signal OscB will lag behind the oscillation signal OscA in the initial stage. However, since the oscillation frequency of the oscillation signal OscB is large, that is, the period is small, the oscillation signal OscB gradually "catch up" the oscillation signal OscA. For example, it is assumed that the period of the oscillation signal OscA is equal to the time T _Δ after subtracting the period of the oscillation signal OscB. In FIG. 2, the first rising edge of the oscillation signal OscA is different from the first rising edge of the oscillation signal OscB by time T2, and the second rising edge of the oscillation signal OscA and the second rising edge of the oscillation signal OscB There is a difference between time T3 and time T2 which is greater than time T3 (this gap is usually small and not clearly discernible in the illustration), specifically T2=T3+T _△ . Therefore, the rising edge of the oscillation signal OscB gradually approaches the rising edge of the oscillation signal OscA. Assuming that after N cycles (N is a positive integer), the rising edge of the oscillation signal OscB is synchronized with the rising edge of the oscillation signal OscA, which means that the first time T1 can be calculated according to the following equation (1).

T1=N. T _△ ...(1)

The timer 127 is used to calculate the positive integer N, and the operation of the fourth flip-flop 124 and the fifth flip-flop 125 is equivalent to a phase detector for detecting whether the oscillation signal OscA is synchronized with the oscillation signal. OscB. Specifically, referring to FIG. 1 and FIG. 3, during the oscillation signal OscB chasing the oscillation signal OscA, the rising edge of the oscillation signal OscB triggers the timer 127. Since the voltage on the timing terminal UP is a fixed value, the timer 127 will continue to accumulate a value equal to the number of clocks in the oscillation signal OscB. At the time point T4, when the fourth flip-flop 124 samples the oscillation signal OscA according to the rising edge of the oscillation signal OscB, it samples to a high level, which indicates that the oscillation signal OscB has not caught up with the oscillation signal OscA, and the fourth flip-flop The signal B on the positive phase output terminal Q of 124 will be at a high level. At time T5, when the fourth flip-flop 124 samples the oscillating signal OscA according to the rising edge of the oscillating signal OscB, it will sample to the low level, which means that the oscillating signal OscB has caught up with the oscillating signal OscA, and the signal B will be from the high standard. The bit is converted to a low level, and the signal A is equivalent to the signal B of the previous clock (ie, the high level). At time T6, the first input of the anti-gate 126 is inverted to the signal B, that is, the high level, and the second input of the gate 126 is the signal A, which is also a high level, and therefore the gate is reversed. The output reset signal RSTN of 126 will change from the high level to the low level, the timer 127 will be reset, and the timer 127 will retain the accumulated value as the positive integer N described above. As shown in the above equation (1), this positive integer N can be used to calculate the first time T1.

On the other hand, the first flip-flop 111 and the second flip-flop 112 are The reset terminal RST of the third flip-flop 113 is coupled to the output of the inverse gate 126 to receive the reset signal RSTN, so that the flip-flops 111-113 are reset at the time point T6. Next, the clock receiving circuit 110 regenerates the start signal START and the stop signal STOP, that is, the above operation (a) is re-executed, and the timer circuit 120 recalculates the first time T1, that is, re-executes the above operation ( b). The clock receiving circuit 110 and the timing circuit 120 respectively perform operations (a) and (b) multiple times (for example, 8 times, but the invention is not limited thereto) to generate a plurality of second times, and the second time includes The first time T1. Each second time represents the period of the clock signal CLK, but since the clock signal CLK may have jitter, which means that these second times may be different from each other, then the jitter determination circuit 130 can judge according to these second times. Whether the degree of jitter meets a standard.

The jitter determination circuit 130 includes a first register 131, a second register 132, and a calculation circuit 133. Whenever a new second time is generated, as long as the second time is greater than the value in the first register 131, the value in the first register 131 can be replaced with the new second time; The second time is less than the value in the second register 132, and the value in the second register 132 can be replaced with the new second time. In this way, the first register 131 can be used to store the maximum value, and the second register 132 can be used to store the minimum value. The calculation circuit 133 calculates the average of the maximum value and the minimum value as a reference value, which can be expressed as the following equation (2), where Base is the reference value, Max is the maximum value, and Min is the minimum value.

Base=(Max+Min)/2...(2)

On the other hand, the calculation circuit 133 multiplies the reference value by a preset value to obtain a jitter threshold. The preset values are programmable, such as one of 0.25, 0.125, 0.0625, and 0.03125. These values are taken because the reference value is shifted to the right by 2, 3, 4, or 5 when doing the multiplication operation. The bit can be. However, in other embodiments, the above-mentioned preset values may also adopt other values, and the present invention is not limited thereto. The jitter threshold is calculated as Equation (3) below, where jitter _SPc is the jitter threshold and S is the preset value.

Jitter _spc =Base×S...(3)

Further, the calculation circuit 133 may subtract the minimum value from the maximum value as the amount of jitter, which may be expressed as the following equation (4), where the jitter is the amount of jitter.

Jitter=Max-Min...(4)

The calculation circuit 130 determines whether the jitter amount jitter is smaller than the jitter threshold value jitter _spc . If the jitter amount jitter is smaller than the jitter threshold value jitter _spc , the jitter determination circuit 130 outputs a pass signal indicating that the clock signal CLK has passed the detection of the jitter. For example, if the user wants to detect whether the amount of jitter is less than 12.5%, the preset value can be selected to be 0.125, and the calculated jitter threshold value jitter _spc will theoretically be 12.5% of the period, if the jitter amount jitter is less than The jitter threshold value jitter _spc means that the detection is passed.

It is noted that, due to the jitter threshold jitter _SPC dither jitter amount is calculated according to a second time, thus avoiding voltage temperature process (process voltage temperature, PVT) effects. For example, if the frequency of the first oscillator 121 and the second oscillator 122 is changed due to the temperature rise or fall, since the jitter amount jitter and the jitter threshold value jitter _spc are synchronously changed, the jitter is not affected. .

In the above embodiment, the stop signal STOP is one cycle behind the start signal START, but in other embodiments, the stop signal STOP may also be behind the start signal START for a plurality of cycles. Such an embodiment does not affect the jitter determination.

In the above embodiment, the reference value is obtained by calculating the average of the maximum value and the minimum value, but in other embodiments, the reference value may also be the average of the second time. For example, the jitter determination circuit 130 has a memory unit (not shown) for storing the second time, and another calculation unit (not shown) is used to calculate the average of the second time. In this embodiment, the reference value. The preset value is also multiplied to get the jitter threshold. In other embodiments, the reference value may also be the median of the second time, and the invention is not limited thereto. On the other hand, in the above embodiment, the amount of jitter is obtained by subtracting the maximum value from the minimum value, but in other embodiments, an extreme value (which may be the maximum value or the minimum value) may be subtracted from the reference value. The amount of jitter is calculated.

In other words, the jitter determination circuit 130 calculates a reference value based on the second time, and calculates a jitter threshold based on the reference value, which may be an average value, a median, or a maximum value in the second time. The average of the minimum. The jitter determination circuit 130 also obtains at least one extreme value of the second time, the extreme value may be a minimum value and/or a minimum value, and the amount of jitter is calculated according to the extreme value, for example, the maximum value is subtracted from the minimum value, or Is to subtract the maximum value from the reference value, or subtract the minimum value from the reference value. Since the jitter threshold and the jitter amount are calculated according to the second time, it can be avoided. Without the influence of PVT, those skilled in the art can design other reference values and jitter amounts according to such teachings, and the present invention is not limited to the above embodiments.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

Claims (10)

A built-in self-test circuit for clock jitter is applicable to a clock signal having a period. The built-in self-test circuit includes: a clock receiving circuit that receives the clock signal and performs an operation (a): Generating a start signal and a stop signal according to the clock signal, wherein the stop signal is behind the start signal for one or more of the cycles; a timing circuit receives the start signal and the stop signal and performs an operation (b): detecting a first time when the start signal and the stop signal are different, wherein the clock receiving circuit and the timing circuit respectively perform the operation (a) and the operation (b) a plurality of times to generate a plurality of second times, The second time includes the first time; and a jitter determining circuit is configured to calculate a reference value according to the second time, and calculate a jitter threshold according to the reference value, wherein the jitter determining circuit obtains the At least one extreme value of the second time, and calculating a jitter amount according to the at least one extreme value, wherein the jitter determination circuit determines whether the jitter amount is less than the jitter threshold value, If the jitter amount is less than the dither threshold value, the determination circuit outputs a dither signal through. Built-in self-test as described in item 1 of the patent application scope a trial circuit, wherein the reference value is an average of the second times, and the jitter determination circuit multiplies the reference value by a predetermined value to obtain the jitter threshold. The built-in self-test circuit according to claim 1, wherein the at least one extreme value includes a maximum value and a minimum value of the second time, and the jitter determination circuit subtracts the maximum value from the minimum value. Value to get the amount of jitter. The built-in self-test circuit according to claim 3, wherein the jitter judging circuit calculates an average of the maximum value and the minimum value to obtain the reference value, and multiplies the reference value by a preset value to obtain The jitter threshold. The built-in self-test circuit according to claim 4, wherein the preset value is programmable, and the preset value is one of 0.25, 0.125, 0.0625 and 0.03125. The built-in self-test circuit according to claim 4, wherein the jitter judging circuit comprises: a first register for storing the maximum value; and a second register for storing the minimum value; And a calculation circuit. The built-in self-test circuit of the first aspect of the invention, wherein the clock receiving circuit comprises: a first flip-flop, the input end of which is coupled to a high-level voltage, and the trigger end is coupled to the time a second positive-reactor, the input end of which is coupled to the positive-phase output end of the first flip-flop, the trigger end is coupled to the clock signal, and the positive-phase output of the second flip-flop is output The start signal; and a third flip-flop having an input coupled to the positive phase output of the second flip-flop, the trigger coupled to the clock signal, the positive phase of the third flip-flop The output outputs the stop signal. The built-in self-test circuit according to claim 7, wherein the timing circuit comprises: a first oscillator that receives the start signal and is driven by the start signal; and a second oscillator that receives the stop The signal is driven by the stop signal, wherein the oscillation frequency of the second oscillator is greater than the oscillation frequency of the first oscillator. The built-in self-test circuit of claim 8, wherein the timing circuit further includes: a fourth flip-flop having an input coupled to the output of the first oscillator, the trigger coupled to An output of the second oscillator; a fifth flip-flop having an input coupled to the positive phase of the fourth flip-flop An output end, the trigger end is coupled to the output end of the second oscillator; a reverse gate, the first input end is coupled to the inverting output end of the fourth flip-flop, and the second input end is coupled to a positive phase output terminal of the fifth flip-flop; and a timer, the timing end of which is coupled to a fixed voltage, the trigger end is coupled to the output end of the second oscillator, and the reset end is coupled to the opposite end And the output of the gate. The built-in self-test circuit according to claim 9, wherein the first flip-flop, the second flip-flop and the reset end of the third flip-flop are coupled to the anti-gate The output.