CN103580696B

CN103580696B - A kind of time deviation selection circuit

Info

Publication number: CN103580696B
Application number: CN201210277401.2A
Authority: CN
Inventors: 李巍; 纪伟伟
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2012-08-06
Filing date: 2012-08-06
Publication date: 2016-11-16
Anticipated expiration: 2032-08-06
Also published as: CN103580696A

Abstract

The invention belongs to time measurement technology field, be specifically related to a kind of time deviation selection circuit, this circuit is the time measuring circuit being applied to be made up of two-stage time-to-digit converter.Time deviation selection circuit of the present invention is by selective signal generator, time delay module and gating module composition, gating module uses two identical multiselect one linear selector compositions, and one of them selector (MUX) is effective selector, and another selector is pseudo-selector (D MUX).Selector (MUX) and pseudo-selector (D MUX) input be all merging input D<N:1>, the time delay output of STOP} A<N:1>, B}, with the deviation introducing transmission delay of minimum degree.Time deviation selection circuit of the present invention simple and reasonable for structure, effective deviation can be realized select, both achieve correct deviation gating, and turn avoid and introduce too much time deviation, especially non-linear deviation, effectively overcomes the technological difficulties of the TDC measure of time of two-layer configuration.

Description

A kind of time deviation selection circuit

Technical field

The invention belongs to time measurement technology field, be specifically related to a kind of time deviation selection circuit, be specifically related to be applied to two-stage The time measuring circuit that time-to-digit converter is constituted.

Background technology

Time-to-digit converter (Time to Digital Converter, TDC), is the circuit that the time changes into numeral expression.TDC It was mainly used in laser range finding, ATE and timing jitter in the past to measure, the height that present stage occurs along with process reduction Resolution TDC is that the Digital Implementation of PLL and ADC has paved road.

TDC mainly includes two parts, sample circuit and corresponding decoding circuit；Sample circuit realizes from the time to the conversion of numeral, Decoding circuit realize corresponding from thermometer-code to the conversion of binary system code system, sample circuit is the key of TDC performance.

The long meeting of TDC time delay chain causes non-linear cumulative and the poorest, but TDC needs again to meet high-resolution and measurement scope Requirement.Then, two-stage TDC having high-resolution and high linearity concurrently is just arisen at the historic moment.

The difficult point of two-stage TDC and key point are the time deviation selection circuits between two-stage TDC quantized level, are on the one hand just needing Really gating, on the other hand to avoid introducing bigger time deviation, especially Nonlinear Time deviation.

The two-layer configuration occurred at present, has DLL structure, time window structure and time amplifier structure etc.；DLL structure Excessively complexity causes area power consumption undesirable, thereby increases and it is possible to introduce non-linear；Time window structure is that the output to trigger processes, Trigger process and processing procedure be not because signal is that identical variation characteristic does not consider PVT characteristic, it is also possible to introduces uncontrollable Time deviation；In time amplifier structure, time amplifier inherently non-linear causes unmanageable robustness to become Significant deficiency for this structure.

Summary of the invention

It is an object of the invention to provide a kind of effective gating that both can realize time deviation, transmitting procedure can be avoided again to introduce Bigger error, especially nonlinearity erron, the time deviation selection circuit being applied in two-stage time-to-digit converter.

The time deviation selection circuit that the present invention proposes is made up of selective signal generator, time delay module and gating module, is located at two Between level TDC, for the intergrade of two-stage quantized level in two-stage TDC, from N number of deviation, select the deviation of minimum.Its input It is time delayed signal group D<N:1>and reference signal STOP of the START of first order TDC, from each time of first order TDC Time deviation D<k>and reference signal STOP that gate minimum in deviation enter second level TDC and quantify.Selection signal is sent out Raw device generates the selection signal of gating module, determines D<N:1>in D<k>gating output, use verilog code to realize, The selection signal of D<k in time delayed signal group D<N:1>that generation first order TDC slightly quantifies>entrance second level TDC Which signal SEL_signal, by processing the quantized result of first order TDC, record according to design requirement and be strobed output. Generally START signal early than reference signal STOP, then select first be transformed into from 10 moment；If START Signal overturns with reference signal STOP, then select first moment being transformed into 1 from 0；If two input signals are the most true Fixed, then select the moment of first order TDC output conversion.Wherein, the input of selective signal generator is that first order TDC quantifies The output of trigger, detects first 1-0 by digital bombination circuit and increase flag bit and changes or first 0-1 conversion k Value is also stored in selection signal SEL_signal.Time delay module ensures that data signal is later than selection signal and arrives gating module.

Gating module is by the core circuit of minimum deflection gating output, it is achieved real gating function, and it is inclined to avoid introducing time delay Difference.Gating module needs the two paths of signals D<k of gating to allow>and reference signal STOP through identical time delay, employing two Individual identical multiselect one linear selector forms, and a selector is effective selector (MUX), makes gating D<k> Selecting output, its output SEL_signal selecting signal to be selective signal generator, another selector is pseudo-selector (D-MUX), only allowing reference signal STOP export through identical time delay, it selects signal to be constant Constant, it addition, Selector (MUX) and pseudo-selector (D-MUX) input be all merging input D<N:1>, the time delay output of STOP} A<N:1>, and B}, so can be with the deviation introducing transmission delay of minimum degree.

The propagation delay of gating process depends on that signal passes through the time required for transistor and charge and discharge capacitance, selector basic Structure is multiselect one linear structure, and the status of each input is identical, in the case of disregarding process deviation, and arbitrary input Need the transistor of process and dead resistance, electric capacity etc. identical to output.Common TDC is only by between asynchronous time Be all clean rising edge signal every measurement, i.e. START and reference signal STOP, frequency is close or frequency all ratios are relatively low. Then, gate with pseudo-gate owing to input is identical and selects signal similar, warp during effective signal propagation and transformation The transistor crossed is identical with the factor of dead resistance, electric capacity and frequency, then D<k>and the transmission of reference signal STOP prolong Shi Xiangtong.Thus selector is the least to the deviation of signal transmission introducing.It addition, the structure of selector is linear, thus this is inclined Difference selection circuit is also linear.

Time deviation selection circuit of the present invention simple and reasonable for structure, especially by choosing linear selector, and input The merging of signal so that the time delayed signal of gating arrives outfan with reference signal through identical circuit and time delay, and the present invention is inclined Difference selection circuit can realize effective deviation and select, and had both achieved correct deviation gating, and turn avoid and introduce the too much time Deviation, especially non-linear deviation, effectively overcome the technological difficulties of the TDC measure of time of two-layer configuration.

Accompanying drawing explanation

Fig. 1 is time deviation selecting circuit structure schematic diagram of the present invention,

Fig. 2 is time deviation selection circuit time diagram of the present invention,

Fig. 3 is the structural representation of gating module,

Fig. 4 is the structural representation of two-stage TDC,

Fig. 5 is the time diagram of two-stage TDC,

Fig. 6 is two-stage MUX structure schematic diagram during N=15,

Fig. 7 is the circuit diagram of MUX unit.

Detailed description of the invention

Below in conjunction with the accompanying drawings the embodiment of the present invention is elaborated.

Fig. 1, time deviation selection circuit of the present invention, by selective signal generator, time delay module and gating module composition, wherein, Gating module (shown in Fig. 3), is constituted real by identical multiselect one linear selector (MUX) and pseudo-selector (D-MUX) Now gate, D<N:1>and reference signal STOP be output as A<N:1 through delay unit>and B, then selector (MUX) Input with pseudo-selector (D-MUX) be A<N:1>, B}.Selective signal generator record first order TDC quantized result The moment of 0 it is transformed into for the first time from 1.Fig. 2 is time deviation selection circuit sequential chart of the present invention.

Shown in Fig. 4, deviation selection circuit of the present invention is applied to the circuit structure of two-stage TDC, for two-stage quantized level in two-stage TDC Intergrade, for two-stage sample circuit and decoding circuit, first order TDC is quantified as slightly quantifying, second level TDC quantify be thin Quantifying, deviation selection circuit of the present invention is located between two-stage quantization.First order TDC quantifies can select based on phase inverter or slow Rushing the low resolution time delay chain of device, second level TDC quantifies to select high-resolution time delay chain based on Vernier time delay chain； Decode the conversion by pseudo-thermometer-code to binary code.

Fig. 5 is the sequential chart of two-stage TDC.The decoding result that first order TDC quantifies is DT, and what second level TDC quantified translates Code result is dt, and final result is:

Dt=DT-dt

Fig. 6 in the present embodiment, sets N=15, owing to input is more, uses two-stage gating structure, the selector of 16:1 (MUX) by 4*(4:1) selector 1 (MUX1)+4:1 selector 2 (MUX2) forms.The base of gating structure shown in Fig. 7 This unit, uses under two groups trombone slide on trombone slide and, and under two groups, the input of trombone slide is gating signal and data signal respectively, thereafter Connecing phase inverter, it is also possible to add buffer again, amplitude and output loading according to output signal determine.When N is other value, also may be used Use the basic element circuit of this gating structure.

Claims

1. a time deviation selection circuit, by selective signal generator, time delay module and gating module composition, it is special Levying and be: gating module is made up of two identical multiselect one linear selector, a selector is effective selection Device (MUX), makes gating D<k>select output, its output SEL_signal selecting signal to be selective signal generator, Another selector is pseudo-selector (D-MUX), only allows reference signal STOP export through identical time delay, and it selects letter Number be constant Constant, selector (MUX) and pseudo-selector (D-MUX) input be all merging input D<N:1>, STOP} time delay output A<N:1>, B}；Selective signal generator generates the selection signal of gating module, determines D<N:1>in D<k>gating output, use verilog code realize；Time delay module makes selection signal prior to data signal Arrive gating circuit input.

Time deviation selection circuit the most according to claim 1, it is characterised in that: it is located between two-stage TDC, For the intergrade of two-stage quantized level in two-stage TDC, its input is the time delayed signal group of the START of first order TDC D<N:1>and reference signal STOP, from each time deviation of first order TDC, gate time deviation D<k>of minimum Enter second level TDC with reference signal STOP to quantify.

Time deviation selection circuit the most according to claim 1, it is characterised in that: selective signal generator defeated Enter the output quantifying trigger for first order TDC, detect first 1-0 by digital bombination circuit and increase flag bit Conversion or first 0-1 conversion, be stored into the k value obtained by detection in selection signal SEL_signal.