CN101499790A - Signal delay circuit - Google Patents

Abstract

The invention discloses a signal delay circuit, comprising a capacitance load component. The component is provided with a first input end, a second input end and a third input end; wherein, the first input end receives a first signal; the second input receives a second signal which is an inversion signal of the first signal; and the third input end receives a control signal; wherein, the capacitance value of the capacitance load component is changed with the control signal.

Description

Signal delay circuit

Technical field

The invention discloses a kind of capacitive load assembly, relate in particular to a kind of capacitive load assembly that is used for signal delay circuit.

Background technology

About digital control arteries and veins delay circuit (digital control delay element), with regard to the mechanism of framework and adjustment, can be divided into analog delay circuit and digital delay circuit.

The feature of analog delay circuit is that analog control signal adds analog delay circuit, and common analog delay circuit includes a digital revolving die and intends a circuit and a delay circuit.(Digital to Analog Converter, DAC) digital controlled signal with the outside is converted to aanalogvoltage to digital controlled signal to analog conversion circuit by numeral.Delay circuit then is made up of a different load resistance or a load capacitance of being made up of N transistor npn npn or P transistor npn npn of differential pair circuit collocation.By the parameter in the fine tune Delay Element,, reach the purpose that changes signal delay time as bias current, output point load capacitance value or load resistance value.Analog delay circuit has resolution and high noise resisting ability, but comparatively complicated in the design, and design cost is also comparatively expensive.In the process of design simulation formula delay circuit, need do repeatedly the fine setting of recursion (iteration) to size of components and operating point, each upgrade make flow process after circuit also need redesign.And digital delay circuit is by the direct control figure delay cell of digital controlled signal, and delay cell itself is made up of inverter, transmission gate, multiplexer, NAND door, NOR door etc.

Fig. 1 is the disclosed digital delay circuit of known technology, and it is made up of a transmission gate 10, one first inverter 11 and one second inverter 12.As shown in the figure, the input In of first inverter 11 receives a signal, and will be exported by output Out after this signal inversion.The input of transmission gate 10 and output also are connected to the output Out of first inverter 11 simultaneously except directly linking to each other.The control end of transmission gate 10 is controlled signal Ctrl and controls.Second inverter 12 receives control signal Ctrl, and the control signal Ctrlb after anti-phase is outputed to another control end of transmission gate 10.

The equivalent electric circuit of transmission gate 10 as shown in Figure 2, form by PMOS transistor 13 and nmos pass transistor 14, the source electrode of PMOS transistor 13 and the output Out that drains and be connected and be connected to first inverter 11, the control signal Ctrlb after the gate pole reception of PMOS transistor 13 is anti-phase.The source electrode of nmos pass transistor 14 receives control signal Ctrl with the output that drains and be connected equally and also be connected to first inverter 11, the grid of nmos pass transistor 14.In the drawings, CN represents the electric capacity by nmos pass transistor that output is seen 14, and CP represents the transistorized electric capacity by PMOS that output is seen.

When the control signal Ctrl that control end received of transmission gate 10 is 0, this moment, no matter the accurate position of logic of the output point of first inverter 11 was 1 or 0, and the capacitance of transmission gate 10 is to equal the capacitance that nmos pass transistor closes to add the capacitance that the PMOS transistor is closed.

At the control signal Ctrl that control end received of transmission gate 10 is 1 o'clock, when the accurate position of the logic of the output of first inverter 11 is 0, this moment, the capacitance of output of first inverter 11 was that the capacitance of nmos pass transistor conducting adds the capacitance that the PMOS transistor is closed.When the accurate position of the logic of the output of first inverter 11 is 1, this moment, the capacitance of output point of first inverter 11 was the capacitance that capacitance that nmos pass transistor is shut adds the PMOS transistor turns.Fig. 3 A is the parasitic capacitance value variation schematic diagram of first inverter, 11 output points under the different control signals with Fig. 3 B.Fig. 3 A is 0 o'clock for control signal Ctrl, and curve 15 is the variation schematic diagram of PMOS transistor capacitance amount, and curve 16 is the variation schematic diagram of nmos pass transistor capacitance.Fig. 3 B is 1 o'clock for control signal Ctrl, and curve 17 is the variation schematic diagram of PMOS transistor capacitance amount, and curve 18 is the variation schematic diagram of nmos pass transistor capacitance.By among the figure as can be known because the change of control signal, the transmission delay of this circuit can increase because of the increase of parasitic capacitance value.

Fig. 4 is disclosed another delay circuit of known technology, and it is made up of inverter 20 and NAND door 21.The input In of inverter 20 receives a signal, and will be exported by output Out after this signal inversion.NAND door 21 has first input end, second input and output.The output Out of the first input end of NAND door 21 and inverter 20 electrically connects, and second input of NAND door 21 then receives control signal Ctrl, and the output of NAND door 21 then is a suspension joint.

The equivalent circuit diagram of NAND door 21 can be represented by PMOS transistor 22,24 and nmos pass transistor 23,25 as shown in Figure 5 among Fig. 4.Fig. 6 A is the parasitic capacitance value variation schematic diagram of inverter 20 output point Out under the different control signals with Fig. 6 B.

In Fig. 6 A, when control signal Ctrl is 0, curve 26 is the variation schematic diagram of PMOS transistor 22 in the parasitic capacitance of inverter 20 outputs generation, and curve 27 is the variation schematic diagram of nmos pass transistor 23 in the parasitic capacitance of inverter 20 output points generation.In Fig. 6 B, when control signal Ctrl is 1, curve 28 is the variation schematic diagram of PMOS transistor 22 in the parasitic capacitance of inverter 20 output points generation, and curve 29 is the variation schematic diagram of nmos pass transistor 23 in the parasitic transistor capacitance of inverter 20 output points generation.

At control signal Ctrl is under the situation of logical zero, this moment, no matter the accurate position of logic of inverter 20 outputs was 1 or 0, nmos pass transistor 23 is all for closing, and PMOS transistor 22 can be conducting in 0 o'clock in the accurate position of the logic of inverter 20 outputs, and is to close in 1 o'clock in the accurate position of output.At control signal Ctrl is under the situation of logical one, the capacitance of NMOS crystal 23 can change with output voltage, in the accurate position of output is conducting in 1 o'clock, and be to close in 0 o'clock in the accurate position of output, the capacitance of PMOS transistor 22 also can change with output voltage, situation and control signal Ctrl be 0 o'clock much at one, difference is to be located at non-0 also non-1 interval when output voltage values, nmos pass transistor 23 has temporary transient conducting state, this makes the interval meeting of conducting of PMOS transistor 22 slightly increase, therefore capacitance variation also slightly increases, PMOS transistor 22 capacitance variation are negligible than the capacitance variation of nmos pass transistor 23, therefore can produce the electric capacity difference that nmos pass transistor 23 is shut and opened by control signal Ctrl.By Fig. 6 A and Fig. 6 B as can be known, because the change of capacitance, the transmission delay meeting of this circuit as a result thereby increase, in addition comparison diagram 6B and Fig. 3 B as can be seen the disclosed signal delay circuit of Fig. 4 than Fig. 1 trickleer capacitance variation is arranged, therefore can produce trickleer frequency and postpone.

Summary of the invention

The object of the present invention is to provide a kind of signal delay circuit, compare with known DIGITAL FREQUENCY delay circuit technology, has higher resolution time of delay, compare with known analog frequency delay circuit technology, the circuit area that is consumed is lower, is operable in lower supply voltage simultaneously.

To achieve these goals, the invention provides a kind of signal delay circuit, include a capacitive load assembly, this assembly has a first input end, one second input and one the 3rd input, wherein first input end receives one first signal, and second input receives a secondary signal, and secondary signal is the inversion signal of first signal, the 3rd input receives a control signal, and wherein the capacitance of this capacitive load assembly changes with this control signal.

Signal delay circuit disclosed in this invention, it removes to finish the signal delay circuit of a high frequency resolution with digital control delay circuit control mode, compare with known DIGITAL FREQUENCY delay circuit technology, has higher resolution time of delay, compare with known analog frequency delay circuit technology, the circuit area that is consumed is lower, is operable in lower supply voltage simultaneously.

Signal delay circuit disclosed in this invention, than the board design mode, also reduce relatively on the design complexities, adjustment for circuit performance is by changing the combination of digital circuit unit, and need not do fine setting to each transistorized size respectively, therefore less when making the design time once more that is spent when flow process shifts.

Signal delay circuit disclosed in this invention in theory analysis and realistic simulation, all can reach higher frequency resolution.

Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.

Description of drawings

Fig. 1 is the disclosed delay circuit of known technology;

Fig. 2 is the schematic diagram of the equivalent electric circuit of the disclosed delay circuit of Fig. 1;

Fig. 3 A and Fig. 3 B are the schematic diagram of the electric capacitance change of the disclosed delay circuit of Fig. 1 under different control signals;

Fig. 4 is the schematic diagram of disclosed another delay circuit of known technology;

Fig. 5 is the schematic diagram of the equivalent electric circuit of the disclosed delay circuit of Fig. 4;

Fig. 6 A and Fig. 6 B are the schematic diagram of the electric capacitance change of the disclosed delay circuit of Fig. 4 under different control signals;

Fig. 7 A and Fig. 7 B are the schematic diagram of the disclosed signal delay circuit of the embodiment of the invention;

Fig. 8 A is the schematic diagram of first embodiment of delay circuit disclosed in this invention;

Fig. 8 B is the schematic diagram of the equivalent electric circuit of the disclosed delay circuit of Fig. 8 A;

Fig. 9 A and Fig. 9 B are the schematic diagram of the electric capacitance change of the disclosed delay circuit of Fig. 8 A under different control signals;

Figure 10 A and Figure 10 B are the schematic diagram of second embodiment of delay circuit disclosed in this invention;

Figure 11 is the schematic diagram of the 3rd embodiment of delay circuit disclosed in this invention;

Figure 12 is the schematic diagram of the equivalent electric circuit of the disclosed delay circuit of Figure 11;

Figure 13 A and Figure 13 B are the schematic diagram of the electric capacitance change of the disclosed delay circuit of Figure 11 under different control signals;

Figure 14 A and Figure 14 B are the schematic diagram of the 4th embodiment of delay circuit disclosed in this invention;

Figure 15 is the schematic diagram of actual verification of the electric capacitance change of the disclosed delay circuit of Fig. 1;

Figure 16 is the actual verification of the electric capacitance change of the disclosed delay circuit of Fig. 4;

Figure 17 is the schematic diagram of actual verification of the electric capacitance change of the disclosed delay circuit of Fig. 7;

Figure 18 is in order to the schematic diagram of the inverter circuit of the resolution of the circuit of difference survey map 1, Fig. 4 and Fig. 7;

Figure 19 A is the schematic diagram of data of the circuit of survey map 1, Fig. 4 and Fig. 7;

Figure 19 B is the schematic diagram of 000 and 111 special case for control signal among Figure 17 A.

Wherein, Reference numeral:

10 transmission gates

11 first inverters

12 second inverters

13 PMOS transistors

14 nmos pass transistors

15 curves

16 curves

17 curves

18 curves

20 inverters

21 NAND doors

22 PMOS transistors

23 nmos pass transistors

24 PMOS transistors

25 nmos pass transistors

26 curves

27 curves

28 curves

29 curves

30 NAND doors

31 inverters

32 PMOS transistors

33 nmos pass transistors

34 PMOS transistors

35 PMOS transistors

36 nmos pass transistors

37 nmos pass transistors

The 38A curve

The 38B curve

The 39A curve

The 39B curve

40 NAND doors

41 first inverters

42 second inverters

43 NAND doors

50 NOR doors

51 inverters

52 nmos pass transistors

53 PMOS transistors

54 nmos pass transistors

55 nmos pass transistors

56 PMOS transistors

57 PMOS transistors

The 58A curve

The 58B curve

The 59A curve

The 59B curve

60 NOR doors

61 first inverters

62 second inverters

63 NAND doors

71 curves

72 curves

73 curves

74 curves

75 curves

76 curves

77 curves

78 curves

79 curves

80 curves

81 curves

82 curves

91 inverters

92 inverters

93 inverters

94 inverters

95 inverters

96 inverters

97A condenser type load 9

97B condenser type load 9

97C condenser type load 9

98A condenser type load 9

98B condenser type load 9

The load of 98C condenser type

100 gates

101 dead resistances

102 dead resistances

103 dead resistances

104 dead resistances

105 switches

106 switches

107 switches

The Ctrl control signal

The Ctrlb control signal

The In input

The Inb input

The Out output

The Outb output

V1 voltage

V2 voltage

Sin first signal

The Sinb secondary signal

The In1 input

The Inb1 input

The Out1 output

The Outb1 output

The C0 control signal

The C1 control signal

The C2 control signal

Embodiment

Please refer to Fig. 7 A and Fig. 7 B, be the schematic diagram of the disclosed signal delay circuit of the embodiment of the invention.Disclosed in an embodiment signal delay circuit is made up of a capacitive load assembly, is a kind of gate 100 with three inputs in this embodiment.This gate 100 is made up of three switches 105,106,107 at least.In one embodiment, can select for use transistor to be used as switch 105,106,107.Resistance is in the drawings represented the dead resistance 101,102,103,104 of interior other driving component of this gate or passive component equivalence.Voltage V1, V2 can be supply voltage or earthed voltage.

In the embodiment shown in Fig. 7 A, switch 105 receives one first signal Sin, and switch 106 receives secondary signal Inb, and switch 107 receives control signal Ctrl.The first signal Sin and secondary signal Sinb be inversion signal each other.In an embodiment, can use an inverter to produce the first signal Sin and secondary signal Sinb.In another embodiment, can use two inverters and produce the first signal Sin and secondary signal Sinb in the mode of differential wave.

In the embodiment shown in Fig. 7 B, switch 105 receives one first signal In, and switch 106 receives secondary signal Inb, and switch 107 receives control signal Ctrl.The first signal Sin and secondary signal Sinb be inversion signal each other.In an embodiment, can use an inverter to produce the first signal Sin and secondary signal Sinb.In another embodiment, can use two inverters and produce the first signal Sin and secondary signal Sinb in the mode of differential wave.

Please refer to Fig. 8 A, be the schematic diagram of the disclosed signal delay circuit of the embodiment of the invention.Disclosed in an embodiment signal delay circuit is made up of a capacitive load assembly, is NAND door 30 in this embodiment.NAND door 30 has first input end, second input, the 3rd input and output.The first input end of NAND door 30 receives first signal, and second input of NAND door 30 receives secondary signal, and first signal and secondary signal be inversion signal each other.In this embodiment, first signal and secondary signal are produced by inverter 21, and first signal is received by the input In of inverter 21, and secondary signal is by the output Out output of inverter 21.The input of the first input end of NAND door 30 and inverter 31 electrically connects, in order to receive first signal, second input of NAND door 30 and the output of inverter 31 electrically connect, in order to receive a secondary signal, the 3rd input of NAND door 30 then receives control signal Ctrl, and the output of NAND door 30 then is a suspension joint.

In this embodiment, secondary signal is the inversion signal of first signal.Therefore, first signal is received by the input In of inverter 31, and exports an inversion signal with as secondary signal by output Out by inverter 31 after with first signal inversion.

The equivalent circuit diagram of the NAND door 30 among Fig. 8 A is shown in Fig. 8 B.The grid of the grid of PMOS transistor 32 and nmos pass transistor 33 is represented the first input end of NAND door 30, PMOS transistor 34 and nmos pass transistor 36 are represented second input of NAND door 30, and PMOS transistor 35 and nmos pass transistor 37 are represented the 3rd input of NAND door 30.

Fig. 9 A and Fig. 9 B are the parasitic capacitor variations schematic diagram that NAND door 30 is caused at inverter 31 output out under the different control signals.In Fig. 9 A, when control signal Ctrl was 0, curve 38A was the variation schematic diagram of PMOS transistor 34 capacitances, and curve 38B is the variation schematic diagram of nmos pass transistor 36 capacitances.In Fig. 9 B, when control signal Ctrl was 1, curve 39A was the variation schematic diagram of PMOS transistor 34 capacitances, and curve 39B is the variation schematic diagram of nmos pass transistor 36 capacitances.

At control signal Ctrl is under the situation of logical zero, this moment, no matter the accurate position of logic of the output of inverter 31 was 1 or 0, PMOS transistor 35 all is an opening, nmos pass transistor 37 all is a closed condition, therefore the accurate position of NAND gate 30 output logics can be 1 always, PMOS transistor 34 can be conducting in 0 o'clock in the accurate position of the logic of inverter 31 outputs, and be to close in 1 o'clock in the accurate position of output, because the accurate position of NAND gate 30 output logics, the accurate position of the logic of the output of nmos pass transistor 36 inverters 31 are 1 or 0 all can't conducting.At control signal Ctrl is under the situation of logical one, PMOS transistor 35 all is a closed condition, nmos pass transistor 37 all is a conducting state, the capacitance variation of PMOS transistor 34 can change with output voltage, change situation and Ctrl and be at 0 o'clock much at one, difference be output voltage values be positioned at non-0 also non-1 interval the time, nmos pass transistor 36 has conducting slightly, make interval can slightly the increasing of conducting of PMOS transistor 34, therefore capacitance variation can slightly increase, the capacitance of NMOS crystal 36 can change with output voltage, in the output accurate position non-0 temporary transient conducting of meeting in also non-1 o'clock, being 0 or all can closing in 1 o'clock in the accurate position of output, is that the situation of logical zero is compared with control signal Ctrl, NMOS crystal 3 more than 6 one section capacitance variation that temporary transient conducting caused.

Because it is anti-phase in the NAND door 30 two input signals being arranged, therefore the nmos pass transistor in the NAND door 30 36 is closing state under lower state.Lower state herein is expressed as the situation of the accurate position 0 or 1 of logic.But when input signal generation transition, near the magnitude of voltage of inverter 31 input in approximates the magnitude of voltage of inverter 31 output out greatly, this nmos pass transistor 36 can be in the state of conducting slightly, and this phenomenon just produces the reason of capacitance variations slightly.Transition herein represents that input signal is transformed into the accurate position 1 of logic by the accurate position 0 of logic, perhaps is transformed into the accurate position 0 of logic by the accurate position 1 of logic.Comparison diagram 9B and Fig. 6 B, the minimizing of capacitance change is represented in the minimizing of hatched example areas, therefore promotes temporal resolution.

Please refer to Figure 10 A, be the schematic diagram of second embodiment of the disclosed signal delay circuit of the embodiment of the invention, in this embodiment with NAND door 40 as the capacitive load assembly.NAND door 40 has first input end, second input, the 3rd input and output, and the first input end of NAND door 40 receives first signal, and second input of NAND door 40 receives secondary signal, and first signal and secondary signal be inversion signal each other.In this embodiment, first signal and secondary signal adopt differential mode to import.The output Outb of the first input end of NAND door 40 and first inverter 41 electrically connects, in order to receive first signal, the input Out of second input of NAND door 40 and second inverter 42 electrically connects, in order to receive secondary signal, the 3rd input of NAND door 40 then receives control signal Ctrl, and the output of NAND door 40 then is a suspension joint.

The input In of first inverter 41 receives first input signal, and first input signal is anti-phase back to export first signal.The input Inb of second inverter 42 receives second input signal, and second input signal is anti-phase back with the output secondary signal, and first input signal and second input signal are differential input signal.The input signal that the first input end of NAND door 40 and second input are received is anti-phase equally.Therefore the input signal that received of first inverter 41 and second inverter 42 is anti-phase equally.

In this embodiment, first signal is by 41 outputs of first inverter.Secondary signal is by 42 outputs of second inverter.Similarly, secondary signal is the inversion signal of first signal.

In above-described embodiment, arrange in pairs or groups inverter as the capacitive load assembly with the NAND door of single-stage.But in other embodiments, also can adopt two groups or more NAND door to form two-stage or the above signal delay circuit of two-stage, shown in Figure 10 B, utilize NAND door 40 and NAND door 43 to form.Similarly, NAND door 43 has first input end, second input, the 3rd input and output, and wherein the input signal of NAND door 43 adopts differential mode to import.The output of the first input end of NAND door 43 and first inverter 41 electrically connects, in order to receive one first signal, the input of second input of NAND door 43 and second inverter 42 electrically connects, and in order to receive a secondary signal, first signal and secondary signal are differential input signal.The 3rd input of NAND door 43 then receives control signal Ctrl, and the output of NAND door 43 then is a suspension joint

Please refer to Figure 11, be the 3rd embodiment schematic diagram of the disclosed signal delay circuit of the embodiment of the invention, disclosed in an embodiment signal delay circuit is made up of a capacitive load assembly, is NOR door 50 in this embodiment.NOR door 50 has first input end, second input, the 3rd input and output.The first input end of NOR door 50 receives first signal, and second input of NOR door 50 receives secondary signal, and first signal and secondary signal be inversion signal each other.In this embodiment, first signal and secondary signal are produced by inverter 51.First signal is received by the input In of inverter 51, and secondary signal is by the output Out output of inverter 51.The input of the first input end of NOR door 50 and inverter 51 electrically connects, in order to receive one first signal, second input of NOR door 50 and the output of inverter 51 electrically connect, in order to receive a secondary signal, the 3rd input of NOR door 50 then receives control signal Ctrl, and the output of NOR door 50 then is a suspension joint.

In this embodiment, secondary signal is the inversion signal of first signal.Therefore, first signal is received by inverter 51, and by inverter 51 with first signal inversion after output one inversion signal with as secondary signal.

The equivalent circuit diagram of the NOR door 50 among Figure 11 as shown in figure 12.The grid of the grid of nmos pass transistor 52 and PMOS transistor 53 is represented the first input end of NOR door 50, nmos pass transistor 54 and PMOS transistor 56 are represented second input of NOR door 50, and nmos pass transistor 55 and PMOS transistor 57 are represented the 3rd input of NOR door 50.

Figure 13 A and Figure 13 B are the parasitic capacitor variations schematic diagram that NOR door 50 is caused at inverter 51 output points under the different control signals.In Figure 13 A, when control signal Ctrl was 1, curve 58A was the variation schematic diagram of PMOS transistor 56 capacitances, and curve 58B is the variation schematic diagram of nmos pass transistor 54 capacitances.In Figure 13 B, when control signal Ctrl was 0, curve 59A was the variation schematic diagram of PMOS transistor 56 capacitances, and curve 59B is the variation schematic diagram of nmos pass transistor 54 capacitances.

At control signal Ctrl is under the situation of logical one, this moment, no matter the accurate position of logic of the output of inverter 51 was 1 or 0, nmos pass transistor 55 all is an opening, PMOS transistor 57 all is a closed condition, therefore the accurate position of NOR gate 50 output logics can be 0 always, nmos pass transistor 54 can be conducting in 1 o'clock in the accurate position of the logic of inverter 51 outputs, and be to close in 0 o'clock in the accurate position of output, because the accurate position of NOR gate 50 output logics is 0, the accurate position of the logic of the output of PMOS transistor 56 inverters 51 is 1 or 0 all can't conducting.At control signal Ctrl is under the situation of logical zero, nmos pass transistor 55 all is a closed condition, PMOS transistor 57 all is a conducting state, the capacitance variation of nmos pass transistor 54 can change with output voltage, change situation and Ctrl and be at 1 o'clock much at one, difference be output voltage values be positioned at non-0 also non-1 interval the time, PMOS transistor 56 has conducting slightly, make interval can slightly the increasing of conducting of nmos pass transistor 54, therefore capacitance variation can slightly increase, the capacitance of PMOS crystal 56 can change with output voltage, in the output accurate position non-0 temporary transient conducting of meeting in also non-1 o'clock, being 0 or all can closing in 1 o'clock in the accurate position of output, is that the situation of logical one is compared with control signal Ctrl, PMOS crystal 5 more than 6 one section capacitance variation that temporary transient conducting caused.

Because it is anti-phase in the NOR door 50 two input signals being arranged, therefore the PMOS transistor 56 in the NOR door 30 is closing state under lower state, but when input signal generation transition, near the magnitude of voltage of inverter 51 inputs approximates the magnitude of voltage of inverter 51 outputs greatly, this PMOS transistor 56 can be in the state of conducting slightly, and this phenomenon just produces the reason of capacitance variations slightly.Comparison diagram 13B and Fig. 6 B, the minimizing of capacitance change is represented in the minimizing of hatched example areas, therefore promotes temporal resolution.

Please refer to Figure 14 A, be the schematic diagram of the 4th embodiment of the disclosed signal delay circuit of the embodiment of the invention, in this embodiment with NOR door 60 as the capacitive load assembly.NOR door 60 has first input end, second input, the 3rd input and output, and the first input end of NOR door 60 receives first signal, and second input of NOR door 60 receives secondary signal, and first signal and secondary signal be inversion signal each other.In this embodiment, first signal and secondary signal adopt differential mode to import.NOR door 60 has first input end, second input, the 3rd input and output.The output Outb of the first input end of NOR door 60 and first inverter 61 electrically connects, in order to receive first signal, the output Out of second input of NOR door 60 and second inverter 62 electrically connects, in order to receive secondary signal, the 3rd input of NOR door 60 then receives control signal Ctrl, and the output of NOR door 60 then is a suspension joint.

The input In of first inverter 61 receives first input signal, and first input signal is anti-phase back to export first signal.The input Inb of second inverter 62 receives one second input signal, and second input signal is anti-phase back with the output secondary signal, and first input signal and second input signal are differential input signal.The input signal that the first input end of NAND door 60 and second input are received is anti-phase equally.Therefore the input signal that received of first inverter 61 and second inverter 62 is anti-phase equally.

In this embodiment, first signal is by 61 outputs of first inverter.Secondary signal is by 62 outputs of second inverter.Similarly, secondary signal is the inversion signal of first signal.

In above-described embodiment, arrange in pairs or groups inverter as the capacitive load assembly with the NOR door of single-stage.But in other embodiments, also can adopt two groups or more NOR door to form two-stage or the above signal delay circuit of two-stage, as shown in Figure 14B, utilize NOR door 60 and NOR door 63 to form.Similarly, NAND door 63 has first input end, second input, the 3rd input and output, and wherein the input signal of NAND door 63 adopts differential mode to import.The output of the first input end of NAND door 63 and first inverter 61 electrically connects, in order to receive one first signal, the input of second input of NAND door 63 and second inverter 62 electrically connects, and in order to receive a secondary signal, first signal and secondary signal are differential input signal.The 3rd input of NAND door 63 then receives control signal Ctrl, and the output of NAND door 63 then is a suspension joint

Please refer to Figure 15 to Figure 17, be respectively the actual verification of the electric capacitance change of Fig. 3, Fig. 6 and Fig. 9.It utilizes Taiwan integrated circuit manufacturing 0.18 micron technology that limited company researched and developed to carry out emulation, transistorized length-width ratio (W/L) is 0.45um/0.18um in all gates, emulation when output voltage changes from 0V to 1.8V, nmos pass transistor parasitic capacitance that output point is seen and PMOS transistor parasitic capacitance.

In Figure 15, curve 71 is the parasitic capacitance of 0 o'clock NMOS for control signal Ctrl, and curve 72 is the parasitic capacitance of 1 o'clock NMOS for control signal Ctrl, and both variations are defined as Δ Cn.Curve 73 is the parasitic capacitance of 0 o'clock PMOS for control signal Ctrl, and curve 74 is the parasitic capacitance of 1 o'clock PMOS for control signal Ctrl, and both variations are defined as Δ Cp.Therefore, under the control of different control signals, the electric capacitance change Δ C of the signal delay circuit shown in Fig. 1 be Δ Cn and Δ Cp and.

In Figure 16, curve 75 is the parasitic capacitance of 0 o'clock PMOS for control signal Ctrl, and curve 76 is the parasitic capacitance of 1 o'clock PMOS for control signal Ctrl, and both variations are defined as Δ Cn.Curve 77 is the parasitic capacitance of 0 o'clock NMOS for control signal Ctrl, and curve 78 is the parasitic capacitance of 1 o'clock NMOS for control signal Ctrl, and both variations are defined as Δ Cp.Therefore, under the control of different control signals, the electric capacitance change Δ C=Δ Cn-Δ Cp of the signal delay circuit shown in Fig. 4.

In Figure 17, curve 79 is the parasitic capacitance of 0 o'clock NMOS for control signal Ctrl, and curve 80 is the parasitic capacitance of 1 o'clock NMOS for control signal Ctrl, and both variations are defined as Δ Cn.Curve 81 is the parasitic capacitance of 0 o'clock PMOS for control signal Ctrl, and curve 82 is the parasitic capacitance of 1 o'clock PMOS for control signal Ctrl, and both variations are defined as Δ Cp.Therefore, under the control of different control signals, the electric capacitance change Δ C=Δ Cn-Δ Cp of the signal delay circuit shown in Fig. 7.

Below for verifying the resolution of capacitive load assembly disclosed in this invention.Please refer to Figure 18, is an inverter circuit, in order to the resolution of the circuit of survey map 1, Fig. 4 and Fig. 7 respectively.Inverter circuit shown in Figure 180 is made up of six inverters 91,92,93,94,95,96, the input termination In1 of inverter 91 receives input signal, output signal is then exported by the output Outb1 of inverter 92, the input Inb1 receiving inputted signal of inverter 93, output signal are then exported by the output Out1 of inverter 94.The output of inverter 91 adds condenser type load 97A, 97B, the 97C of three of binary systems, the output of inverter 93 also adds condenser type load 98A, 98B, the 98C of three of binary systems, these condenser type loads 97A, 97B, 97C, 98A, 98B, 96C adjust the frequency delay of output by control signal C0, C1, C2, and then calculate adjustable extent and frequency resolution. Condenser type load 97A, 97B, 97C, 98A, 98B, 98C realize with Fig. 1, Fig. 4 and the disclosed circuit of Fig. 7.

During test, the time delay of setting input signal In1, Inb1 and output signal Outb1, Out1 is Td.About the size design of inverter, the transistorized breadth length ratio of PMOS (W/L) is 1.62u/0.18u, and the W/L of nmos pass transistor is 0.45u/0.18u.About the size design of gates such as transmission gate 11, NAND door 20 and NAND door 30, the transistorized W/L of PMOS is 45u/0.18u, and the W/L of nmos pass transistor is 0.45u/0.18u.

When testing with Fig. 1, the input of transmission gate 10 and output are all received output signal Out1.When testing with Fig. 4, the first input end of NAND door 21 is received output signal Out1.When testing with Fig. 7, the first input end of NAND door 30 and second input are received output signal Out1, Outb1 respectively.

Control signal from 000 to 111 is changed in regular turn, can obtain as the data of Figure 19 A and the curve chart of Figure 19 B, Figure 19 B is to be that 000 and 111 special case is taken out displaying with control signal among Figure 19 A, therefore the adjustable extent of three kinds of frameworks as can be seen.In this simulation, the resolution that can see Fig. 1 is 3.11ps, and the resolution of Fig. 4 is 1.4ps, and the resolution of capacitive load assembly disclosed in this invention can reach 0.33ps, and tangible improvement is arranged on resolution as can be seen.

Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.

Claims (19)

1, a kind of signal delay circuit is characterized in that, includes:

One capacitive load assembly, this assembly has a first input end, one second input and one the 3rd input, this first input end receives one first signal, this second input receives a secondary signal, wherein this secondary signal is the inversion signal of this first signal, the 3rd input receives a control signal, and wherein the capacitance of this capacitive load assembly changes with this control signal.

2, signal delay circuit according to claim 1 is characterized in that, this capacitive load assembly includes three switches at least.

3, signal delay circuit according to claim 1 is characterized in that, this capacitive load assembly is a NAND door.

4, signal delay circuit according to claim 3 is characterized in that, under lower state, the N transistor npn npn in this NAND door is for closing.

5, signal delay circuit according to claim 3 is characterized in that, when this first signal equated haply with this secondary signal, the N transistor npn npn in this NAND door was in the state of conducting slightly.

6, signal delay circuit according to claim 3 is characterized in that, also includes an inverter, and this inverter receives this first signal, and should with after first signal inversion to export an inversion signal with as this secondary signal.

7, signal delay circuit according to claim 3 is characterized in that, also includes:

One first inverter receives one first input signal, and should be with the anti-phase back of first input signal to export this first signal; And

One second inverter receives one second input signal, and should be with the anti-phase back of second input signal to export this secondary signal.

8, signal delay circuit according to claim 7 is characterized in that, this first input signal and this second input signal are differential input signal.

9, signal delay circuit according to claim 1 is characterized in that, this capacitive load assembly is a NOR door.

10, signal delay circuit according to claim 9 is characterized in that, also includes an inverter, and this inverter receives this first signal, and should with after first signal inversion to export an inversion signal with as this secondary signal.

11, signal delay circuit according to claim 9 is characterized in that, also includes:

One first inverter, this first inverter receives one first input signal, and should be with the anti-phase back of first input signal to export this first signal; And

One second inverter, this second inverter receives one second input signal, and should be with the anti-phase back of second input signal to export this secondary signal.

12, signal delay circuit according to claim 11 is characterized in that, this first input signal and this second input signal are differential input signal.

13, a kind of signal delay circuit is characterized in that, includes:

One first inverter, this first inverter receives one first input signal, and should be with the anti-phase back of first input signal to export one first signal;

One second inverter, this second inverter receives one second input signal, and should be with the anti-phase back of second input signal to export a secondary signal, wherein this secondary signal is the inversion signal of this first signal, wherein this first input signal and this second input signal are differential input signal; And

More than one capacitive load assembly, each this capacitive load assembly has a first input end, one second input and one the 3rd input, this first input end receives this first signal, this second input receives this secondary signal the 3rd input and receives a control signal, and wherein the capacitance of this capacitive load assembly changes with this control signal.

14, signal delay circuit according to claim 13 is characterized in that, this capacitive load assembly includes three switches at least.

15, signal delay circuit according to claim 13 is characterized in that, this capacitive load assembly is a NAND door.

16, signal delay circuit according to claim 15 is characterized in that, under lower state, the N transistor npn npn in this NAND door is for closing.

17, signal delay circuit according to claim 15 is characterized in that, when this first signal equated haply with this secondary signal, the N transistor npn npn in this NAND door was in the state of conducting slightly.

18, signal delay circuit according to claim 13 is characterized in that, this capacitive load assembly is a NOR door.

19, signal delay circuit according to claim 13 is characterized in that, this first input signal and this second input signal are differential input signal.

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