CN103105514B - A kind of oscillograph with digital meter frequency function - Google Patents
A kind of oscillograph with digital meter frequency function Download PDFInfo
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Abstract
The invention provides a kind of oscillograph with digital meter frequency function, including: data sampling unit, numeral comparing unit, trigger control unit, samples storage unit；Also include frequency counting unit, for producing the time gate signal with gate time according to system clock；And according to comparing in gate time, gate time, the very first time between the total degree of data variation of data, the initial time of gate time and the data variation comparing data in gate time is poor, the second time difference between the finish time of gate time and the final data change comparing data in gate time, produces meter result frequently.The frequency counting of the present invention considers very first time difference and the second time difference, therefore, it is possible to the measurement error of frequency is reduced to zero, improves oscillographic meter frequency precision；Additionally, due to do not use analog comparater, peripheral analog trigger circuitry, decrease hardware cost.
Description
Technical field
The present invention relates to test, field of measuring technique, particularly relate to a kind of oscillograph with digital meter frequency function.
Background technology
Oscillograph is the electronic measuring instrument that a kind of purposes is quite varied, and current oscillograph mainly includes two kinds: analog oscilloscope and digital oscilloscope.With reference to Fig. 1, it is shown that the structural representation of a kind of analog oscilloscope in prior art.The data sampling unit 101 of oscillograph 100 carries out data sampling to measured signal a, it is thus achieved that digitized sampled data b；Analog comparater 102 compares process to measured signal a, measured signal a is converted to the comparison signal c that height changes, is a square-wave signal；Trigger control unit 103 produces a Trig control signal d according to this comparison signal c, and sampled data b is stored by samples storage unit 104 according to Trig control signal d, produces the waveform video data e shown for waveform.
With reference to Fig. 2, it is shown that the structural representation of a kind of digital oscilloscope in prior art.The data sampling unit 201 of oscillograph 200 carries out data sampling to measured signal a, it is thus achieved that digitized sampled data b；Digital comparator 202 carries out level comparison process to sampled data b, obtain and digitized compare data f, trigger control unit 203 compares data f according to this and produces a Trig control signal d, sampled data b is stored by samples storage unit 204 according to Trig control signal d, produces waveform video data e.
Along with technological progress, oscillographic function is more and more perfect, and some oscillograph also can possess a meter frequency function, and its Main Function is to facilitate user while observation signal, can obtain the frequency of measured signal accurately.With reference to Fig. 3, it is shown that a kind of oscillographic structural representation with meter frequency function in prior art.Oscillograph 300 includes data sampling unit 301, analog comparater 302, trigger control unit 303, samples storage unit 304 and frequency counting unit 305, and frequency counting unit 305 has T gate time for producing one0Time gate signal, and the comparison signal c that analog comparater 302 produces is carried out frequency counting, wherein, at T gate time according to time gate signal0Initial time, start frequency counting；At T gate time0Finish time, terminate frequency counting, final meter frequency result g produced is the frequency values of measured signal a.With reference to Fig. 4, for the principle schematic of the frequency counting of prior art.
In conjunction with Fig. 3, frequency counting unit 305 generally uses the method for meter frequency and carries out frequency counting.As shown in Fig. 4 (a), for using meter frequency method to carry out the principle schematic of frequency counting.The method uses comparison signal c as meter frequency clock, has had how many meter frequency clocks in calculating certain gate time, and reference clock is used for producing time gate signal, when calculating frequency according to formula: the number of meter frequency result g=meter frequency clock/gate time T0.It can be seen that owing to time gate signal is asynchronous with comparison signal c, the time of synchronization is T from Fig. 4 (a), T gate time therefore can be caused0It it not the integral multiple of comparison signal c.Owing to the method does not accounts for these two sections of time differences of T1, T2, final meter frequency result g produced has the frequency error of 0～1.Wherein, T1 is T gate time0In, first rising edge of comparison signal c to T gate time0Initial time between time difference；T2 is T gate time0In, last trailing edge of comparison signal c to T gate time0Finish time between time difference.
Additionally, a kind of frequency counting method counting week mode.As shown in Fig. 4 (b), for using meter week mode to carry out the principle schematic of frequency counting.The method uses a cycle of comparison signal c as T gate time0, utilize reference clock to go to calculate a cycle of comparison signal c, obtain final meter frequency result g according to this cycle.It can be seen that owing to comparison signal c is asynchronous with reference clock from Fig. 4 (b), therefore can cause cycle of comparison signal c is not the integral multiple of reference clock, and the cycle of the actual comparison signal c measured is T.Owing to not accounting for these two sections of time differences of T3, T4, equally, also can therefore bring the frequency error of 0～1.Wherein, T3 is T gate time0In, first rising edge of reference clock to T gate time0Initial time between time difference；T4 is T gate time0In, last trailing edge of reference clock to T gate time0Finish time between time difference.
It addition, the frequency counting method of a kind of equally accurate mode.As shown in Fig. 4 (c), for using equally accurate mode to carry out the principle schematic of frequency counting.The method using comparison signal c as clock, produce a sync gate time signal Tong Bu with comparison signal c, that there is sync gate time T ', then go to calculate the sync gate time T ' in sync gate time signal with reference clock, converse the frequency of comparison signal according to sync gate time T '.It can be seen that owing to sync gate time T ' is asynchronous with reference clock, the time of synchronization is T from Fig. 4 (c), therefore can cause sync gate time T ' is not the integral multiple of reference clock.Owing to not accounting for these two sections of time differences of T5, T6, equally, also can therefore bring the frequency error of 0～1.Wherein, in T5 is sync gate time T ', first rising edge of reference clock is to the time difference between the initial time of sync gate time T ', in T6 is sync gate time T ', and the time difference between last trailing edge of reference clock to the finish time of sync gate time T '.
It can be seen that all there is the trueness error that frequency calculates in above-mentioned three kinds of methods.
Summary of the invention
The technical problem to be solved is to provide a kind of oscillograph with digital meter frequency function, it is possible to increase oscillographic meter frequency precision.
In order to solve the problems referred to above, the invention discloses a kind of oscillograph with digital meter frequency function, including:
Data sampling unit, for carrying out digital sample according to a sampling clock to measured signal, it is thus achieved that sampled data；
Numeral comparing unit, for described sampled data carries out level comparison process, produces and compares data；
Trigger control unit, for according to the described data that compare, produces a Trig control signal；
Samples storage unit, for storing described sampled data according to described Trig control signal, produces the waveform video data shown for waveform；
Frequency counting unit, for producing a time gate signal with gate time according to a system clock；And the second time difference poor according to the very first time compared in described gate time, described gate time between the total degree of data variation of data, the initial time of described gate time and first data variation comparing data in described gate time, between the finish time of described gate time and last data variation comparing data in described gate time, produce meter frequency result.
Compared with prior art, the invention have the advantages that the present invention for the comparison data that the signal of frequency counting is numeral comparing unit output, it counts not as clock, but compares the data variation of data by judgement and carry out count frequency；Simultaneously, consider that the very first time between the initial time of gate time and first data variation comparing data in gate time is poor and the second time difference between the finish time of gate time and last data variation comparing data in gate time, the measurement error of frequency is reduced to zero, improves oscillographic meter frequency precision.
Illustrating as one, frequency counting unit of the present invention is made up of a PLD.Present invention saves complete machine cost, completely dispense with analog comparater, peripheral analog trigger circuitry, on the basis of existing digital oscilloscope, only by existing logical block, such as FPGA, so that it may realize high-precision digital frequency meter, decrease hardware cost, reduce hardware fault risk.
Illustrating as one, data sampling unit of the present invention carries out digital sample for measured signal to multiple passages respectively, it is thus achieved that corresponding multi-channel sampling data；Described numeral comparing unit, for respectively described multi-channel sampling data being carried out level comparison process, produces corresponding multichannel comparative result, and selects the comparison data that wherein a road comparative result exports as described data comparing unit from described multichannel comparative result.
As a kind of example, in this illustration, described data sampling unit is additionally operable to an outside signal that introduces carried out signal comparison process, and in response to the different over-sampling clock of N number of phase place, result after described signal comparison process is carried out digital sample, produces over-sampling result；Described numeral comparing unit is additionally operable to select described over-sampling result to compare data as described.
As a kind of modification, in this example, described system clock and described sampling clock, over-sampling clock are Tong Bu；The frequency of described sampling clock is the integral multiple of the frequency of described system clock；The frequency of described over-sampling clock is the integral multiple of the frequency of described system clock.
Illustrating as one, frequency counting unit of the present invention includes:
Data variation searches module, for comparing data and described system clock according to described, obtains the described monocycle data variation number of times comparing data successively；
First phase inverter, for described time gate signal is carried out anti-phase process, produces a reset signal；
Number of times accumulator, for according to described time gate signal and reset signal, carries out accumulation operations to the described monocycle data variation number of times comparing data, it is thus achieved that compare the total degree of the data variation of data in described gate time.
As a kind of example, in this illustration, described data variation is searched module and is additionally operable to record one group of first preset data, and described first preset data include: the different types of monocycle data variation number of times comparing data and correspondence thereof；Described data variation is searched module and is used for comparing data and described system clock according to described, obtains described monocycle data variation number of times from described first preset data.
As a kind of example, in this illustration, described number of times accumulator, when described time gate signal is high level, carries out accumulation operations to described monocycle data variation number of times；When described time gate signal is converted into low level by high level, the result of described monocycle data variation number of times accumulation operations is exported as the total degree of data variation；When described reset signal is high level, the result of described monocycle data variation number of times accumulation operations is reset reset.
Illustrating as one, frequency counting unit of the present invention includes:
Module is searched at first edge, for comparing data according to described, in a system clock cycle, produce an expression and compare the first edge position information of first data variation of data and the spacing of described system clock cycle initial time, and produce an id signal indicating whether data variation simultaneously；
Pretreatment module, for carrying out level conversion process according to described id signal and described time gate signal, produces one and enables signal；
Second phase inverter, for described time gate signal is carried out anti-phase process, produces a reset signal；
First accumulator, for according to described enable signal and reset signal, carries out accumulation operations, and it is poor to obtain the described very first time according to the result of this accumulation operations described first edge position information.
As a kind of example, in this illustration, described first edge is searched module and is additionally operable to record one group of second preset data, and described second preset data include: different types of compares data and the first edge position information of correspondence thereof, whether have the mark of data variation；Described first edge is searched module and is used for comparing data and described system clock according to described, produces described first edge position information and described id signal from described second preset data.
As a kind of example, in this illustration, described pretreatment module includes:
Latch, is low level latch signal for one initial value of output, and when described id signal has been expressed as data variation for the first time within described gate time, described latch signal is converted to high level output；
Latch inverters, for described latch signal is carried out anti-phase process, produces an inversion signal；
Logical AND module, for described time gate signal and inversion signal are carried out logic and operation operation, produces described enable signal.
As a kind of example, in this illustration, described first accumulator includes:
Primary importance adds up submodule, for according to described enable signal and reset signal, described first edge position information is carried out accumulation operations, it is thus achieved that first adds up position；
The very first time obtains submodule, is used for one of frequency of the frequency according to described sampling clock and over-sampling clock, and it is poor that position of adding up described first is converted to the described very first time.
As a kind of modification, in this example, the described primary importance submodule that adds up, when described enable signal is high level, carries out accumulation operations to described first edge position information；When described enable signal is converted into low level by high level, using the result of the first edge position information accumulation operations as first add up position output；When reset signal is high level, the result of the first edge position information accumulation operations is reset reset.
Illustrating as one, described frequency counting unit of the present invention includes:
Module is searched at second edge, for comparing data according to described, in a system clock cycle, produce an expression and compare second edge position information of last data variation of data and the spacing of described system clock cycle finish time, and when relatively data have data variation, produce an override signal simultaneously；
3rd phase inverter, for described time gate signal is carried out anti-phase process, produces a reset signal；
Second accumulator, for according to described time gate signal, reset signal and override signal, carries out accumulation operations, and obtains described second time difference according to the result of accumulation operations described second edge position information.
As a kind of example, in this illustration, described second edge is searched module and is additionally operable to record one group of the 3rd preset data, and described 3rd preset data include: different types of compares data and the second edge position information of correspondence thereof, whether have the mark of data variation；Described second searches module is used for comparing data and described system clock according to described, produces described second edge position information and described override signal from described 3rd preset data.
As a kind of example, in this illustration, described second accumulator includes:
The second position adds up submodule, for according to described time gate signal, reset signal and override signal, described second edge placement value is carried out accumulation operations, it is thus achieved that second adds up position；
Second time obtained submodule, was used for one of frequency of the frequency according to described sampling clock and over-sampling clock, and position of adding up described second is converted to described second time difference.
As a kind of modification, in this example, the described second position submodule that adds up, when time gate signal is high level, carries out accumulation operations to described second edge position information；When getting described override signal, the result of the second edge position information accumulation operations is updated to the second edge position information simultaneously produced with described override signal；When described time gate signal is converted into low level by high level, using the result of the second edge position information accumulation operations as second add up position output；When reset signal is high level, the result of the second edge position information accumulation operations is reset reset.
Illustrate as one, frequency counting unit of the present invention is poor according to the very first time compared in described gate time, described gate time between the total degree of data variation in data " 10 ", the initial time of described gate time and first data variation " 10 " comparing data in described gate time, the second time difference between the finish time of described gate time and last data variation " 10 " comparing data in described gate time, produces described meter frequency result.
Illustrate as one, frequency counting unit of the present invention is poor according to the very first time compared in described gate time, described gate time between the total degree of data variation in data " 01 ", the initial time of described gate time and first data variation " 01 " comparing data in described gate time, the second time difference between the finish time of described gate time and last data variation " 01 " comparing data in described gate time, produces described meter frequency result.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of analog oscilloscope in prior art；
Fig. 2 is the structural representation of a kind of digital oscilloscope in prior art；
Fig. 3 is a kind of oscillographic structural representation with meter frequency function in prior art；
Fig. 4 is the principle schematic of the frequency counting of prior art；
Fig. 5 is the structural representation of a kind of oscillograph embodiment with digital meter frequency function of the present invention；
Fig. 6 is the structural representation of a kind of illustration of oscillograph embodiment of the present invention.
Fig. 7 is the schematic diagram of frequency counting of the present invention.
Fig. 8 is the structural representation of the frequency counting unit described in the embodiment of the present invention；
Fig. 9 is the structural representation of the data variation enumerator described in the embodiment of the present invention；
Figure 10 is the structural representation of the very first time enumerator described in the embodiment of the present invention；
Figure 11 is the structural representation of the second time counter described in the embodiment of the present invention.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, the present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings.
With reference to Fig. 5, showing the structural representation of a kind of oscillograph embodiment with digital meter frequency function of the present invention, the oscillograph 500 that the present embodiment proposes includes: data sampling unit 501, numeral comparing unit 502, trigger control unit 503, samples storage unit 504 and frequency counting unit 505.
Data sampling unit 501, it carries out digital sample according to a sampling clock h to measured signal a, it is thus achieved that sampled data b；
Numeral comparing unit 502, it carries out level comparison process, produces and compare data f sampled data b；
Trigger control unit 503, it produces a Trig control signal d according to comparing data f；
Samples storage unit 504, sampled data b is stored by it according to Trig control signal d, produces the waveform video data e shown for waveform；
In conjunction with Fig. 7, frequency counting unit 505 produces one according to a system clock i and has T gate time0Time gate signal j；And according to T gate time0, T gate time0Inside compare the total degree m of the data variation of data f, T gate time0Initial time with gate time T0Inside compare the very first time difference t1, T gate time between first data variation of data f0Finish time with gate time T0Inside compare the second time difference t2 between last data variation of data f, produce meter frequency result g.
Measured signal a described in the present embodiment is by oscillographic passage input to data sampling unit 501, and data sampling unit 501 is equivalent to analog-digital converter ADC, and it is simulated the conversion of numeral according to sampling clock h to measured signal a, it is achieved data sampling；Afterwards, during sampled data b obtained is respectively sent to numeral comparing unit 502 and samples storage unit 504 by data sampling unit 501.General, before data sampling unit 501, also have an analog front circuit, process for realizing a series of operation of the buffering to measured signal a, decay, bandwidth restriction etc..Implementing of analog front circuit can use multiple design, is not repeating.
Numeral comparing unit 502 is generally made up of a series of viscous comparators, and each viscous comparator can be that 8bit compares precision, comparative level and viscous scope and all can arrange.Two physics comparative levels can be obtained after comparative level and viscous range combinations, be referred to as the gentle lower level that powers on.If sampled data b (8bit) of viscous comparator input is more than upper level, then viscous comparator output logical one (1bit)；If sampled data b of input is less than lower level, then viscous comparator output logical zero (1bit).
Frequency counting unit 505 produces according to system clock i has T gate time0Time gate signal j, say, that desynchronize start time of gate time and finish time with system clock, can be that rising edge synch or the trailing edge of system clock synchronizes.User can be as desired to arrange T gate time0Length, for example, it is possible to be set to: 100ms, 500ms, 1s etc..If T gate time0Shorter, then the meter frequency speed of frequency counting unit 505；If T gate time0Longer, then meter frequency result g that frequency counting unit 505 obtains can be more accurate, this is because one gate time T0In, frequency change frequency is many, then, by average measured signal a (the actual frequency error brought for comparing data f) self to shake measured, the error of meter frequency result g recorded after Ping Jun is the least, it doesn't matter for the measurement error of frequency error and frequency, and frequency error is the error that test signal self brings, the error that it produces during being not belonging to measure.In frequency measurement, frequency counting unit 505 is according to T gate time0, T gate time0Inside comparing the total degree m of the data variation of data f, very first time difference t1, the second time difference t2, produce meter frequency result g, concrete frequency calculation method is:
1) when the total degree m of data variation is less than or equal to 1, meter frequency result g=0；
2) when the total degree m of data variation is more than 1, meter frequency result g=(the total degree m-1 of data variation)/(gate time T0-very first time difference t1-the second time difference t2).
One of difference with the prior art of the present invention is, the comparison signal c that analog comparater is exported by prior art as clock, comparison signal c and T gate time0Being asynchronous relationship, therefore cannot calculate T1, T2, and the present invention is for the comparison data that the signal of frequency counting is numeral comparing unit output, it counts not as clock, but compares the data variation of data by judgement and carry out count frequency；Additionally, the present invention considers T gate time0Initial time with gate time T0Inside compare the very first time difference t1 and T gate time between first data variation of data f0Finish time with gate time T0Inside comparing the second time difference t2 between last data variation of data f, by the measurement error of frequency, i.e. meter frequency error is reduced to zero, improves oscillographic meter frequency precision.
It is understandable that, frequency counting unit 505 is actual, and measure is the frequency comparing data f, but, owing to comparing data f and carried out sampling by measured signal a, level compares and obtains, therefore, the frequency measuring comparison data f obtained is equivalent to the frequency of measured signal a.
It should be noted that, described oscillograph 500 can also include a central control unit, for to data sampling unit 501, numeral comparing unit 502, trigger control unit 503, samples storage unit 504 and frequency counting unit 505 is controlled and parameter arrange, such as, comparative level and the viscous scope of numeral comparing unit 502 are set, the generation of regulating gate time signal j, meter frequency result g that reading frequency counting unit 505 produces, control Wave data, the display etc. of meter frequency result.
As an illustration, the frequency counting unit 505 described in the present embodiment can be made up of a PLD.As, can be made up of devices such as FPGA or CPLD.In addition, this PLD can compare with integrated digital sampling, level, triggering controls, samples storage and to data sampling, the control function of the operation such as level compares, samples storage, waveform show, various functions are integrated in one, both reduce the volume of digital oscilloscope, save again cost.
The meter frequency method of prior art is required to, by analog comparater, the measured signal of input is converted to the comparison signal that height changes, use the meter frequency method of simulation, peripheral circuit must be had before its analog comparater, such as analog trigger circuitry, it brings extra hardware cost, also increases the risk of hardware fault simultaneously.Present invention saves complete machine cost, completely dispense with analog comparater, peripheral analog trigger circuitry, on the basis of existing digital oscilloscope, only by existing logical block, such as FPGA, so that it may realize high-precision digital frequency meter, decrease hardware cost, reduce hardware fault risk.
As an illustration, the data sampling unit 501 described in the present embodiment can carry out digital sample to the measured signal a of multiple passages respectively, it is thus achieved that corresponding multi-channel sampling data b；Numeral comparing unit 502 carries out level comparison process to multi-channel sampling data b respectively, produces corresponding multichannel comparative result k, and selects comparison data f that wherein a road comparative result exports as data comparing unit 501 from multichannel comparative result k.
With reference to Fig. 6, for the structural representation of a kind of illustration of oscillograph embodiment of the present invention.Data sampling unit 501 includes that ADC1 and ADC2, ADC1 carry out digital sample to the measured signal a1 of passage 1, it is thus achieved that road sampled data b1, and ADC2 carries out digital sample to the measured signal a2 of passage 2, it is thus achieved that another road sampled data b2.Numeral comparing unit 502 includes that two numerals compare subelement 5021 and 5022, respectively sampled data b1 and sampled data b2 is carried out level comparison process, produces corresponding two-way comparative result k1 and k2；Numeral comparing unit 502 also includes a channel to channel adapter 5023, for selecting frequency counting and triggering the data source controlled, i.e. select a wherein road comparative result from two-way comparative result k1 and k2, as comparison data f of data comparing unit 502 output.
Sampled data b1 or sampled data b2 are stored by samples storage unit 504 according to Trig control signal d.It should be noted that can also have an intertexture control unit between data sampling unit 501 and samples storage unit 504, sampled data b1 and b2 being interleaved combination, sampled data b1 after interleaving combinations and b2 are stored by samples storage unit 504.Fig. 6 is illustrated as a example by the oscillograph of two passages, and the oscillograph of two or more passage can be with cross-reference.
Illustrate as another, data sampling unit 501 described in the present embodiment is additionally operable to an outside signal p that introduces is carried out signal comparison process, and in response to the different over-sampling clock q of N number of phase place, result after signal comparison process is carried out digital sample, producing over-sampling result r, numeral comparing unit 502 selects over-sampling result r as comparing data f.
With reference to Fig. 6, data sampling unit 501 can also include an external trigger comparator 5011 and an oversampled subband unit 5012, external trigger comparator 5011 is by signal comparison process, outside introduces signal p being changed into the external trigger signal s that edge is precipitous, outside introducing signal p can be the signal etc. of external clock, circuit under test.Oversampled subband unit 5012, in response to the different over-sampling clock q of N number of phase place, carries out Parallel Digital sampling to external trigger signal s, it is thus achieved that N passes by sampled data, afterwards, according to the time sequencing of Parallel Digitalization sampling, N is passed by sampled data and carries out cross arrangement combination, produce over-sampling result r；Channel to channel adapter 5023 can select comparison data f that over-sampling result r exports as data comparing unit 502, and trigger control unit 503 can produce Trig control signal d, it is achieved external trigger function according to comparison data f obtained by over-sampling result r.Frequency counting unit 505 compares data f according to this and carries out frequency counting.Same, introduced signal p by outside and carry out over-sampling etc. owing to this compares data f and process and obtain, therefore, should in the case of, the frequency measuring comparison data f obtained is equivalent to the outside frequency introducing signal p.
From this illustration it can be seen that the frequency of measured signal a both can be counted by frequency counting unit 505, it is also possible to the frequency of the outside introducing signal p for realizing external trigger is counted.
As a kind of example, clock q is Tong Bu for the system clock i described in this illustration and sampling clock h, over-sampling；The frequency of sampling clock h can be the integral multiple of the frequency of system clock i；The frequency of over-sampling clock q can be the integral multiple of the frequency of system clock i.
As a kind of example, the system clock i described in this illustration may refer to the total clock (namely process clock of PLD) within system of Oscillograph, then can produce sampling clock h and over-sampling clock q according to system clock i.Illustrate as another kind, system clock i of the present invention can not be the total clock within system of Oscillograph, system clock i is only used for producing time gate signal j, system clock i, sampling clock h, over-sampling clock q and all can produce according to total clock of internal system.
As an illustration, with reference to Fig. 7 (a) and combine Fig. 5, the frequency counting unit 505 described in the present embodiment can be according to T gate time0, compare the total degree m of data variation in data f " 01 ", T gate time in gate time0Initial time with gate time T0Inside compare the very first time difference t1, T gate time between first data variation " 01 " of data f0Finish time with gate time T0Inside compare the second time difference t2 between last data variation " 01 " of data f, produce meter frequency result g.Then, the rising edge that the mode shown in Fig. 7 (a) is equivalent to according to comparing data carries out frequency counting.
Illustrating as another, with reference to Fig. 7 (b) and combine Fig. 5, the frequency counting unit 505 described in the present embodiment can be according to T gate time0, compare the total degree m of data variation in data f " 10 ", T gate time in gate time0Initial time with gate time T0Inside compare the very first time difference t1, T gate time between first data variation " 10 " of data f0Finish time with gate time T0Inside compare the second time difference t2 between last data variation " 10 " of data f, produce meter frequency result g.Then, the trailing edge that the mode shown in Fig. 7 (b) is equivalent to according to comparing data carries out frequency counting.
As an illustration, as shown in Figure 8, the frequency counting unit 505 described in the present embodiment may include that generator gate time 81, and it produces according to system clock i has T gate time0Time gate signal j；Data variation enumerator 82, it, according to comparing data f, system clock i and time gate signal j, obtains T gate time0Inside compare the total degree m of the data variation of data f；Very first time enumerator 83, it, according to comparing data f, system clock i and time gate signal j, obtains T gate time0Initial time with gate time T0Inside compare the very first time difference t1 between first data variation of data f；Second time counter 84, it, according to comparing data f, system clock i and time gate signal j, obtains T gate time0Finish time with gate time T0Inside compare the second time difference t2 between last data variation of data f；Frequency counter 85, it produces meter frequency result g according to the total degree m of data variation, very first time difference t1 and the second time difference t2.
In this illustration, as it is shown in figure 9, data variation enumerator 82 specifically may include that
Data variation searches module 821, and it obtains, according to comparing data f and system clock i, the monocycle data variation frequency n comparing data f successively；
First phase inverter 822, it carries out anti-phase process, produces reset signal y time gate signal j；
Number of times accumulator 823, it, according to time gate signal j and reset signal y, carries out accumulation operations to the monocycle data variation frequency n comparing data f, it is thus achieved that gate time T0Inside compare the total degree m of the data variation of data f.
As a kind of example, in illustration, data variation is searched module 821 and is additionally operable to record one group of first preset data, and described first preset data include: the different types of monocycle data variation number of times comparing data and correspondence thereof；Data variation lookup module 821, according to comparing data f and system clock i, obtains monocycle data variation frequency n from described first preset data.Described first preset data can be presented in tables of data.
Data instance is compared with a system clock cycle 8bit, as shown in table 1, by the one group of first preset data recorded according to data variation " 01 " (rising edge) meter frequency, previous it is classified as: the data that last data (last bit) of previous system clock cycle and the comparison data in current system time clock cycle are formed, it from left to right arranges according to time order and function order, and rear one is classified as and the different types of monocycle data variation number of times compared corresponding to data.As example, table 1 only gives a portion of the first preset data, and remaining data is omitted herein.
Table 1
In this example, when opening meter frequency function, data variation searches module 821 successively in each system clock cycle, last Bit data and the comparison data in current system time clock cycle according to previous system clock cycle, first preset data make a look up, obtain monocycle data variation frequency n corresponding thereto, and input to number of times accumulator 823.Time gate signal j is controlled as the enable signal of number of times accumulator 823, beginning and end to number of times accumulator 823 accumulation operations, according to reset signal y, the result of accumulation operations is reset reset simultaneously.
As a kind of example, in this illustration, number of times accumulator 823 (is equivalent to T gate time when time gate signal j is high level0Time period), monocycle data variation frequency n is carried out accumulation operations；(T gate time is equivalent to when time gate signal j is converted into low level by high level0Finish time), preserve monocycle data variation frequency n accumulation operations result, as data variation total degree m export；When reset signal y is high level, the result of monocycle data variation frequency n accumulation operations is reset reset.As another kind of example, number of times accumulator 823 can also carry out accumulation operations when time gate signal j is low level to monocycle data variation frequency n；When time gate signal j is converted into high level by low level, the result of this accumulation operations is exported as the total degree m of data variation；When reset signal y is low level, the result of this accumulation operations is reset reset.
In this illustration, as shown in Figure 10, very first time enumerator 83 specifically may include that
Module 831 is searched at first edge, for according to comparing data f, in a system clock cycle, produce an expression and compare the first edge position information x1 of first data variation of data f and the spacing of this system clock cycle initial time, and produce an id signal u indicating whether data variation simultaneously；
Pretreatment module 832, for carrying out level conversion process according to id signal u and time gate signal j, produces one and enables signal v；
Second phase inverter 833, for time gate signal j is carried out anti-phase process, produces reset signal y；
First accumulator 834, for according to enabling signal v and reset signal y, carries out accumulation operations, and obtains very first time difference t1 according to the result of this accumulation operations the first edge position information x1.
As a kind of example, in illustration, first edge is searched module 831 and is additionally operable to record one group of second preset data, and described second preset data include: different types of compares data and the first edge position information of correspondence thereof, whether have the mark of data variation；First edge lookup module 831, according to comparing data f and system clock i, produces the first edge position information x1 and id signal u from described second preset data.Described second preset data can be presented in tables of data.
Data instance is compared with a system clock cycle 8bit, as shown in table 2, by the one group of second preset data recorded according to data variation " 01 " (rising edge) meter frequency, first is classified as: the data that last data (last bit) of previous system clock cycle and the comparison data in current system time clock cycle are formed, it from left to right arranges according to time order and function order, second is classified as and different types of the first edge position information compared corresponding to data, 3rd is classified as the mark whether having data variation, in this example, represent there is no data variation with mark " 0 ", data variation is indicated with mark " 1 ".As example, table 2 only gives a portion of the second preset data, and remaining data is omitted herein.
Table 2
In this example, with reference to Figure 10, when opening meter frequency function, module 831 is searched successively in each system clock cycle in first edge, last Bit data and the comparison data in current system time clock cycle according to previous system clock cycle, second preset data make a look up, obtains the first edge position information x1 corresponding thereto, and input to the first accumulator 834；Additionally, by the lookup in the second preset data, while producing the first edge position information x1, also can produce an id signal u indicating whether data variation, and by id signal u input to pretreatment module 832.Pretreatment module 832 carries out level conversion process according to id signal u and time gate signal j, produces a beginning to the accumulation operations of the first accumulator and enable signal v that result is controlled.
As a kind of example, as shown in Figure 10, in this illustration, pretreatment module 832 includes:
Latch 1001, its one initial value of output is low level latch signal w, and at T gate time0When interior id signal u has been expressed as data variation for the first time, latch signal w is converted to high level output；
Latch inverters 1002, it carries out anti-phase process, produces an inversion signal z latch signal w；
Logical AND module 1003, it carries out logic and operation operation, produces and enable signal v time gate signal j and inversion signal z.
Latch 1001 receives the first edge and searches the id signal u that module 831 produces, and output latch signal w accordingly.Under each system clock cycle, id signal u may indicate data variation, it is also possible to represents do not have data variation.At T whole gate time0In, when latch id signal u has been expressed as data variation for the first time, initial value is that low level latch signal w is converted into high level output by latch 1001, that is, just latch in the moment of first data variation (being equivalent to first rising edge or trailing edge), and always remain as high level output.After latch inverters 1002 process anti-phase to latch signal w (i.e. level reversion), produce inversion signal z.Logical AND module 1003 carries out logic and operation operation to time gate signal j and inversion signal z, and the enable signal v of generation can ensure that when time gate signal j and inversion signal z is high level, just controls the first accumulator 834 and carries out accumulation operations.
As a kind of example, the first accumulator 814 may include that
Primary importance adds up submodule, and it, according to enabling signal v and reset signal y, carries out accumulation operations to the first edge position information x1, it is thus achieved that first adds up position；
The very first time obtains submodule, one of the frequency of its foundation sampling clock and the frequency of over-sampling clock, and position of adding up first is converted to very first time difference t1.
In this example, the first edge is searched exactly the first edge position information x1 that module 831 exports and is added up always by the add up effect of submodule of primary importance, until first data is only changed to, stops cumulative, and first finally drawn is added up position i.e. T gate time0Beginning to T gate time0Inside compare the position between first data variation of data f.As a kind of modification, in this example, the primary importance submodule that adds up, when enabling signal v and being high level, carries out accumulation operations to the first edge position information x1；Enable signal v be converted into low level by high level time, using the result of the first edge position information x1 accumulation operations as first add up position output；When reset signal y is high level, the result of the first edge position information x1 accumulation operations is reset reset.
The very first time obtain submodule carry out the position conversion to the time, will first add up position be converted to the very first time difference t1.Concrete, obtained by measured signal a if comparing data f, then convert according to the frequency of sampling clock h, i.e. very first time difference t1=first adds up position * (frequency of 1/ sampling clock h)；If comparing data f to be introduced signal p by outside and obtain, then convert according to the frequency of over-sampling clock q, i.e. very first time difference t1=first adds up position * (frequency of 1/ over-sampling clock q).
In this illustration, as shown in figure 11, the second time counter 84 specifically may include that
Module 841 is searched at second edge, it is according to comparing data f, in a system clock cycle, produce an expression and compare second edge position information x2 of last data variation of data f and the spacing of this system clock cycle finish time, and when relatively data f have data variation, produce override signal L simultaneously；
3rd phase inverter 842, it carries out anti-phase process, produces reset signal y time gate signal j；
Second accumulator 843, it is according to time gate signal j, reset signal y and override signal L, the second edge position information x2 carries out accumulation operations, and obtains the second time difference t2 according to the result of accumulation operations.
As a kind of example, in illustration, second edge is searched module 841 and is additionally operable to record one group of the 3rd preset data, and described 3rd preset data include: different types of compares data and the second edge position information of correspondence thereof, whether have the mark of data variation；Second searches module foundation compares data f and system clock i, produces the second edge position information x2 and override signal L from the 3rd preset data.Described 3rd preset data can be presented in tables of data.
Data instance is compared with a system clock cycle 8bit, as shown in table 3, by one group of the 3rd preset data recorded according to data variation " 01 " (rising edge) meter frequency, first is classified as: the data that last data (last bit) of previous system clock cycle and the comparison data in current system time clock cycle are formed, it from left to right arranges according to time order and function order, second is classified as and different types of the second edge position information compared corresponding to data, 3rd is classified as the mark whether having data variation, in this example, represent there is no data variation with mark " 0 ", data variation is indicated with mark " 1 ".As example, table 3 only gives a portion of the 3rd preset data, and remaining data is omitted herein.
Table 3
In this example, with reference to Figure 11, when opening meter frequency function, module 841 is searched successively in each system clock cycle in second edge, comparison data and last Bit data of previous system clock cycle according to the current system time clock cycle, 3rd preset data make a look up, obtains the second edge position information x2 corresponding thereto, and input to the second accumulator 843；In addition, by the lookup in the second preset data, if under the current system time clock cycle, when judging that comparing data f has data variation, while producing the second edge position information x2, also can produce override signal L, then the second edge position information x2 and id signal u can be simultaneously entered to the second accumulator 843.Second accumulator 843, according to time gate signal j, reset signal y and override signal L, carries out accumulation operations, and obtains the second time difference t2 according to the result of this accumulation operations the second edge position information x2.
As a kind of example, the second accumulator 843 may include that
The second position adds up submodule, and it, according to time gate signal j, reset signal y and override signal L, carries out accumulation operations to the second edge placement value x2, it is thus achieved that second adds up position；
Second time obtained submodule, and one of the frequency of its foundation sampling clock h and the frequency of over-sampling clock q, position of adding up second is converted to the second time difference t2.
In this example, the add up effect of submodule of the second position is through searching the second edge the second edge position information x2 of module 841 output and carries out accumulation operations, it is thus achieved that gate time T0End with gate time T0Inside comparing the position between last data variation of data f, i.e. second adds up position.Wherein, if comparing data f do not have data variation, then the second position submodule that adds up carries out accumulation operations always；If comparing data f have data variation, then the second position add up submodule also can according to override signal L, heavy duty accumulation operations result.As a kind of modification, in this example, the second position submodule that adds up (is equivalent to T gate time when time gate signal j is high level0Time period), the second edge position information x2 is carried out accumulation operations；When getting override signal, the result of the second edge position information x2 accumulation operations is updated to the second edge position information x2 simultaneously produced with override signal；(T gate time is equivalent to when time gate signal j is converted into low level by high level0Finish time), preserve the result of the second edge position information x2 accumulation operations, as second add up position output；When reset signal is high level, the result of the second edge position information x2 accumulation operations is reset reset.
Second time obtained submodule and carries out the position conversion to the time, will be converted to the second time difference t2 in the second position of adding up.Concrete, obtained by measured signal a if comparing data f, then convert according to the frequency of sampling clock h, the i.e. second time difference t2=second adds up position * (frequency of 1/ sampling clock h)；If comparing data f to be introduced signal p by outside and obtain, then converting according to the frequency of over-sampling clock q, the i.e. second time difference t2=second adds up position * (frequency of 1/ over-sampling clock q).
It should be noted that, in this illustration, in described first preset data, the second preset data and the 3rd preset data, the different types of data that compare of record are: the data that last data (last bit) of previous system clock cycle and the comparison data in current system time clock cycle are formed.This kind of recording mode is able to accurately to judge in the comparison data in current system time clock cycle whether have data variation.As a example by the judgement of data variation " 01 ", in some cases, such as, the comparison data in current system time clock cycle are 11110000, if the comparison data of previous system clock cycle are 00000000, then the comparison data in current system time clock cycle have data variation " 01 ", have a rising edge；If previous cycle data is 11111111, then the comparison data in current system time clock cycle just do not have data variation " 01 ", do not have rising edge.Therefore, it may be judged whether have data variation to also need to last data according to previous system clock cycle.
As a kind of example, in this illustration, first phase inverter the 822, second phase inverter 833 and the 3rd phase inverter 842 can share same public phase inverter, thus reached the purpose economized on resources.
Below, lift a concrete example, the detailed description of the invention of the present invention is introduced.In this example, measured signal a is carried out frequency counting.Wherein, sampling clock h is 1GHz, and over-sampling clock q is 1GHz, and system clock i is 125MHz, and the parallel width comparing data f is 8.As a example by the rising edge frequency counting method shown in Fig. 7 (a), in conjunction with Fig. 9, within the first systematic clock cycle, comparing data f is 01100110, data variation is searched mould 821 and is passed through look-up table 1, and the monocycle data variation number of times that can obtain correspondence is 2；In second system clock cycle, relatively data f are 01100110, module 821 is searched by data variation, the monocycle data variation number of times that can obtain correspondence is similarly 2, by that analogy, the accumulation operations of number of pass times accumulator 823, the cycle data change frequency that placed an order by 5 system clock cycles adds up, and obtains T whole gate time0Inside compare the total degree m, m=2+2+2+2+2=10 of the data variation of data f.
In conjunction with Figure 10, the first edge lookup module 831 is according to the comparison data 01100110 in the first systematic clock cycle, and by look-up table 2, the first edge position information of generation is 1, and produces the id signal u indicating data variation simultaneously.First accumulator 834, according to enabling signal v and reset signal y, carries out accumulation operations to the first edge position information, and final the first position of adding up obtained is 1；Further, according to the frequency of sampling clock h, position of adding up first is converted to very first time difference t1:
T1=1* (1/1GHz)=1ns.
In conjunction with Figure 11, the second edge lookup module 841 is according to the comparison data 01100110 in last system clock cycle, and by look-up table 3, the second edge position information of generation is 3, has data variation owing to this compares data, produces override signal L the most simultaneously；The accumulation result of before 4 system clock cycles is updated to 3 according to override signal L by the second accumulator again, and final the first position of adding up obtained is 3；Further, according to the frequency of sampling clock h, position of adding up second is converted to the second time difference t2:
T2=3* (1/1GHz)=3ns.
Meter frequency result g then finally obtained
=(the total degree m-1 of data variation)/(gate time T0-very first time difference t1-the second time difference t2)
=(10-1)/(40ns-1ns-3ns)
=250MHz.
Described meter frequency result g is the frequency values of measured signal a, it can be seen that by means of the invention it is possible to obtain the frequency of measured signal a the most accurately.
Mainly being introduced in measured signal a frequency counting mode in the specific embodiment of the invention, the outside frequency counting introducing signal p can be the most cross-referenced.
Mainly being introduced in the frequency counting mode of data variation " 01 " (i.e. rising edge) in the specific embodiment of the invention, the frequency counting of data variation " 10 " (i.e. trailing edge) can be the most cross-referenced.
Above to a kind of oscillograph with digital meter frequency function provided by the present invention, it is described in detail, principle and the embodiment of the present invention are set forth by specific case used herein, and the explanation of above example is only intended to help to understand method and the core concept thereof of the present invention；Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, the most all will change, in sum, this specification content should not be construed as limitation of the present invention.
Claims (19)
1. there is an oscillograph for digital meter frequency function, including:
Data sampling unit, for carrying out digital sample according to a sampling clock to measured signal, it is thus achieved that sampled data；
Numeral comparing unit, for described sampled data carries out level comparison process, produces and compares data；
Trigger control unit, for according to the described data that compare, produces a Trig control signal；
Samples storage unit, for storing described sampled data according to described Trig control signal, produces the waveform video data shown for waveform；
It is characterized in that, also include:
Frequency counting unit, for producing a time gate signal with gate time according to a system clock；And the second time difference poor according to the very first time compared in described gate time, described gate time between the total degree of data variation of data, the initial time of described gate time and first data variation comparing data in described gate time, between the finish time of described gate time and last data variation comparing data in described gate time, produce meter frequency result.
2. oscillograph as claimed in claim 1, it is characterised in that
Described frequency counting unit is made up of a PLD.
3. oscillograph as claimed in claim 1, it is characterised in that
Described data sampling unit carries out digital sample for measured signal to multiple passages respectively, it is thus achieved that corresponding multi-channel sampling data；
Described numeral comparing unit, for respectively described multi-channel sampling data being carried out level comparison process, produces corresponding multichannel comparative result, and selects the comparison data that wherein a road comparative result exports as described data comparing unit from described multichannel comparative result.
4. oscillograph as claimed in claim 3, it is characterised in that also include:
Described data sampling unit is additionally operable to an outside signal that introduces carried out signal comparison process, and in response to the different over-sampling clock of N number of phase place, the result after described signal comparison process carries out digital sample, produces over-sampling result；
Described numeral comparing unit is additionally operable to select described over-sampling result to compare data as described.
5. the oscillograph as described in any one of Claims 1-4, it is characterised in that
Described frequency counting unit includes:
Data variation searches module, for comparing data and described system clock according to described, obtains the described monocycle data variation number of times comparing data successively；
First phase inverter, for described time gate signal is carried out anti-phase process, produces a reset signal；
Number of times accumulator, for according to described time gate signal and reset signal, carries out accumulation operations to the described monocycle data variation number of times comparing data, it is thus achieved that compare the total degree of the data variation of data in described gate time.
6. oscillograph as claimed in claim 5, it is characterised in that
Described data variation is searched module and is additionally operable to record one group of first preset data, and described first preset data include: the different types of monocycle data variation number of times comparing data and correspondence thereof；
Described data variation is searched module and is used for comparing data and described system clock according to described, obtains described monocycle data variation number of times from described first preset data.
7. oscillograph as claimed in claim 5, it is characterised in that
Described number of times accumulator, when described time gate signal is high level, carries out accumulation operations to described monocycle data variation number of times；When described time gate signal is converted into low level by high level, the result of described monocycle data variation number of times accumulation operations is exported as the total degree of data variation；When described reset signal is high level, the result of described monocycle data variation number of times accumulation operations is reset reset.
8. the oscillograph as described in any one of Claims 1-4, it is characterised in that
Described frequency counting unit includes:
Module is searched at first edge, for comparing data according to described, in a system clock cycle, produce an expression and compare the first edge position information of first data variation of data and the spacing of described system clock cycle initial time, and produce an id signal indicating whether data variation simultaneously；
Pretreatment module, for carrying out level conversion process according to described id signal and described time gate signal, produces one and enables signal；
Second phase inverter, for described time gate signal is carried out anti-phase process, produces a reset signal；
First accumulator, for according to described enable signal and reset signal, carries out accumulation operations, and it is poor to obtain the described very first time according to the result of this accumulation operations described first edge position information.
9. oscillograph as claimed in claim 8, it is characterised in that
Described first edge is searched module and is additionally operable to record one group of second preset data, and described second preset data include: different types of compares data and the first edge position information of correspondence thereof, whether have the mark of data variation；
Described first edge is searched module and is used for comparing data and described system clock according to described, produces described first edge position information and described id signal from described second preset data.
10. oscillograph as claimed in claim 8, it is characterised in that
Described pretreatment module includes:
Latch, is low level latch signal for one initial value of output, and when described id signal has been expressed as data variation for the first time within described gate time, described latch signal is converted to high level output；
Latch inverters, for described latch signal is carried out anti-phase process, produces an inversion signal；
Logical AND module, for described time gate signal and inversion signal are carried out logic and operation operation, produces described enable signal.
11. oscillographs as claimed in claim 8, it is characterised in that
Described first accumulator includes:
Primary importance adds up submodule, for according to described enable signal and reset signal, described first edge position information is carried out accumulation operations, it is thus achieved that first adds up position；
The very first time obtains submodule, is used for one of frequency of the frequency according to described sampling clock and over-sampling clock, and it is poor that position of adding up described first is converted to the described very first time.
12. oscillographs as claimed in claim 9, it is characterised in that
The described primary importance submodule that adds up, when described enable signal is high level, carries out accumulation operations to described first edge position information；When described enable signal is converted into low level by high level, using the result of the first edge position information accumulation operations as first add up position output；When reset signal is high level, the result of the first edge position information accumulation operations is reset reset.
13. oscillographs as described in any one of Claims 1-4, it is characterised in that
Described frequency counting unit includes:
Module is searched at second edge, for comparing data according to described, in a system clock cycle, produce an expression and compare second edge position information of last data variation of data and the spacing of described system clock cycle finish time, and when relatively data have data variation, produce an override signal simultaneously；
3rd phase inverter, for described time gate signal is carried out anti-phase process, produces a reset signal；
Second accumulator, for according to described time gate signal, reset signal and override signal, carries out accumulation operations, and obtains described second time difference according to the result of accumulation operations described second edge position information.
14. oscillographs as claimed in claim 13, it is characterised in that
Described second edge is searched module and is additionally operable to record one group of the 3rd preset data, and described 3rd preset data include: different types of compares data and the second edge position information of correspondence thereof, whether have the mark of data variation；
Described second searches module is used for comparing data and described system clock according to described, produces described second edge position information and described override signal from described 3rd preset data.
15. oscillographs as claimed in claim 13, it is characterised in that
Described second accumulator includes:
The second position adds up submodule, for according to described time gate signal, reset signal and override signal, described second edge placement value is carried out accumulation operations, it is thus achieved that second adds up position；
Second time obtained submodule, was used for one of frequency of the frequency according to described sampling clock and over-sampling clock, and position of adding up described second is converted to described second time difference.
16. oscillographs as claimed in claim 15, it is characterised in that
The described second position submodule that adds up, when time gate signal is high level, carries out accumulation operations to described second edge position information；When getting described override signal, the result of the second edge position information accumulation operations is updated to the second edge position information simultaneously produced with described override signal；When described time gate signal is converted into low level by high level, using the result of the second edge position information accumulation operations as second add up position output；When reset signal is high level, the result of the second edge position information accumulation operations is reset reset.
17. oscillographs as claimed in claim 4, it is characterised in that
Described system clock and described sampling clock, over-sampling clock are Tong Bu；
The frequency of described sampling clock is the integral multiple of the frequency of described system clock；
The frequency of described over-sampling clock is the integral multiple of the frequency of described system clock.
18. oscillographs as claimed in claim 1, it is characterised in that
Described frequency counting unit is poor according to the very first time compared in described gate time, described gate time between the total degree of data variation in data " 10 ", the initial time of described gate time and first data variation " 10 " comparing data in described gate time, the second time difference between the finish time of described gate time and last data variation " 10 " comparing data in described gate time, produces described meter frequency result.
19. oscillographs as claimed in claim 1, it is characterised in that
Described frequency counting unit is poor according to the very first time compared in described gate time, described gate time between the total degree of data variation in data " 01 ", the initial time of described gate time and first data variation " 01 " comparing data in described gate time, the second time difference between the finish time of described gate time and last data variation " 01 " comparing data in described gate time, produces described meter frequency result.
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